74LVC2G74GM [NXP]
Single D-type flip-flop with set and reset; positive edge trigger; 单一的D- FL型IP- FL运算与置位和复位;上升沿触发
| 型号： | 74LVC2G74GM |
| 厂家： | 
NXP |
| 描述： | Single D-type flip-flop with set and reset; positive edge trigger |
| 文件： | 总20页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2G74
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 01 — 3 November 2005
Product data sheet
1. General description
The 74LVC2G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to
most advanced CMOS compatible TTL families.
The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.
This device is fully specified for partial power down applications using IOFF
.
The IOFF circuitry disables the output, preventing damaging backflow current through the
device when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2. Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ 5 V tolerant inputs for interfacing with 5 V logic
■ High noise immunity
■ Complies with JEDEC standard:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8-B/JESD36 (2.7 V to 3.6 V)
■ ±24 mA output drive (VCC = 3.0 V)
■ ESD protection:
◆ HBM EIA/JESD22-A114-C exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V
■ CMOS low power consumption
■ Latch-up performance exceeds 250 mA
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
Symbol Parameter
tPHL, tPLH propagation delay
CP to Q, Q
Conditions
Min
Typ
Max
Unit
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
-
-
-
-
3.5
3.0
3.0
280
-
-
-
-
ns
SD to Q, Q
ns
RD to Q, Q
ns
fmax
maximum input clock CL = 50 pF; VCC = 3.3 V
frequency
MHz
Ci
input capacitance
-
-
4.0
15
-
-
pF
pF
[1] [2]
CPD
power dissipation
capacitance
VCC = 3.3 V
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC
.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2G74DP
74LVC2G74DC
74LVC2G74GT
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
SOT765-1
SOT833-1
VSSOP8
XSON8
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
5. Marking
Table 3:
Marking
Type number
74LVC2G74DP
74LVC2G74DC
74LVC2G74GT
Marking code
V74
V74
V74
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
2 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
6. Functional diagram
7
SD
SD
7
Q
Q
5
3
2
1
D
S
5
3
D
Q
Q
1
2
6
C1
CP
CP
1D
R
FF
mnb140
RD
RD
6
mnb139
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Q
C
C
C
C
C
C
C
D
Q
C
RD
SD
CP
mna421
C
C
Fig 3. Logic diagram
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
3 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
7. Pinning information
7.1 Pinning
74
CP
D
1
2
3
4
8
7
6
5
V
CC
SD
RD
Q
Q
1
2
3
4
8
7
6
5
CP
D
V
CC
SD
RD
Q
74
GND
Q
GND
001aab658
Transparent top view
001aab659
Fig 4. Pin configuration TSSOP8 and
VSSOP8
Fig 5. Pin configuration XSON8
7.2 Pin description
Table 4:
Pin description
Symbol
CP
Pin
1
Description
clock input (LOW-to-HIGH, edge-triggered)
data input
D
2
Q
3
complement flip-flop output
ground (0 V)
GND
Q
4
5
true flip-flop output
RD
SD
6
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
7
VCC
8
8. Functional description
8.1 Function table
[1]
Table 5:
Function table for asynchronous operation
Input
SD
L
Output
RD
H
CP
X
D
X
X
X
Q
H
L
Q
L
H
L
X
H
H
L
L
X
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
4 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
[1]
Table 6:
Input
SD
Function table for synchronous operation
Output
RD
H
CP
↑
D
L
Qn+1
L
Qn+1
H
H
H
H
↑
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
9. Limiting values
Table 7:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
-
Max
+6.5
−50
Unit
V
VCC
IIK
supply voltage
input clamping current VI < 0 V
input voltage
mA
V
[1]
VI
−0.5
-
+6.5
±50
IOK
VO
output clamping current VO > VCC or VO < 0 V
mA
[1] [2]
[1] [2]
output voltage
active mode
−0.5
−0.5
-
VCC + 0.5 V
Power-down mode
VO = 0 V to VCC
+6.5
±50
V
IO
output current
mA
mA
ICC
quiescent supply
current
-
±100
IGND
Tstg
Ptot
ground current
-
±100
+150
250
mA
°C
storage temperature
−65
total power dissipation Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
10. Recommended operating conditions
Table 8:
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
0
Typ
Max Unit
VCC
VI
supply voltage
input voltage
output voltage
-
-
-
-
5.5
5.5
VCC
5.5
V
V
V
V
VO
active mode
0
Power-down mode;
VCC = 0 V
0
Tamb
ambient temperature
−40
0
-
-
-
+125 °C
∆t/∆V
input transition rise and
fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
20
10
ns/V
ns/V
0
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
5 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
11. Static characteristics
Table 9:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
HIGH-state input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-state input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
-
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VOH
HIGH-state output
voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
V
CC − 0.1
-
-
-
-
-
-
-
V
V
V
V
V
V
1.2
1.9
2.2
2.3
3.8
1.54
2.15
2.50
2.62
4.11
VOL
LOW-state output
voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
±5
V
0.07
0.12
0.17
0.33
0.39
±0.1
±0.1
V
V
V
V
V
ILI
input leakage current
µA
µA
IOFF
power-off leakage
current
±10
ICC
∆ICC
Ci
quiescent supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
0.1
5
10
500
-
µA
µA
pF
V
additional quiescent
supply current (per pin)
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
V
input capacitance
4.0
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
6 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Table 9:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
HIGH-state input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-state input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
-
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VOH
HIGH-state output
voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
0.95
1.7
1.9
2.0
3.4
VOL
LOW-state output
voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10
0.70
0.45
0.60
0.80
0.80
±20
V
V
V
V
V
V
ILI
input leakage current
µA
µA
IOFF
power-off leakage
current
±20
ICC
quiescent supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
40
µA
µA
V
∆ICC
additional quiescent
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
5000
supply current (per pin)
V
[1] All typical values are measured at Tamb = 25 °C.
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
7 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
12. Dynamic characteristics
Table 10: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
tPHL, tPLH propagation delay
CP to Q, Q
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
6.0
13.4
7.1
7.1
5.9
4.1
ns
ns
ns
ns
ns
3.5
3.5
3.5[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
2.5
SD to Q, Q
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
6.0
12.9
7.0
7.0
5.9
4.1
ns
ns
ns
ns
ns
3.5
3.5
3.0[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
2.5
RD to Q, Q
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
5.0
12.9
7.0
7.0
5.9
4.1
ns
ns
ns
ns
ns
3.5
3.5
3.0[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
2.5
tW
pulse width
clock CP HIGH or LOW
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
1.3[2]
-
set SD (LOW) and
reset RD (LOW)
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.6[2]
-
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
8 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Table 10: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
trec
recovery time
set SD or reset RD
see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.9
1.4
1.3
1.2
1.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
−3.0[2]
-
tsu
setup time
D to CP
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.5[2]
-
th
hold time
D to CP
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.0
0.3
0.5
1.2
0.5
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
0.6[2]
-
fmax
maximum input clock
frequency
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
175
175
175
200
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
280[2]
-
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
9 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Table 10: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay
CP to Q, Q
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
-
-
-
-
-
13.4
7.1
7.1
5.9
4.1
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
SD to Q, Q
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
-
-
-
-
-
12.9
7.0
7.0
5.9
4.1
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
RD to Q, Q
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
-
-
-
-
-
12.9
7.0
7.0
5.9
4.1
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
tW
pulse width
clock CP HIGH or LOW
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
set SD (LOW) and
reset RD (LOW)
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
trec
recovery time
set SD or reset RD
see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.9
1.4
1.3
1.2
1.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
10 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Table 10: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol
Parameter
setup time
D to CP
Conditions
Min
Typ
Max
Unit
tsu
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
th
hold time
D to CP
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.0
0.3
0.5
1.2
0.5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
fmax
maximum input clock
frequency
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
175
175
175
200
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[1] All typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
11 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
13. Waveforms
V
I
V
CP input
M
GND
t
W
1/f
max
V
I
V
D input
M
GND
t
t
h
h
t
t
su
su
t
t
PLH
PHL
V
OH
V
Q output
Q output
M
V
OL
V
OH
V
M
V
OL
t
t
PHL
PLH
mnb141
Measurement points are given in Table 11.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 6. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width,
the D to CP set-up, the CP to D hold times and the maximum clock pulse
frequency
Table 11: Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
12 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
V
I
V
CP input
M
GND
t
rec
V
I
V
M
SD input
RD input
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
Q output
Q output
V
V
M
V
OL
V
OH
M
V
OL
t
t
PLH
PHL
mnb142
Measurement points are given in Table 11.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and
reset pulse widths and the RD to CP removal time
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
C
L
R
L
R
T
mna616
Test data is given in Table 12.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 8. Load circuitry for switching times
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
13 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Table 12: Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
open
open
open
open
open
GND
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
500 Ω
500 Ω
500 Ω
500 Ω
3.0 V to 3.6 V
4.5 V to 5.5 V
6 V
2 × VCC
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
14 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
14. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 9. Package outline SOT505-2 (TSSOP8)
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
15 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 10. Package outline SOT765-1 (VSSOP8)
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
16 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
04-07-22
04-11-09
SOT833-1
- - -
MO-252
Fig 11. Package outline SOT833-1 (XSON8)
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
17 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
15. Abbreviations
Table 13: Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal Oxide Semiconductor
Transistor Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
CDM
DUT
Charged Device Model
Device Under Test
16. Revision history
Table 14: Revision history
Document ID
Release date Data sheet status
20051103 Product data sheet
Change notice Doc. number
Supersedes
74LVC2G74_1
-
-
-
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
18 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
17. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
18. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
20. Trademarks
Notice — All referenced brands, product names, service names and
19. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74LVC2G74_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 3 November 2005
19 of 20
74LVC2G74
Philips Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
9
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information . . . . . . . . . . . . . . . . . . . . 19
10
11
12
13
14
15
16
17
18
19
20
21
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 3 November 2005
Document number: 74LVC2G74_1
Published in The Netherlands
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