74LVC374APW-Q100J [NXP]
74LVC374A-Q100 - Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state TSSOP2 20-Pin;
| 型号： | 74LVC374APW-Q100J |
| 厂家： | 
NXP |
| 描述： | 74LVC374A-Q100 - Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state TSSOP2 20-Pin |
| 文件： | 总18页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC374A-Q100
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 1 — 22 November 2012
Product data sheet
1. General description
The 74LVC374A-Q100 is an octal D-type flip-flop featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops store the state of their individual D-inputs that meet the set-up and hold
times requirements on the LOW to HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when VCC = 0 V
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC374AD-Q100
40 C to +125 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVC374APW-Q100 40 C to +125 C
74LVC374ABQ-Q100 40 C to +125 C
TSSOP20
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1
very thin quad flat package; no leads;
20 terminals; body 2.5 4.5 0.85 mm
4. Functional diagram
1
EN
11
C1
11
3
2
1D
CP
3
4
2
5
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
OE
1
mna196
mna891
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
2 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Q0
Q1
Q2
Q3
3
4
2
5
6
9
D0
D1
D2
D3
D4
7
8
FF1
to
FF8
3-STATE
OUTPUTS
13
Q4 12
Q5
14 D5
15
17
18
Q6 16
Q7 19
D6
D7
CP
OE
11
1
mna892
Fig 3. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
FF3
CP
CP
CP
CP
CP
FF1
FF2
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4. Logic diagram
74LVC374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
3 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
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(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO20 and TSSOP20
Fig 6. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
1
Pin description
Pin
OE
CP
Description
output enable input (active LOW)
clock input (LOW to HIGH, edge-triggered)
data input
11
D[0:7]
Q[0:7]
10
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
3-state flip-flop output
ground (0 V)
GND
VCC
20
supply voltage
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
4 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
OE
L
Internal flip-flop Output
CP
Dn
Qn
L
Load and read register
l
L
L
h
l
H
L
H
Z
Load register and disable
outputs
H
H
h
H
Z
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
= LOW to HIGH clock transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0
mA
V
[1]
VI
+6.5
50
VCC + 0.5
+6.5
50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0
output HIGH or LOW state
output 3-state
mA
V
[2]
[2]
VO
0.5
0.5
-
V
IO
output current
VO = 0 V to VCC
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
100
65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C derate linearly with 8 mW/K.
For TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
5 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
1.2
0
Typ
Max
3.6
-
Unit
V
VCC
supply voltage
-
-
-
-
-
-
-
-
functional
V
VI
input voltage
5.5
VCC
5.5
+125
20
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
V
0
V
Tamb
ambient temperature
in free air
40
0
C
ns/V
ns/V
t/V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
10
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
1.08
-
-
-
-
-
-
-
-
-
1.08
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V
0.65 VCC
-
0.65 VCC
-
VCC = 2.3 V to 2.7 V
1.7
-
1.7
-
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
2.0
-
0.12
2.0
-
0.12
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
0.35 VCC
0.7
0.35 VCC
0.7
0.8
0.8
VOH
HIGH-level
output
voltage
IO = 100 A;
VCC = 1.65 V to 3.6 V
VCC 0.2
-
-
VCC 0.3
-
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 18 mA; VCC = 3.0 V
IO = 24 mA; VCC = 3.0 V
VI = VIH or VIL
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output
voltage
IO = 100 A;
-
-
0.2
-
0.3
V
VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
-
0.45
0.6
-
-
-
-
-
0.65
0.8
V
-
V
-
-
0.4
0.6
V
0.55
5
0.8
V
II
input leakage VCC = 3.6 V; VI = 5.5 V or GND
current
0.1
20
A
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
6 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
IOZ
OFF-state
output
VI = VIH or VIL; VCC = 3.6 V;
VO = 5.5 V or GND;
-
0.1
5
-
20
A
current
IOFF
power-off
leakage
supply
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
-
0.1
5
10
-
-
40
A
A
ICC
additional
supply
per input pin; VCC = 2.7 V to 3.6
V; VI = VCC 0.6 V; IO = 0 A
500
5000
current
CI
input
VCC = 0 V to 3.6 V;
-
4.0
-
-
-
pF
capacitance VI = GND to VCC
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
[2]
[2]
tpd
ten
tdis
propagation CP to Qn; see Figure 7
delay
VCC = 1.2 V
-
16
7.4
3.9
3.5
3.3
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.2
1.5
1.5
1.5
16.3
8.4
8.0
7.0
2.2
1.5
1.5
1.5
18.8
9.7
10.0
9.0
VCC = 3.0 V to 3.6 V
enable time
OE to Qn; see Figure 8
VCC = 1.2 V
-
19
6.6
3.7
3.8
3.0
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.5
1.5
1.5
16.7
9.3
8.5
7.5
1.5
1.5
1.5
1.5
19.3
10.8
11.0
9.5
VCC = 3.0 V to 3.6 V
disable time OE to Qn; see Figure 8
VCC = 1.2 V
-
8.0
4.0
2.2
3.1
2.9
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.3
1.0
1.5
1.5
10.1
5.7
6.5
6.0
2.3
1.0
1.5
1.5
11.7
6.7
9.0
7.5
VCC = 3.0 V to 3.6 V
74LVC374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
7 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
tW
pulse width
set-up time
hold time
clock HIGH or LOW; see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
5.0
4.0
3.0
3.0
-
-
-
-
-
-
5.0
4.0
4.5
4.5
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
Dn to CP; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
tsu
4.0
3.0
2.0
2.0
-
-
-
-
-
-
4.0
3.0
2.0
2.0
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
Dn to CP; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0
th
3.0
2.0
1.5
1.5
-
-
-
-
-
-
3.0
2.0
1.5
1.5
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
see Figure 7
0.6
fmax
maximum
frequency
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
100
125
150
150
-
-
-
-
-
-
-
64
100
120
120
-
-
MHz
MHz
MHz
MHz
ns
-
-
-
-
VCC = 3.0 V to 3.6 V
-
-
[3]
[4]
tsk(o)
CPD
output skew VCC = 3.0 V to 3.6 V
time
1.0
1.5
power
per flip-flop; VI = GND to VCC
dissipation
capacitance
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
-
-
-
11.6
13.6
15.4
-
-
-
-
-
-
pF
pF
pF
[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
en is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
t
.
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
8 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
11. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
mna894
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Clock input to output propagation delays, pulse width, output transition times, and the maximum
frequency
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna644
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. 3-state enable and disable times
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
9 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
V
I
V
M
CP input
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
mna202
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 9. Data set-up and hold times for the Dn input to the CP input
Table 8.
Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
0.5 VCC
0.5 VCC
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
0.5 VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.15 V
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
1.5 V
1.5 V
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
10 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Load circuitry for switching times
Table 9.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 VCC
2 VCC
2 VCC
2 VCC
2 VCC
tPHZ, tPZH
GND
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
2 ns
2 ns
2 ns
2.5 ns
2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 k
1 k
500
500
500
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
GND
open
GND
open
GND
3.0 V to 3.6 V
open
GND
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
11 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 11. Package outline SOT163-1 (SO20)
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
12 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 12. Package outline SOT360-1 (TSSOP20)
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
13 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 13. Package outline SOT764-1 (DHVQFN20)
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
14 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
DUT
ESD
HBM
MM
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
TTL
Transistor-Transistor Logic
Military
MIL
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC374A_Q100 v.1 20121122
Product data sheet
-
-
74LVC374A_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
15 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC374A_Q100
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Product data sheet
Rev. 1 — 22 November 2012
16 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC374A_Q100
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Product data sheet
Rev. 1 — 22 November 2012
17 of 18
74LVC374A-Q100
NXP Semiconductors
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 November 2012
Document identifier: 74LVC374A_Q100
相关型号：
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