74LVC3G14GM [NXP]
Triple inverting Schmitt trigger with 5 V tolerant input; 三重反相施密特触发器具有5 V容限输入
| 型号： | 74LVC3G14GM |
| 厂家： | 
NXP |
| 描述： | Triple inverting Schmitt trigger with 5 V tolerant input |
| 文件： | 总17页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
Rev. 05 — 5 October 2007
Product data sheet
1. General description
The 74LVC3G14 provides three inverting buffers with Schmitt trigger action.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at the inputs
makes the circuit tolerant of slower input rise and fall time. This device is fully specified for
partial power-down applications using IOFF. The IOFF circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Unlimited rise and fall times
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C.
3. Applications
I Wave and pulse shaper for highly noisy environment
I Astable multivibrator
I Monostable multivibrator.
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC3G14DP −40 °C to +125 °C
74LVC3G14DC −40 °C to +125 °C
74LVC3G14GT −40 °C to +125 °C
74LVC3G14GM −40 °C to +125 °C
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
SOT833-1
SOT902-1
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
XQFN8
plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6 × 1.6 × 0.5 mm
5. Marking
Table 2.
Marking codes
Type number
74LVC3G14DP
74LVC3G14DC
74LVC3G14GT
74LVC3G14GM
Marking code
V14
V14
V14
V14
6. Functional diagram
1
6
3
7
2
5
1
2
3
1A
3Y
2A
1Y
3A
2Y
7
6
5
A
Y
mna740
mna025
mna741
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
(one Schmitt trigger)
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
2 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
7. Pinning information
7.1 Pinning
74LVC3G14
1
2
3
4
8
7
6
5
1A
3Y
V
CC
1Y
3A
2Y
2A
GND
001aag081
Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74LVC3G14
terminal 1
index area
74LVC3G14
1A
3Y
1
2
3
4
8
7
6
5
V
1Y
1
CC
7
6
5
1A
3Y
2A
1Y
3A
2Y
3A
2Y
2
3
2A
GND
001aag082
001aab834
Transparent top view
Transparent top view
Fig 5. Pin configuration SOT833-1 (XSON8)
Fig 6. Pin configuration SOT902-1 (XQFN8)
7.2 Pin description
Table 3.
Pin description
Symbol (n = 1, 2, 3)
Pin
Description
SOT902-1
SOT505-2, SOT765-1 and
SOT833-1
nA
1, 3, 6
7, 5, 2
data input
nY
7, 5, 2
1, 3, 6
data output
ground (0 V)
supply voltage
GND
VCC
4
8
4
8
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
3 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
8. Functional description
Table 4.
Function table [1]
Input nA
Output nY
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
±50
VCC + 0.5
+6.5
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1][2]
[1][2]
VO
−0.5
−0.5
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
mW
°C
ICC
IGND
Ptot
Tstg
supply current
-
ground current
−100
-
[3]
total power dissipation
storage temperature
Tamb = −40 °C to +125 °C
250
+150
−65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 and VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
10. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
1.65
0
Typ
Max
5.5
Unit
V
supply voltage
input voltage
output voltage
-
-
-
-
-
VI
5.5
V
VO
Active mode
0
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
−40
+125
°C
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
4 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = −40 °C to +85 °C
VOH
HIGH-level output voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
V
CC − 0.1 -
-
-
-
-
-
-
V
V
V
V
V
V
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
0.1
V
-
0.45
0.3
V
-
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
VI or VO = 5.5 V; VCC = 0 V
VI = 5.5 V or GND; IO = 0 A;
-
0.4
V
-
0.55
0.55
±5
V
-
V
II
input leakage current
power-off leakage current
supply current
±0.1
±0.1
0.1
µA
µA
µA
IOFF
ICC
±10
10
V
CC = 1.65 V to 5.5 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
∆ICC
additional supply current
input capacitance
-
-
5
500
-
µA
V
CI
VCC = 3.3 V; VI = GND to VCC
3.5
pF
Tamb = −40 °C to +125 °C
VOH HIGH-level output voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
V
CC − 0.1 -
-
-
-
-
-
-
V
V
V
V
V
V
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.7
0.45
0.6
0.8
0.8
±20
V
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
V
V
V
II
input leakage current
µA
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
5 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
IOFF power-off leakage current
ICC
Conditions
Min
Typ [1]
Max
±20
40
Unit
µA
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
supply current
VI = 5.5 V or GND; IO = 0 A;
µA
V
CC = 1.65 V to 5.5 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
∆ICC
additional supply current
-
-
5000
µA
V
[1] All typical values are measured at maximum VCC and Tamb = 25 °C.
Table 8.
Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 8
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
VT+
positive-going
threshold voltage
see Figure 9 and Figure 10
VCC = 1.8 V
0.70
1.00
1.30
1.90
2.20
1.10
1.40
1.76
2.47
2.91
1.50
1.80
2.20
3.10
3.60
0.70
1.00
1.30
1.90
2.20
1.70
2.00
2.40
3.30
3.80
V
VCC = 2.3 V
V
V
V
V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
VT−
negative-going
threshold voltage
see Figure 9 and Figure 10
VCC = 1.8 V
0.25
0.40
0.60
1.00
1.20
0.61
0.80
1.04
1.55
1.86
0.90
1.15
1.50
2.00
2.30
0.25
0.40
0.60
1.00
1.20
1.10
1.35
1.70
2.20
2.50
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
[2]
VH
hysteresis voltage see Figure 9, Figure 10
and Figure 11
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.15
0.25
0.40
0.60
0.70
0.49
0.60
0.73
0.92
1.02
1.00
1.10
1.20
1.50
1.70
0.15
0.25
0.40
0.60
0.70
1.20
1.30
1.40
1.70
1.90
V
V
V
V
V
[1] All typical values are measured at Tamb = 25 °C
[2] VH = VT+ − VT-
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
6 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
12. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay nA to nY; see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
0.5
0.5
0.5
0.5
-
4.2
3.0
3.8
3.2
2.4
18.1
11.0
6.5
7.0
6.0
4.3
-
1.0
0.5
0.5
0.5
0.5
-
12.0
7.2
7.7
6.7
4.7
-
ns
ns
ns
ns
ns
pF
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
CPD
power dissipation VI = GND to VCC; VCC = 3.3 V
capacitance
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
7 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
13. Waveforms
V
I
V
V
M
nA input
M
GND
t
t
PHL
PLH
V
OH
V
V
M
nY output
M
V
OL
mna344
Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The data input (nA) to output (nY) propagation delays
Table 10. Measurement points
VCC
Input VM
0.5 × VCC
0.5 × VCC
1.5 V
Output VM
0.5 × VCC
0.5 × VCC
1.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
8 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
14. Waveforms transfer characteristics
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mna208
V
H
V
V
T+
T−
mna207
VT+ and VT− limits at 70 % and 20 %.
Fig 9. Transfer characteristic
Fig 10. Definition of VT+, VT− and VH
mdb627
14
12
I
CC
(mA)
10
8
6
4
2
0
0
0.5
1
1.5
2
V (V)
I
VCC = 3.0 V
Fig 11. Typical transfer characteristics
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd = fi × (tr × ∆ICC(AV) + tf × ∆ICC(AV)) × VCC where:
Padd = additional power dissipation (µW);
fi = input frequency (MHz);
tr = input rise time (ns); 10 % to 90 %;
tf = input fall time (ns); 90 % to 10 %;
∆ICC(AV) = average additional supply current (µA).
∆ICC(AV) differs with positive or negative input transitions, as shown in Figure 12.
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
9 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
An example of a relaxation circuit using the 74LVC3G14 is shown in Figure 13.
mnb086
50
∆I
CC(AV)
(mA)
(1)
40
30
20
(2)
10
0
2
3
4
5
6
V
(V)
CC
Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified.
(1) Positive-going edge.
(2) Negative-going edge.
Fig 12. ∆ICC(AV) as a function of VCC
R
C
mna035
1
T
1
f =
≈
--- ---------------------
0.8 × RC
Fig 13. Relaxation oscillator
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
10 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
16. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 14. Package outline SOT505-2 (TSSOP8)
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
11 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 15. Package outline SOT765-1 (VSSOP8)
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
12 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
04-07-22
04-11-09
SOT833-1
- - -
MO-252
Fig 16. Package outline SOT833-1 (XSON8)
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
13 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
C
1
y
L
M
M
v
C
C
A
B
4
w
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-16
05-11-25
SOT902-1
- - -
- - -
Fig 17. Package outline SOT902-1 (XQFN8)
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
14 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
17. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
18. Revision history
Table 13. Revision history
Document ID
74LVC3G14_5
Modifications:
Release date
20071005
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC3G14_4
• In Section 11 “Static characteristics”, changed conditions for input leakage and supply
current.
74LVC3G14_4
74LVC3G14_3
74LVC3G14_2
74LVC3G14_1
20070314
20050131
20041027
20040510
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
74LVC3G14_3
74LVC3G14_2
74LVC3G14_1
-
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
15 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
19.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC3G14_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 5 October 2007
16 of 17
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
21. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Waveforms transfer characteristics. . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
9
10
11
12
13
14
15
16
17
18
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 October 2007
Document identifier: 74LVC3G14_5
相关型号：
©2020 ICPDF网 联系我们和版权申明