74LVC574APW,118 [NXP]
74LVC574A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger (3-state) TSSOP2 20-Pin;
| 型号： | 74LVC574APW,118 |
| 厂家： | 
NXP |
| 描述： | 74LVC574A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger (3-state) TSSOP2 20-Pin 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC574A
Octal D-type flip-flop with 5 V
tolerant inputs/outputs; positive
edge-trigger; 3-state
Product specification
2004 Mar 22
Supersedes data of 2003 Jun 20
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
FEATURES
DESCRIPTION
• 5 V tolerant inputs and outputs, for interfacing with 5 V
logic
The 74LVC574A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
• Supply voltage range from 1.2 to 3.6 V
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 and 5 V environment.
• Direct interface with TTL levels
• High impedance when VCC = 0 V
• 8-bit positive edge-triggered register
• Independent register and 3-state buffer operation
• Flow-through pin-out architecture
• Complies with JEDEC standard no. 8-1A
The 74LVC574A is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus-oriented applications. A clock (CP) and an
Output Enable (OE) input are common to all flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
When OE is LOW, the contents of the eight flip-flops is
available at the outputs. When OE is HIGH, the outputs go
to the high impedance off-state. Operation of the OE input
does not affect the state of the flip-flops.
• Specified from −40 to +85 °C and −40 to +125 °C.
The 74LVC574A is functionally identical to the
74LVC374A, but has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPHL/tPLH
PARAMETER
propagation delay CP to Qn
maximum clock frequency
input capacitance
CONDITIONS
TYPICAL
3.2
UNIT
CL = 50 pF; VCC = 3.3 V
ns
fmax
CI
150
5.0
15
MHz
pF
CPD
power dissipation capacitance per flip-flop notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2004 Mar 22
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
INTERNAL
FLIP-FLOP
OPERATING MODE
OE
CP
Dn
Qn
Load and read register
L
L
↑
↑
↑
↑
l
L
H
L
L
H
Z
Z
h
l
Load register and disable
outputs
H
H
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑ = LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
−40 to +125 °C
PINS
20
PACKAGE
SO20
MATERIAL
plastic
CODE
74LVC574AD
74LVC574ADB
74LVC574APW
74LVC574ABQ
SOT163-1
SOT339-1
SOT360-1
SOT764-1
−40 to +125 °C
20
SSOP20
TSSOP20
DHVQFN20
plastic
−40 to +125 °C
20
plastic
−40 to +125 °C
20
plastic
PINNING
PIN
SYMBOL
DESCRIPTION
PIN
1
SYMBOL
DESCRIPTION
output enable input (active LOW)
data input
11
CP
clock input (LOW-to-HIGH; edge
triggered)
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
12
13
14
15
16
17
18
19
20
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
data output
data output
data output
data output
data output
data output
data output
data output
supply voltage
2
3
data input
4
data input
5
data input
6
data input
7
data input
8
data input
9
data input
10
ground (0 V)
2004 Mar 22
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
V
handbook, halfpage
OE
1
CC
20
handbook, halfpage
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
V
OE
1
2
20
19
CC
D0
D1
Q0
3
18 Q1
17
4
Q2
D2
D3
16
15
5
Q3
Q4
(1)
GND
574
6
D4
7
14 Q5
13
D5
8
Q6
12 Q7
CP
D6
9
D7
GND
10
11
10
11
MNA797
GND CP
Top view
MNA978
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO20 and (T)SSOP20.
Fig.2 Pin configuration DHVQFN20.
handbook, halfpage
1
C1
11
EN
handbook, halfpage
11
CP
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
19
1D
3
4
5
18
17
16
6
7
8
9
15
14
13
12
OE
1
MNA798
MNA799
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Mar 22
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
handbook, halfpage
D0
2
Q0
19
Q1 18
17
3
4
5
6
7
8
9
D1
D2
D3
D4
D5
D6
D7
Q2
FF1
to
FF8
Q3 16
Q4 15
3-STATE
OUTPUTS
Q5
14
Q6 13
Q7 12
CP
OE
11
1
MNA800
Fig.5 Functional diagram.
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q
7
MNA801
Fig.6 Logic diagram.
5
2004 Mar 22
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
for maximum speed performance 2.7
V
for low-voltage applications
1.2
0
3.6
5.5
VCC
5.5
+125
20
V
VI
input voltage
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
V
0
V
Tamb
tr, tf
operating ambient temperature in free air
input rise and fall times VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
−40
0
°C
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5
V
IIK
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
mA
V
output HIGH or LOW state; note 1 −0.5
VCC + 0.5
+6.5
±50
output 3-state; note 1
VO = 0 to VCC
−0.5
−
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
mA
mA
°C
mW
ICC, IGND
Tstg
−
±100
+150
500
−65
−
Ptot
Tamb = −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
2004 Mar 22
6
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C; note 1
VIH
VIL
HIGH-level input voltage
1.2
VCC
−
−
−
−
−
V
2.7 to 3.6
1.2
2.0
−
−
V
V
V
LOW-level input voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −12 mA
IO = −100 µA
IO = −18 mA
IO = −24 mA
2.7
3.0
3.0
3.0
V
V
V
V
CC − 0.5
−
−
−
−
−
V
V
V
V
CC − 0.2
CC − 0.6
CC − 0.8
VCC
−
−
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL
IO = 12 mA
IO = 100 µA
IO = 24 mA
2.7
3.0
3.0
3.6
−
−
−
−
−
0.40
0.20
0.55
±5
V
GND
−
V
V
ILI
VI = 5.5 V or GND;
note 2
±0.1
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND
3.6
−
0.1
±10
µA
Ioff
power-off leakage supply
quiescent supply current
VI or VO = 5.5 V
0.0
3.6
−
−
0.1
0.1
±10
µA
µA
ICC
VI = VCC or GND;
IO = 0
10
∆ICC
additional quiescent supply VI = VCC − 0.6 V;
current per input pin IO = 0
2.7 to 3.6
−
5
500
µA
2004 Mar 22
7
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +125 °C
VIH
HIGH-level input voltage
LOW-level input voltage
1.2
VCC
−
−
−
−
−
V
2.7 to 3.6
1.2
2.0
−
−
V
V
V
VIL
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −12 mA
IO = −100 µA
IO = −18 mA
IO = −24 mA
2.7
V
V
V
V
CC − 0.65
−
−
−
−
−
−
−
−
V
V
V
V
2.7 to 3.6
3.0
CC − 0.3
CC − 0.75
CC − 1
3.0
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL
IO = 12 mA
2.7
−
−
−
−
−
−
−
−
−
−
0.6
0.3
0.8
±20
±20
V
IO = 100 µA
2.7 to 3.6
3.0
V
IO = 24 mA
V
ILI
VI = 5.5 V or GND
3.6
µA
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND
3.6
Ioff
power-off leakage supply
quiescent supply current
VI or VO = 5.5 V
0.0
3.6
−
−
−
−
±20
µA
µA
ICC
VI = VCC or GND;
IO = 0
40
∆ICC
additional quiescent supply VI = VCC − 0.6 V;
current per input pin IO = 0
2.7 to 3.6
−
−
5000
µA
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2004 Mar 22
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C; note 1
tPHL/tPLH
propagation delay CP to Qn see Figs 7 and 10 2.7
1.5
3.6
8.0
ns
3.0 to 3.6 1.5
3.2(2)
7.0
8.5
7.5
6.5
6.0
−
ns
tPZH/tPZL
tPHZ/tPLZ
tW
3-state output enable time
OE to Qn
see Figs 9 and 10 2.7
1.5
4.3
ns
3.0 to 3.6 1.5
3.5(2)
2.8
2.5(2)
ns
3-state output disable time
OE to Qn
see Figs 9 and 10 2.7
1.5
ns
3.0 to 3.6 1.5
ns
clock pulse width
HIGH or LOW
see Fig.7
see Fig.8
see Fig.8
2.7
3.0 to 3.6 3.4
2.7 2.0
3.0 to 3.6 2.0
2.7 1.5
3.0 to 3.6 1.5
2.7 80
3.0 to 3.6 100
3.3
−
ns
1.7(2)
−
0.3(2)
−
ns
tsu
set-up time Dn to CP
hold time Dn to CP
maximum clock frequency
skew
−
ns
−
ns
th
−
−
ns
−0.2(2)
−
150(2)
−
ns
fmax
−
MHz
MHz
ns
−
tsk(0)
note 3
3.0 to 3.6
−
−
1.0
Tamb = −40 to +125 °C
PHL/tPLH propagation delay CP to Qn see Figs 7 and 10 2.7
3.0 to 3.6
see Figs 9 and 10 2.7
3.0 to 3.6
see Figs 9 and 10 2.7
t
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10.0
9.0
11.0
9.5
8.5
7.5
−
ns
ns
tPZH/tPZL
tPHZ/tPLZ
tW
3-state output enable time
OE to Qn
ns
ns
3-state output disable time
OE to Qn
ns
3.0 to 3.6
2.7
ns
clock pulse width
HIGH or LOW
see Fig.7
see Fig.8
see Fig.8
ns
3.0 to 3.6
2.7
−
ns
tsu
set-up time Dn to CP
hold time Dn to CP
maximum clock frequency
skew
−
ns
3.0 to 3.6
2.7
−
ns
th
−
ns
3.0 to 3.6
2.7
−
ns
fmax
−
MHz
MHz
ns
3.0 to 3.6
3.0 to 3.6
−
tsk(0)
note 3
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
2004 Mar 22
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
AC WAVEFORMS
1/f
max
V
I
CP input
V
M
t
GND
t
W
t
PHL
PLH
V
OH
V
Qn output
M
V
OL
MNA802
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.7 Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the
maximum clock pulse frequency.
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
MNA803
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.8 Data setup and hold times for the Dn input to the CP input.
10
2004 Mar 22
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CC
Q
output
n
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
Q
output
n
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA804
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.1VCC at VCC < 2.7 V.
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1VCC at VCC < 2.7 V.
Fig.9 3-state enable and disable times.
S1
2 × V
CC
open
GND
V
CC
R
R
= 500 Ω
= 500 Ω
L
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
=
L
R
L
T
50 pF
MNA815
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
VCC
<2.7 V
2.7 to 3.6 V
VI
open
VCC
2 × VCC
GND
2.7 V
Definitions for test circuit:
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to Zo of pulse generators.
Fig.10 Load circuitry for switching times.
11
2004 Mar 22
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
2004 Mar 22
12
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
c
H
v
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
2004 Mar 22
13
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
2004 Mar 22
14
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
2004 Mar 22
15
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
74LVC574A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Mar 22
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/03/pp17
Date of release: 2004 Mar 22
Document order number: 9397 750 13028
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