74LVC821AD,118 [NXP]
74LVC821A - 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state SOP 24-Pin;
| 型号： | 74LVC821AD,118 |
| 厂家： | 
NXP |
| 描述： | 74LVC821A - 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state SOP 24-Pin 驱动 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 03 — 11 May 2004
Product data sheet
1. General description
The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an
output enable input (pin OE) are common to all flip-flops. The ten flip-flops will store the
state of their individual D-inputs that meet the set-up and hold times requirements on the
LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops is
available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE inputs does not affect the state of the flip-flops.
2. Features
■ 5 V tolerant inputs and outputs; for interfacing with 5 V logic
■ Wide supply voltage range from 1.2 V to 3.6 V
■ Inputs accept voltages up to 5.5 V
■ CMOS low power consumption
■ Direct interface with TTL levels
■ Flow-through pin-out architecture
■ 10-bit positive edge-triggered register
■ Independent register and 3-state buffer operation
■ Complies with JEDEC standard JESD8-B
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
Symbol
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
fmax
Parameter
Conditions
Min
Typ
3.7
3.5
3.0
200
5.0
Max
Unit
ns
propagation delay CP to Qn
3-state output enable time OE to Qn
3-state output disable time OE to Qn
maximum clock frequency
input capacitance
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
-
-
-
-
-
-
-
-
-
-
ns
ns
MHz
pF
CI
[1] [2]
CPD
power dissipation capacitance per gate
VCC = 3.3 V
outputs enabled
outputs disabled
-
-
17
11
-
-
pF
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ (CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC
.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range
−40 °C to +125 °C
Name
Description
Version
74LVC821AD
SO24
plastic small outline package; 24 leads; body width SOT137-1
7.5 mm
74LVC821ADB
−40 °C to +125 °C
SSOP24
plastic shrink small outline package; 24 leads; body SOT340-1
width 5.3 mm
74LVC821APW −40 °C to +125 °C
TSSOP24
plastic thin shrink small outline package; 24 leads; SOT355-1
body width 4.4 mm
74LVC821ABQ
−40 °C to +125 °C
DHVQFN24 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 24 terminals;
body 3.5 × 5.5 × 0.85 mm
SOT815-1
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
2 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
5. Functional diagram
Q0
Q1
Q2
Q3
Q4
Q5
2
3
23
22
21
20
19
18
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
4
5
6
FF0
to
FF9
3-STATE
OUTPUTS
7
8
Q6 17
Q7
9
16
10
11
Q8 15
Q9 14
CP
OE
13
1
001aaa679
Fig 1. Functional diagram.
13
1
C1
EN
13
CP
2
23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
2
23
3
4
22
21
20
19
18
17
16
15
14
1D
3
4
5
22
21
20
5
6
7
6
7
19
18
8
9
10
11
8
9
17
16
15
14
OE
10
11
1
001aaa677
001aaa678
Fig 2. Logic symbol.
Fig 3. IEC logic symbol.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
3 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
D0
D1
D2
D3
D4
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
FF1
FF2
FF3
FF4
FF5
CP
OE
Q0
Q1
Q2
Q3
Q4
D5
D6
D7
D8
D9
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
FF6
FF7
FF8
FF9
FF10
Q5
Q6
Q7
Q8
Q9
001aaa681
Fig 4. Logic diagram.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
4 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
6. Pinning information
6.1 Pinning
V
OE
1
CC
24
Q0
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
23
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
V
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
GND(1)
821A
D8 10
D9 11
GND 12
D8 10
D9 11
001aaa676
12
13
GND CP
Top view
001aaa680
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO24 and (T)SSOP24.
Fig 6. Pin configuration DHVQFN24.
6.2 Pin description
Table 3:
Symbol
OE
Pin description
Pin
1
Description
output enable input (active LOW)
data input
D0
2
D1
3
data input
D2
4
data input
D3
5
data input
D4
6
data input
D5
7
data input
D6
8
data input
D7
9
data input
D8
10
11
data input
D9
data input
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
5 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
Table 3:
Symbol
GND
CP
Pin description …continued
Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
Description
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
supply voltage
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
7. Functional description
Table 4:
Function table[1]
Operating mode
Input
Internal
Output
flip-flops
OE
L
CP
Dn
I
Qn
L
Load and read register
Load register and disable outputs
↑
L
L
↑
h
I
H
H
H
H
L
↑
L
Z
↑
h
X
H
Z
Hold
H or L
NC
NC
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
NC = no change;
X = don’t care.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5 +6.5
−50
−0.5 +6.5
±50
Max
Unit
V
supply voltage
input diode current
input voltage
VI < 0 V
-
mA
V
[1]
VI
IOK
output diode current
VO > VCC or VO < 0 V
-
mA
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
6 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
Table 5:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
[1]
[1]
VO
output voltage
HIGH or LOW state
3-state
−0.5 VCC + 0.5 V
−0.5 +6.5
V
IO
output source or sink
current
VO = 0 V to VCC
-
±50
mA
ICC, IGND
Tstg
VCC or GND current
storage temperature
power dissipation
-
±100
+150
500
mA
°C
−65
[2]
Ptot
Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO24 package: above 70 °C derate linearly with 8 mW/K.
For SSOP24 and TSSOP24 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN24 package: above 60 °C derate linearly with 4.5 mW/K.
9. Recommended operating conditions
Table 6:
Operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
for maximum speed
performance
2.7
-
3.6
V
for low-voltage
applications
1.2
-
3.6
V
VI
input voltage
0
-
-
-
-
5.5
VCC
5.5
V
V
V
VO
output voltage
HIGH or LOW state
3-state
0
0
Tamb
tr, tf
operating ambient
temperature
in free air
−40
+125 °C
input rise and fall times VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
0
-
-
20
10
ns/V
ns/V
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
VIL
HIGH-level input voltage
VCC = 1.2 V
VCC
-
-
-
-
-
V
V
V
V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
2.0
-
LOW-level input voltage
-
-
GND
0.8
VCC = 2.7 V to 3.6 V
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
7 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH HIGH-level output voltage
Conditions
Min
Typ
Max
Unit
VI = VIH or VIL
[2]
IO = −100 µA; VCC = 2.7 V to 3.6 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
V
V
V
V
CC − 0.2 VCC
-
-
-
-
V
V
V
V
CC − 0.5
CC − 0.6
CC − 0.8
-
-
-
VOL
LOW-level output voltage
input leakage current
[2]
IO = 100 µA; VCC = 2.7 V to 3.6 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VI = 5.5 V or GND; VCC = 3.6 V
VI = VIH or VIL; VO = 5.5 V or GND;
-
-
-
-
-
GND
-
0.2
0.4
0.55
±5
V
V
-
V
ILI
±0.1
0.1
µA
µA
IOZ
3-state output OFF-state
current
±5
VCC = 3.6 V
Ioff
power-off leakage supply
current
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
0.1
0.1
5
±10
10
500
-
µA
µA
µA
pF
ICC
∆ICC
CI
quiescent supply current
VI = VCC or GND; IO = 0 A;
V
CC = 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.7 V to 3.6 V
[2]
additional quiescent supply
current per pin
V
input capacitance
5.0
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
VCC = 1.2 V
VCC
-
-
-
-
-
V
V
V
V
VCC = 2.7 V to 3.6 V
2.0
-
VIL
LOW-level input voltage
HIGH-level output voltage
VCC = 1.2 V
-
-
0
VCC = 2.7 V to 3.6 V
0.8
VOH
VI = VIH or VIL
IO = −100 µA; VCC = 2.7 V to 3.6 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
V
V
V
V
CC − 0.3
-
-
-
-
-
V
V
V
V
CC − 0.65 -
CC − 0.75 -
CC − 1
-
VOL
LOW-level output voltage
input leakage current
IO = 100 µA; VCC = 2.7 V to 3.6 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VI = 5.5 V or GND; VCC = 3.6 V
VI = VIH or VIL; VO = 5.5 V or GND;
-
-
-
-
-
-
-
-
-
-
0.3
0.6
0.8
±20
±20
V
V
V
ILI
µA
µA
IOZ
3-state output OFF-state
current
VCC = 3.6 V
Ioff
power-off leakage supply
current
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
-
-
±20
40
µA
µA
µA
ICC
∆ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
V
CC = 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.7 V to 3.6 V
additional quiescent supply
current per pin
5000
V
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
8 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
[1] All typical values are measured Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
11. Dynamic characteristics
Table 8:
Dynamic characteristics
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 10
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
tPHL, tPLH propagation delay CP to Qn
see Figure 7
VCC = 1.2 V
-
18
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
8.5
7.3
[2]
[2]
[2]
[2]
[2]
[2]
VCC = 3.0 V to 3.6 V
see Figure 9
3.7
tPZH, tPZL 3-state output enable time OE to Qn
tPHZ, tPLZ 3-state output disable time OE to Qn
VCC = 1.2 V
-
20
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.3
8.8
7.6
VCC = 3.0 V to 3.6 V
see Figure 9
3.5
VCC = 1.2 V
-
9.0
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
6.8
6.2
VCC = 3.0 V to 3.6 V
see Figure 7
3.0
tW
clock pulse width HIGH or LOW
set-up time Dn to CP
VCC = 1.2 V
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
3.3
3.3
-
VCC = 3.0 V to 3.6 V
see Figure 8
1.7
tsu
VCC = 1.2 V
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
0.9
1.9
-
VCC = 3.0 V to 3.6 V
see Figure 8
0.6
th
hold time Dn to CP
VCC = 1.2 V
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
-
VCC = 3.0 to 3.6 V
see Figure 7
0.0
fmax
maximum clock frequency
VCC = 1.2 V
-
-
-
MHz
MHz
MHz
ns
VCC = 2.7 V
150
150
-
-
-
[2]
[3]
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V
200
-
-
tsk(0)
CPD
skew
1.0
[4] [5]
power dissipation capacitance per gate
outputs enabled
outputs disabled
-
-
17
11
-
-
pF
pF
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
9 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 10
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay CP to Qn
see Figure 7
VCC = 1.2 V
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
11.0
9.5
VCC = 3.0 V to 3.6 V
see Figure 9
tPZH, tPZL 3-state output enable time OE to Qn
tPHZ, tPLZ 3-state output disable time OE to Qn
VCC = 1.2 V
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.3
11.0
9.5
VCC = 3.0 V to 3.6 V
see Figure 9
VCC = 1.2 V
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
8.5
8.0
VCC = 3.0 V to 3.6 V
see Figure 7
tW
clock pulse width HIGH or LOW
set-up time Dn to CP
hold time Dn to CP
maximum clock frequency
skew
VCC = 1.2 V
-
-
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
3.3
3.3
VCC = 3.0 V to 3.6 V
see Figure 8
tsu
VCC = 1.2 V
-
-
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
0.9
1.9
VCC = 3.0 V to 3.6 V
see Figure 8
th
VCC = 1.2 V
-
-
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
VCC = 3.0 V to 3.6 V
see Figure 7
fmax
VCC = 1.2 V
-
-
-
-
-
-
MHz
MHz
MHz
ns
VCC = 2.7 V
150
150
-
-
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
-
[3]
tsk(0)
1.0
[1] All typical values are measured Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ (CL × VCC2 × fo) = sum of the outputs.
[5] The condition is VI = GND to VCC
9397 750 13276
.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
10 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
12. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
mna894
Measurement points are given in Table 9.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the
maximum clock pulse frequency.
Table 9:
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5 × VCC
1.5 V
0.5 × VCC
1.5 V
≥ 2.7 V
V
I
V
M
CP input
GND
t
t
su
su
t
t
h
h
V
I
V
M
Dn input
GND
V
OH
V
Qn output
M
V
OL
mna202
Measurement points are given in Table 10.
VOL and VOH are the typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output
performance.
Fig 8. Data set-up and hold times for the Dn input to the CP input.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
11 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
Table 10: Measurement points
Supply voltage
VCC
Input
Output
VM
VM
< 2.7 V
0.5 × VCC
1.5 V
0.5 × VCC
1.5 V
≥ 2.7 V
V
I
OE input
V
V
M
M
GND
t
t
PZL
PLZ
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mgu775
Measurement points are given in Table 11.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig 9. 3-state enable and disable times.
Table 11: Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
< 2.7 V
0.5 × VCC
1.5 V
0.5 × VCC
1.5 V
VOL + 0.1 × VCC
VOL + 0.3 V
V
OH − 0.1 × VCC
OH − 0.3 V
≥ 2.7 V
V
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
Data test circuit (see Table 12).
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse
generator.
Fig 10. Load circuitry for switching times.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
12 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
Table 12: Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCC
2 × VCC
2 × VCC
1.2 V
VCC
2.7 V
2.7 V
50 pF
50 pF
50 pF
500 Ω [1]
500 Ω
500 Ω
2.7 V
open
GND
3.0 V to 3.6 V
open
GND
[1] The circuit performs better when RL = 1000 Ω.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
13 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 11. Package outline SO24.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
14 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT340-1
MO-150
Fig 12. Package outline SSOP24.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
15 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 13. Package outline TSSOP24.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
16 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
A
A
E
1
c
detail X
terminal 1
index area
C
e
1
terminal 1
index area
y
y
v
M
C
C
A B
C
1
e
b
w
M
2
11
L
12
13
1
e
E
h
2
24
23
14
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
1
2
1
h
max.
0.05 0.30
0.00 0.18
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
0.3
mm
1
0.2
0.5
4.5
1.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-29
SOT815-1
- - -
- - -
- - -
Fig 14. Package outline DHVQFN24.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
17 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
14. Revision history
Table 13: Revision history
Document ID
74LVC821A_3
Modifications:
74LVC821A_2
74LVC821A_1
Release date Data sheet status
20040511 Product data
• Figure 4: corrected.
Change notice Order number
Supersedes
-
9397 750 13276 74LVC821A_2
20040415
Product data
-
-
9397 750 13047 74LVC821A_1
19980925
Product specification
9397 750 04584
-
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
18 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
19 of 20
74LVC821A
Philips Semiconductors
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information . . . . . . . . . . . . . . . . . . . . 19
8
9
10
11
12
13
14
15
16
17
18
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 11 May 2004
Document order number: 9397 750 13276
Published in The Netherlands
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