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74LVCH16245AEV,157 [NXP]

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74LVCH16245AEV,157
型号： 74LVCH16245AEV,157
厂家： NXP    NXP
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74LVC16245A; 74LVCH16245A  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
Rev. 12 — 13 February 2012  
Product data sheet  
1. General description  
The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting  
3-state bus compatible outputs in both send and receive directions. The device features  
two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for  
direction control. nOE controls the outputs so that the buses are effectively isolated. This  
device can be used as two 8-bit transceivers or one 16-bit transceiver.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed  
3.3 V and 5 V applications.  
The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up  
resistors to hold unused inputs.  
2. Features and benefits  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
MULTIBYTE flow-through standard pin-out architecture  
Low inductance multiple power and ground pins for minimum noise and ground  
bounce  
Direct interface with TTL levels  
High-impedance when VCC = 0 V  
All data inputs have bus hold (74LVCH16245A only)  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Temperature range Package  
Name  
Description  
Version  
74LVC16245ADL  
74LVCH16245ADL  
74LVC16245ADGG  
74LVCH16245ADGG  
74LVC16245AEV  
74LVCH16245AEV  
74LVC16245ABX  
74LVCH16245ABX  
40 C to +125 C  
40 C to +125 C  
40 C to +125 C  
40 C to +125 C  
SSOP48  
plastic shrink small outline package; 48 leads;  
body width 7.5 mm  
SOT370-1  
TSSOP48  
VFBGA56  
HXQFN60  
plastic thin shrink small outline package;  
48 leads; body width 6.1 mm  
SOT362-1  
plastic very thin fine-pitch ball grid array package; SOT702-1  
56 balls; body 4.5 7 0.65 mm  
plastic compatible thermal enhanced extremely  
thin quad flat package; no leads; 60 terminals;  
body 4 6 0.5 mm  
SOT1134-2  
4. Functional diagram  
2DIR  
1DIR  
2OE  
2B0  
2B1  
2B2  
2B3  
2B4  
2B5  
2B6  
1OE  
1B0  
2A0  
2A1  
2A2  
2A3  
2A4  
2A5  
2A6  
2A7  
1A0  
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
1A7  
1B1  
1B2  
1B3  
1B4  
1B5  
1B6  
1B7  
2B7  
001aaa789  
Fig 1. Logic symbol  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
2 of 20  
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
1OE  
G3  
1DIR  
3EN1[BA]  
3EN2[AB]  
G6  
2OE  
6EN1[BA]  
6EN2[AB]  
2DIR  
1A0  
1B0  
1
2
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
1A7  
1B1  
1B2  
1B3  
1B4  
1B5  
1B6  
1B7  
2B0  
2A0  
4
5
2A1  
2A2  
2A3  
2A4  
2A5  
2A6  
2A7  
2B1  
2B2  
2B3  
2B4  
2B5  
2B6  
2B7  
001aaa790  
Fig 2. IEC logic symbol  
V
CC  
data input  
to internal circuit  
mna705  
Fig 3. Bus hold circuit  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
3 of 20  
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
5. Pinning information  
5.1 Pinning  
74LVC16245A  
74LVCH16245A  
1OE  
1A0  
1A1  
GND  
1A2  
1A3  
1DIR  
1B0  
1B1  
GND  
1B2  
1B3  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
3
4
5
6
V
V
CC  
7
CC  
1A4  
1A5  
GND  
1A6  
1A7  
2A0  
2A1  
GND  
2A2  
2A3  
1B4  
1B5  
GND  
1B6  
1B7  
2B0  
2B1  
GND  
2B2  
2B3  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
74LVC16245A  
74LVCH16245A  
ball A1  
index area  
1
2 3 4 5 6  
A
B
C
D
E
F
G
H
J
V
CC  
V
CC  
2B4 19  
2B5 20  
GND 21  
2B6 22  
2B7 23  
2DIR 24  
30 2A4  
29 2A5  
28 GND  
27 2A6  
26 2A7  
25 2OE  
K
001aad111  
Transparent top view  
001aad110  
Fig 4. Pin configuration SOT370-1 (SSOP48) and  
SOT362-1 (TSSOP48)  
Fig 5. Pin configuration SOT702-1 (VFBGA56)  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
4 of 20  
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
terminal 1  
index area  
D1  
A32  
D5  
A31  
A30  
A29  
A28  
A27  
D8  
D4  
B20  
B19  
B18  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A26  
A25  
A24  
A23  
A22  
A21  
A20  
A19  
A18  
A17  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B17  
B16  
B15  
B14  
B13  
B12  
B11  
74LVC16245A  
74LVCH16245A  
(1)  
GND  
D6  
B8  
B9  
B10  
D7  
D2  
A11  
A12  
A13  
A14  
A15  
A16  
D3  
001aai894  
Transparent top view  
(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or  
mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to  
GND.  
Fig 6. Pin configuration SOT1134-2 (HXQFN60)  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
5 of 20  
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
5.2 Pin description  
Table 2.  
Symbol  
Pin description  
Pin  
Description  
SOT1134-2  
SOT370-1 and  
SOT362-1  
SOT702-1  
1DIR, 2DIR 1, 24  
A1, K1  
A30, A13  
direction control input  
data input/output  
1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, B2, B1, C2, C1, D2, D1, B20, A31, D5, D1, A2,  
12 E2, E1 B2, B3, A5  
2B0 to 2B7 13, 14, 16, 17, 19, F1, F2, G1, G2, H1, H2, A6, B5, B6, A9, D2, D6, data input/output  
20, 22, 23  
J1, J2  
A12, B8  
GND  
VCC  
4, 10, 15, 21, 28,  
34, 39, 45  
B3, B4, D3, D4, G3, G4, A32, A3, A8, A11, A16,  
ground (0 V)  
J3, J4  
A19, A24, A27  
A1, A10, A17, A26  
A29, A14  
7, 18, 31, 42  
C3, C4, H3, H4  
A6, K6  
supply voltage  
1OE, 2OE 48, 25  
output enable input (active LOW)  
1A0 to 1A7 47, 46, 44, 43, 41, B5, B6, C5, C6, D5, D6, B18, A28, D8, D4, A25, data input/output  
40, 38, 37 E5, E6 B16, B15, A22  
2A0 to 2A7 36, 35, 33, 32, 30, F6, F5, G6, G5, H6, H5, A21, B13, B12, A18, D3, data input/output  
29, 27, 26  
J6, J5  
D7, A15, B10  
n.c.  
-
A2, A3, A4, A5, K2, K3, A4, A7, A20, A23, B1,  
not connected  
K4, K5  
B4, B7, B9, B11, B14,  
B17, B19  
6. Functional description  
Table 3.  
Function table[1]  
Inputs  
Outputs  
nAn  
nOE  
L
nDIR  
nBn  
L
nAn = nBn  
inputs  
Z
inputs  
nBn = nAn  
Z
L
H
X
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
6 of 20  
 
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
0.5  
50  
0.5  
-
Max  
+6.5  
-
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
[1]  
VI  
+6.5  
50  
VCC + 0.5  
+6.5  
50  
100  
-
IOK  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
output HIGH or LOW  
output 3-state  
mA  
V
[2]  
[2]  
VO  
0.5  
0.5  
-
V
IO  
output current  
VO = 0 V to VCC  
mA  
mA  
mA  
C  
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
100  
65  
storage temperature  
total power dissipation  
+150  
Tamb = 40 C to +125 C;  
(T)SSOP48 package  
VFBGA56 package  
[3]  
[4]  
[4]  
-
-
-
500  
mW  
mW  
mW  
1000  
1000  
HXQFN60 package  
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.  
[2] The output voltage ratings may be exceeded if the output current ratings are observed.  
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.  
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.  
8. Recommended operating conditions  
Table 5.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
1.65  
1.2  
0
Typ  
Max  
3.6  
Unit  
supply voltage  
-
-
-
-
-
-
-
-
V
functional  
3.6  
5.5  
V
VI  
input voltage  
V
VO  
output voltage  
output HIGH or LOW  
output 3-state  
0
VCC  
5.5  
V
0
V
Tamb  
ambient temperature  
in free air  
40  
0
+125  
20  
C  
ns/V  
ns/V  
t/V  
input transition rise and fall rate  
VCC = 1.2 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
0
10  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
7 of 20  
 
 
 
 
 
 
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
9. Static characteristics  
Table 6.  
Static characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter Conditions 40 C to +85 C  
40 C to +125 C  
Unit  
Min  
Typ[1]  
Max  
Min  
Max  
VIH  
HIGH-level input VCC = 1.2 V  
voltage  
1.08  
-
-
-
-
-
-
-
-
-
1.08  
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V  
0.65 VCC  
-
0.65 VCC  
-
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
1.7  
-
1.7  
-
2.0  
-
0.12  
2.0  
-
0.12  
VIL  
LOW-level input VCC = 1.2 V  
-
-
-
-
-
-
-
-
voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VI = VIH or VIL  
0.35 VCC  
0.7  
0.35 VCC  
0.7  
0.8  
0.8  
VOH  
HIGH-level  
output voltage  
IO = 100 A;  
VCC 0.2  
-
-
VCC 0.3  
-
V
VCC = 1.65 V to 3.6 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 18 mA; VCC = 3.0 V  
IO = 24 mA; VCC = 3.0 V  
1.2  
1.8  
2.2  
2.4  
2.2  
-
-
-
-
-
-
-
-
-
-
1.05  
1.65  
2.05  
2.25  
2.0  
-
-
-
-
-
V
V
V
V
V
VOL  
LOW-leveloutput VI = VIH or VIL  
voltage  
IO = 100 A;  
-
-
0.2  
-
0.3  
V
VCC = 1.65 V to 3.6 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
-
-
-
-
-
-
0.45  
0.6  
-
-
-
-
-
0.65  
0.8  
V
-
V
-
-
0.4  
0.6  
V
0.55  
5  
0.8  
V
II  
input leakage  
current[2]  
VI = 5.5 V or GND;  
VCC = 3.6 V  
0.1  
20  
A  
IOZ  
OFF-state output VI = VIH or VIL;  
-
0.1  
5  
-
20  
A  
current[2][3]  
VO = 5.5 V or GND;  
CC = 3.6 V  
V
IOFF  
ICC  
power-off  
leakage current  
VI or VO = 5.5 V; VCC = 0.0 V  
-
-
-
-
-
0.1  
0.1  
5
10  
20  
500  
-
-
-
-
-
-
20  
A  
A  
A  
pF  
pF  
supply current  
VI = VCC or GND; IO = 0 A;  
VCC = 3.6 V  
80  
ICC  
CI  
additional supply per input pin; VI = VCC 0.6 V;  
current IO = 0 A; VCC = 2.7 V to 3.6 V  
5000  
input capacitance VCC = 0 V to 3.6 V;  
VI = GND to VCC  
5.0  
10  
-
-
CI/O  
input/output  
capacitance  
VCC = 0 V to 3.6 V;  
VI = GND to VCC  
-
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
8 of 20  
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
Table 6.  
Static characteristics …continued  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C  
Unit  
Min  
Typ[1]  
Max  
Min  
10  
Max  
IBHL  
bus hold LOW  
current [4][5]  
VCC = 1.65; VI = 0.58 V  
VCC = 2.3; VI = 0.7 V  
VCC = 3.0; VI = 0.8 V  
VCC = 1.65; VI = 1.07 V  
VCC = 2.3; VI = 1.7 V  
VCC = 3.0; VI = 2.0 V  
VCC = 1.95 V  
10  
30  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A  
A  
A  
A  
A  
A  
A  
A  
A  
A  
A  
A  
25  
75  
60  
IBHH  
bus hold HIGH  
current [4][5]  
10  
30  
75  
200  
300  
500  
200  
300  
500  
10  
25  
60  
200  
300  
500  
200  
300  
500  
IBHLO  
bus hold LOW  
overdrive current  
[4][6]  
VCC = 2.7 V  
VCC = 3.6 V  
IBHHO  
bus hold HIGH  
overdrive current  
[4][6]  
VCC = 1.95 V  
VCC = 2.7 V  
VCC = 3.6 V  
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.  
[2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal.  
[3] For I/O ports the parameter IOZ includes the input leakage current.  
[4] Valid for data inputs of bus hold parts only (74LVCH16245A). Note that control inputs do not have a bus hold circuit.  
[5] The specified sustaining current at the data input holds the input below the specified VI level.  
[6] The specified overdrive current at the data input forces the data input to the opposite input state.  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[2]  
Max  
Min  
Max  
[1]  
tpd  
propagation  
delay  
nAn to nBn; nBn to nAn; see Figure 7  
VCC = 1.2 V  
-
13.0  
5.2  
2.8  
2.7  
2.4  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.5  
1.0  
1.0  
1.0  
12.2  
6.0  
4.7  
4.5  
1.5  
1.0  
1.0  
1.0  
13.8  
6.7  
6.0  
6.0  
VCC = 3.0 V to 3.6 V  
nOE to nAn, nBn; see Figure 8  
VCC = 1.2 V  
[1]  
ten  
enable time  
-
15.0  
5.9  
3.3  
3.5  
2.7  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.5  
1.0  
1.5  
1.0  
15.0  
7.9  
6.7  
5.5  
1.5  
1.0  
1.5  
1.0  
16.9  
8.8  
8.5  
7.0  
VCC = 3.0 V to 3.6 V  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
9 of 20  
 
 
 
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
Table 7.  
Dynamic characteristics …continued  
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[2]  
Max  
Min  
Max  
[1]  
tdis  
disable time  
nOE to nAn, nBn; see Figure 8  
VCC = 1.2 V  
-
11.0  
4.9  
2.7  
3.4  
3.3  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
0.5  
1.5  
1.5  
13.1  
7.1  
6.6  
5.6  
1.0  
0.5  
1.5  
1.5  
14.7  
7.9  
8.5  
7.0  
VCC = 3.0 V to 3.6 V  
per input; VI = GND to VCC  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
[3]  
CPD  
power  
dissipation  
capacitance  
-
-
-
11.5  
15.2  
18.5  
-
-
-
-
-
-
-
-
-
pF  
pF  
pF  
[1] tpd is the same as tPLH and tPHL  
ten is the same as tPZL and tPZH  
tdis is the same as tPLZ and tPHZ  
.
.
.
[2] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.  
[3] CPD is used to determine the dynamic power dissipation (PD in W).  
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz; fo = output frequency in MHz  
CL = output load capacitance in pF  
VCC = supply voltage in Volts  
N = number of inputs switching  
(CL VCC2 fo) = sum of the outputs.  
11. Waveforms  
V
I
nAn, nBn  
input  
V
M
GND  
t
t
PHL  
PLH  
V
OH  
nBn, nAn  
output  
V
M
mna477  
V
OL  
Measurement points are given in Table 8.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 7. The input (nAn, nBn) to output (nBn, nAn) propagation delays  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
10 of 20  
 
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
V
I
nOE input  
GND  
V
M
t
t
PZL  
PLZ  
V
CC  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
X
V
OL  
t
t
PHZ  
PZH  
V
OH  
V
Y
output  
HIGH-to-OFF  
OFF-to-HIGH  
V
M
GND  
outputs  
enabled  
outputs  
enabled  
outputs  
disabled  
mna362  
Measurement points are given in Table 8.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 8. 3-state enable and disable times  
Table 8.  
Measurement points  
Supply voltage  
VCC  
VM  
Input  
VI  
tr = tf  
VX  
VY  
1.2 V  
0.5 VCC  
0.5 VCC  
0.5 VCC  
1.5 V  
VCC  
VCC  
VCC  
2.7 V  
2.7 V  
2.5 ns  
2.5 ns  
2.5 ns  
2.5 ns  
2.5 ns  
VOL + 0.15 V  
VOL + 0.15 V  
VOL + 0.15 V  
VOL + 0.3 V  
VOL + 0.3 V  
VOH 0.15 V  
VOH 0.15 V  
VOH 0.15 V  
VOH 0.3 V  
VOH 0.3 V  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
3.0 V to 3.6 V  
1.5 V  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
11 of 20  
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
EXT  
R
V
CC  
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
001aae331  
Test data is given in Table 9.  
Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig 9. Test circuit for measuring switching times  
Table 9.  
Test data  
Supply voltage  
Input  
VI  
Load  
CL  
VEXT  
tr, tf  
RL  
tPLH, tPHL  
open  
tPLZ, tPZL  
2 VCC  
2 VCC  
2 VCC  
2 VCC  
2 VCC  
tPHZ, tPZH  
GND  
1.2 V  
VCC  
VCC  
VCC  
2.7 V  
2.7 V  
2 ns  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
30 pF  
50 pF  
50 pF  
1 k  
1 k  
500   
500   
500   
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
open  
GND  
open  
GND  
open  
GND  
3.0 V to 3.6 V  
open  
GND  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
12 of 20  
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
12. Package outline  
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm  
SOT370-1  
D
E
A
X
c
y
H
v
M
A
E
Z
25  
48  
Q
A
2
A
A
(A )  
3
1
θ
pin 1 index  
L
p
L
24  
1
detail X  
w M  
b
p
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.  
8o  
0o  
0.4  
0.2  
2.35  
2.20  
0.3  
0.2  
0.22 16.00  
0.13 15.75  
7.6  
7.4  
10.4  
10.1  
1.0  
0.6  
1.2  
1.0  
0.85  
0.40  
mm  
2.8  
0.25  
0.635  
1.4  
0.25  
0.18  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT370-1  
MO-118  
Fig 10. Package outline SOT370-1 (SSOP48)  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
13 of 20  
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm  
SOT362-1  
E
D
A
X
c
H
v
M
A
y
E
Z
48  
25  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
detail X  
1
24  
w
M
b
e
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions).  
A
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.15  
0.05  
1.05  
0.85  
0.28  
0.17  
0.2  
0.1  
12.6  
12.4  
6.2  
6.0  
8.3  
7.9  
0.8  
0.4  
0.50  
0.35  
0.8  
0.4  
mm  
1.2  
0.5  
1
0.25  
0.25  
0.08  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT362-1  
MO-153  
Fig 11. Package outline SOT362-1 (TSSOP48)  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
14 of 20  
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm  
SOT702-1  
B
A
D
ball A1  
index area  
A
2
A
E
A
1
detail X  
e
1
C
∅ v M  
∅ w M  
C
C
A B  
b
e
y
y
C
1
1/2 e  
K
J
H
G
F
e
e
2
E
D
C
B
A
1/2 e  
X
ball A1  
index area  
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)  
A
A
A
b
e
y
UNIT  
D
E
e
e
v
w
y
1
1
2
0
2.5  
5 mm  
1
2
max.  
0.3  
0.2  
0.7  
0.6  
0.45  
0.35  
4.6  
4.4  
7.1  
6.9  
scale  
mm  
1
3.25 5.85  
0.08  
0.1  
0.65  
0.15 0.08  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
02-08-08  
03-07-01  
SOT702-1  
MO-225  
Fig 12. Package outline SOT702-1 (VFBGA56)  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
15 of 20  
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;  
60 terminals; body 4 x 6 x 0.5 mm  
SOT1134-2  
D
B
A
terminal 1  
index area  
A
A
2
E
A
1
detail X  
e
2
b
v
C
C
A
B
w
e
1
eR  
C
C
A
B
e
v
C
eT  
1/2 e  
B8 B10  
w
y
y
C
1
L
1
D2  
A11  
A16  
D3  
D7  
D6  
L
A17  
B11  
A10  
B7  
e
eR  
eT  
E
h
e
3
e
4
1/2 e  
B1  
A1  
B17  
A26  
terminal 1  
index area  
D5  
D1  
B20 B18  
D8  
D4  
eT  
eR  
A32  
A27  
X
D
h
K
eT  
eR  
0
5 mm  
Dimensions  
Unit  
A
A
1
A
2
b
D
D
h
E
E
e
e
e
2
e
3
e
eR eT  
K
L
L
v
w
y
y
1
h
1
4
1
max 0.50 0.08 0.42 0.28 4.1 1.95 6.1 3.95  
0.25 0.28 0.195  
mm nom  
min  
0.05 0.40 0.23 4.0 1.85 6.0 3.85 0.5 1.0 2.5 3.0 4.5 0.5 0.49 0.20 0.23 0.145 0.1 0.05 0.08 0.1  
0.02 0.38 0.18 3.9 1.75 5.9 3.75  
0.15 0.18 0.095  
sot1134-2_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
- - -  
JEDEC  
- - -  
JEITA  
- - -  
SOT1134-2  
11-08-15  
Fig 13. Package outline SOT1134-2 (HXQFN60)  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
16 of 20  
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
13. Abbreviations  
Table 10. Abbreviations  
Acronym  
CDM  
DUT  
Description  
Charged Device Model  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
HBM  
MM  
TTL  
Transistor-Transistor Logic  
14. Revision history  
Table 11. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
74LVC_LVCH16245A v.12 20120213  
Product data sheet  
-
74LVC_LVCH16245A v.11  
Modifications:  
• For type number 74LVC16245ABX and 74LVCH16245ABX the sot code has changed to  
SOT1134-2.  
74LVC_LVCH16245A v.11 20111208  
Modifications: • Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges.  
74LVC_LVCH16245A v.10 20110623 Product data sheet 74LVC_LVCH16245A v.9  
Product data sheet  
-
74LVC_LVCH16245A v.10  
-
Modifications:  
• type numbers 74LVC16245ABQ and 74LVCH16245ABQ changed to 74LVC16245ABX  
and 74LVCH16245ABX.  
• Figure 6: figure note 1 changed.  
74LVC_LVCH16245A v.9  
74LVC_LVCH16245A v.8  
74LVC_LVCH16245A v.7  
74LVC_LVCH16245A v.6  
74LVC_LVCH16245A v.5  
74LVC_H16245A v.4  
20100329  
20081106  
20031125  
20030130  
20021030  
19970925  
Product data sheet  
Product data sheet  
Product specification  
Product specification  
Product specification  
Product specification  
-
-
-
-
-
-
74LVC_LVCH16245A v.8  
74LVC_LVCH16245A v.7  
74LVC_LVCH16245A v.6  
74LVC_LVCH16245A v.5  
74LVC_H16245A v.4  
74LVC16245A_  
74LVCH16245A v.3  
74LVC16245A_  
19970925  
Product specification  
-
74LVC16245A v.2  
74LVCH16245A v.3  
74LVC16245A v.2  
74LVC16245A v.1  
19970801  
-
Product specification  
-
-
-
74LVC16245A v.1  
-
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
17 of 20  
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use — NXP Semiconductors products are not designed,  
15.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
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applying the customer’s general terms and conditions with regard to the  
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Notwithstanding any damages that customer might incur for any reason  
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construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
18 of 20  
 
 
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
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NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
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Translations — A non-English (translated) version of a document is for  
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non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74LVC_LVCH16245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 12 — 13 February 2012  
19 of 20  
 
 
74LVC16245A; 74LVCH16245A  
NXP Semiconductors  
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state  
17. Contents  
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6  
6
Functional description . . . . . . . . . . . . . . . . . . . 6  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Recommended operating conditions. . . . . . . . 7  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17  
7
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 19  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2012.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 13 February 2012  
Document identifier: 74LVC_LVCH16245A  
 

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