74LVCH16373ADGG:51 [NXP]
74LVC(H)16373A - 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state TSSOP 48-Pin;
| 型号： | 74LVCH16373ADGG:51 |
| 厂家： | 
NXP |
| 描述： | 74LVC(H)16373A - 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state TSSOP 48-Pin 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 8 — 6 January 2014
Product data sheet
1. General description
The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring
separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state
outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable
(OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices.
When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of
these devices in mixed 3.3 V and 5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the
latches are transparent, that is, the latch outputs change each time its corresponding
D-input changes. The latches store the information that was present at the D-inputs one
set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs. When OE is HIGH, the outputs
go to the high impedance OFF-state. Operation of the OE input does not affect the state of
the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors
to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A only)
High-impedance when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC16373ADGG
74LVCH16373ADGG
74LVC16373ADL
40 C to +125 C
TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
40 C to +125 C
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVCH16373ADL
4. Functional diagram
1
1EN
C3
1OE
1LE
2OE
2LE
1
24
48
24
25
2EN
C4
1OE
2OE
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
3
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1
3D
5
6
5
8
6
9
8
11
12
13
14
16
17
19
20
22
23
9
11
12
13
14
16
17
19
20
22
23
4D
2
1LE
48
2LE
25
mgu768
mgu770
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
2 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
1D0
1Q0
2D0
2Q0
D
Q
D
Q
LATCH
1
LATCH
9
LE LE
LE LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
mgu769
Fig 3. Logic diagram
V
CC
data input
to internal circuit
mgu771
Fig 4. Bus hold circuit
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
3 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
1
2
48
47
46
1LE
1D0
1D1
1OE
1Q0
1Q1
GND
1Q2
1Q3
3
4
45 GND
44 1D2
43 1D3
V
5
6
V
CC
7
42
CC
8
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
V
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
16373A
V
CC
31
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
2Q4
2Q5
GND
2Q6
2Q7
2OE
2LE
25
001aad112
Fig 5. Pin configuration SSOP48 and TSSOP48
5.2 Pin description
Table 2.
Symbol
1OE
Pin description
Pin
Description
1
output enable input (active LOW)
output enable input (active LOW)
latch enable input (active HIGH)
latch enable input (active HIGH)
ground (0 V)
2OE
24
1LE
48
2LE
25
GND
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
VCC
supply voltage
1Q[0:7]
2Q[0:7]
1D[0:7]
2D[0:7]
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
data output
data output
data input
data input
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
4 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3.
Function table
Per section of eight bits [1]
.
Operating modes
Input
Internal latch
Output
nQ0 to nQ7
nOE
L
nLE
H
nDn
Enable and read register
(transparent mode)
L
H
l
L
L
L
H
H
L
H
L
Latch and read register
L
L
L
L
h
l
H
L
H
Z
Z
Latch register and disable outputs
H
L
H
L
h
H
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition
Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0
mA
V
[1]
VI
+6.5
50
VCC + 0.5
+6.5
50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0
output HIGH or LOW state
output 3-state
mA
V
[2]
[2]
VO
0.5
0.5
-
V
IO
output current
VO = 0 V to VCC
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
100
65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
5 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
1.65
1.2
0
Typ
Max
3.6
3.6
5.5
VCC
5.5
+125
20
Unit
V
supply voltage
-
-
-
-
-
-
-
-
functional
V
VI
input voltage
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
V
0
V
Tamb
ambient temperature
in free air
40
0
C
ns/V
ns/V
t/V
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
10
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
1.08
-
-
-
-
-
-
-
-
-
1.08
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V
0.65 VCC
-
0.65 VCC
-
VCC = 2.3 V to 2.7 V
1.7
-
1.7
-
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
2.0
-
0.12
2.0
-
0.12
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
0.35 VCC
0.7
0.35 VCC
0.7
0.8
0.8
VOH
HIGH-level
output
voltage
IO = 100 A;
VCC = 1.65 V to 3.6 V
VCC 0.2
-
-
VCC 0.3
-
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 18 mA; VCC = 3.0 V
IO = 24 mA; VCC = 3.0 V
VI = VIH or VIL
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output
voltage
IO = 100 A;
-
-
0.2
-
0.3
V
VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
-
0.45
0.6
-
-
-
-
-
0.65
0.8
V
-
V
-
-
0.4
0.6
V
0.55
5
0.8
V
II
input leakage VCC = 3.6 V;
current
VI = 5.5 V or GND[2]
0.1
20
A
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
6 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
IOZ
OFF-state
output
VI = VIH or VIL; VCC = 3.6 V;
VO = 5.5 V or GND[2]
-
0.1
5
-
20
A
current
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
-
0.1
5
20
-
-
80
A
A
ICC
additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
500
5000
CI
input
VCC = 0 V to 3.6 V;
-
5.0
-
-
-
pF
capacitance VI = GND to VCC
IBHL
bus hold
LOW current
VCC = 1.65; VI = 0.58 V[3][4]
10
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
25
-
-
-
-
-
-
-
-
-
A
A
A
A
A
A
A
A
A
VCC = 2.3; VI = 0.7 V
VCC = 3.0; VI = 0.8 V
VCC = 1.65; VI = 1.07 V[3][4]
VCC = 2.3; VI = 1.7 V
VCC = 3.0; VI = 2.0 V
VCC = 1.95 V[3][5]
75
60
IBHH
bus hold
HIGH current
10
30
75
200
300
500
10
25
60
200
300
500
IBHLO
bus hold
LOW
overdrive
current
VCC = 2.7 V
VCC = 3.6 V
IBHHO
bus hold
HIGH
overdrive
current
VCC = 1.95 V[3][5]
VCC = 2.7 V
200
300
500
-
-
-
-
-
-
200
300
500
-
-
-
A
A
A
VCC = 3.6 V
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
[2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
[3] Valid for data inputs (74LVCH16373A) only; control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
7 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation
delay
Dn to Qn; see Figure 6
VCC = 1.2 V
-
12
5.4
2.9
2.9
2.4
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.5
1.0
11.4
5.7
4.9
4.4
1.5
1.0
1.5
1.0
13.2
6.6
6.5
5.5
VCC = 3.0 V to 3.6 V
LE to Qn; see Figure 7
VCC = 1.2 V
-
14
6.4
3.4
3.0
2.9
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.5
12.4
6.1
5.3
4.8
2.0
1.5
1.5
1.5
14.4
7.1
7.0
6.0
VCC = 3.0 V to 3.6 V
OE to Qn; see Figure 8
VCC = 1.2 V
[2]
ten
enable time
-
18
5.5
3.1
3.3
2.5
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
1.5
1.0
1.5
1.0
12.4
6.6
5.7
4.9
1.5
1.0
1.5
1.0
14.3
7.6
7.5
6.5
V
CC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
OE to Qn; see Figure 8
VCC = 1.2 V
[2]
tdis
disable time
-
11
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.8
1.0
1.5
1.5
4.5
2.5
3.3
3.1
9.1
5.1
6.3
5.4
2.8
1.0
1.5
1.5
10.5
6.0
8.0
7.0
VCC = 3.0 V to 3.6 V
LE HIGH; see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tW
pulse width
set-up time
5.0
4.0
3.0
3.0
-
-
-
-
-
-
5.0
4.0
3.0
3.0
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
Dn to LE; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
tsu
3.0
2.5
2.0
2.0
-
-
-
-
-
-
3.0
2.5
2.0
2.0
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
1.0
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
8 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
th
hold time
Dn to LE; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.5
2.0
0.9
+0.9
-
-
-
2.5
2.0
0.9
+0.9
-
-
ns
ns
ns
ns
ns
-
-
-
-
-
-
1.0
-
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
-
-
[3]
[4]
tsk(o)
CPD
output skew
time
1.0
1.5
power
dissipation
capacitance
per input; VI = GND to VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
10.8
13.0
15.0
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 3.0 V to 3.6 V
[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] PD is used to determine the dynamic power dissipation (PD in W).
.
.
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs
11. Waveforms
V
I
V
I
LE input
GND
V
t
V
V
t
M
M
M
V
V
M
Dn input
GND
M
t
W
PHL
t
t
PLH
PHL
PLH
V
V
OH
OH
V
V
M
Qn output
V
Qn output
V
M
M
V
OL
mgu772
OL
mgu773
Measurement points are given in Table 8.
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur
with the output load.
VOL and VOH are typical output voltage levels that occur
with the output load.
Fig 6. Input (Dn) to output (Qn) propagation delays
Fig 7. Latch enable input (LE) pulse width, and the
latch enable input to output (Qn) propagation
delays
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
9 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
V
I
OE input
V
V
M
M
GND
t
t
PZL
PLZ
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mgu775
Measurement points are given in Table 8.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 8. 3-state enable and disable times
V
I
V
Dn input
M
GND
t
t
h
h
t
t
su
su
V
I
V
LE input
M
GND
mgu774
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times for the Dn input to the LE input
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
10 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Table 8.
Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
0.5 VCC
0.5 VCC
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
0.5 VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.15 V
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
1.5 V
1.5 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
2 ns
2 ns
2 ns
2.5 ns
2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 k
1 k
500
500
500
2 VCC
2 VCC
2 VCC
2 VCC
2 VCC
GND
GND
GND
GND
GND
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
open
open
3.0 V to 3.6 V
open
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
11 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
12. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
(1)
(2)
Unit
max
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
0.4
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Fig 11. Package outline SOT362-1 (TSSOP-48)
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
12 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
Fig 12. Package outline SOT370-1 (SSOP48)
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
13 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release
date
Data sheet status
Change
notice
Supersedes
74LVC_LVCH16373A v.8
Modifications:
20140106 Product data sheet
-
74LVC_LVCH16373A v.7
• General description corrected (errata).
20130118 Product data sheet
74LVC_LVCH16373A v.7
Modifications:
-
74LVC_LVCH16373A v.6
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage
ranges.
74LVC_LVCH16373A v.6
74LVC_LVCH16373A v.5
74LVC_H16373A v.4
20031208 Product specification
20021002 Product specification
19980317 Product specification
-
-
-
-
-
-
74LVC_LVCH16373A v.5
74LVC_H16373A v.4
74LVC16373A_74LVCH16373A v.3
74LVC16373A v.2
74LVC16373A v.1
-
74LVC16373A_74LVCH16373A v.3 19980317 Product specification
74LVC16373A v.2
74LVC16373A v.1
19970822 Product specification
-
-
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
14 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
15 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 6 January 2014
16 of 17
74LVC16373A; 74LVCH16373A
NXP Semiconductors
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 January 2014
Document identifier: 74LVC_LVCH16373A
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