74LVCH322244AEC/G_技术文档

74LVCH322244A

32-bit buffer/line driver; 30  series termination resistors; 5 V

tolerant input/output; 3-state

Rev. 3 — 16 December 2011

Product data sheet

1. General description

The 74LVCH322244A is a 32-bit non-inverting buffer/line driver with 3-state outputs. The

3-state outputs are controlled by the output enable inputs nOE. A HIGH on input nOE

causes the outputs to assume a high-impedance OFF-state.

The device is designed with 30  series termination resistors in both HIGH and LOW

output stages to reduce line noise.

To ensure the high-impedance state during power-up or power-down, input nOE should

be tied to V_CCthrough a pull-up resistor; the minimum value of the resistor is determined

by the current-sinking capability of the driver.

Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can

handle 5 V. These features allow the use of these devices in a mixed 3.3 V and 5 V

environment.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused

or floating data inputs at a valid logic level.

2. Features and benefits

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 MULTIBYTE flow-through standard pin-out architecture

 Low inductance multiple power and ground pins for minimum noise and ground

bounce

 Direct interface with TTL levels

 Integrated 30  termination resistors

 All data inputs have bus hold

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

 Packaged in plastic fine-pitch ball grid array package

3. Ordering information

Table 1:

Ordering information

Type number

Package

Temperature

range

Name

Description

Version

74LVCH322244AEC 40 C to +85 C LFBGA96

plastic low profile fine pitch ball grid array package;

96 balls; body 13.5  5.5  1.05 mm

SOT536-1

4. Functional diagram

3A0

3Y0

3Y1

3Y2

3Y3

5A0

5A1

5A2

5Y0

5Y1

5Y2

5Y3

1A0

1A1

1A2

1Y0

1Y1

1Y2

1Y3

7A0

7A1

7A2

7Y0

7Y1

7Y2

7Y3

A2

A1

B2

B1

E2

E1

F2

F1

J2

J1

K2

K1

N2

A5

A6

B5

E5

E6

F5

J5

J6

N5

N6

P5

3A1

3A2

3A3

3OE

N1

P2

P1

K5

5A3

1A3

7A3

B6

A3

F6

H4

K6

J3

P6

T4

1OE

5OE

7OE

2A0

2A1

2A2

2Y0

2Y1

2Y2

2Y3

4A0

4A1

4A2

4Y0

4Y1

4Y2

4Y3

6A0

6A1

6A2

6Y0

6Y1

6Y2

6Y3

8A0

8A1

8A2

8Y0

8Y1

8Y2

8Y3

C2

C1

D2

D1

G2

G1

H1

H2

L2

R2

R1

T1

T2

C5

C6

D5

G5

G6

H6

L5

L6

R5

R6

T6

L1

M2

M1

M5

2A3

4A3

6A3

8A3

D6

A4

H5

H3

M6

J4

T5

T3

2OE

4OE

6OE

8OE

mna472

Fig 1. Logic symbol

V

CC

data

input

to internal circuit

mna473

Fig 2. Bushold circuit

74LVCH322244A

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Product data sheet

Rev. 3 — 16 December 2011

2 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

5. Pinning information

5.1 Pinning

mna471

6

5

4

3

2

1

1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A2 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A2

1A0 1A2 2A0 2A2 3A0 3A2 4A0 4A3 5A0 5A2 6A0 6A2 7A0 7A2 8A0 8A3

2OE GND V

1OE GND V

GND GND V

GND 3OE 6OE GND V

GND 4OE 5OE GND V

GND GND V

GND 7OE

GND 8OE

CC

1Y0 1Y2 2Y0 2Y2 3Y0 3Y2 4Y0 4Y3 5Y0 5Y2 6Y0 6Y2 7Y0 7Y2 8Y0 8Y3

1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y2 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y2

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Fig 3. Pin configuration

5.2 Pin description

Table 2:

Ball

Pin description

Symbol

Description

nOE (n = 1 to 8)

1A[0:3]

2A[0:3]

3A[0:3]

4A[0:3]

5A[0:3]

6A[0:3]

7A[0:3]

8A[0:3]

1Y[0:3]

2Y[0:3]

3Y[0:3]

4Y[0:3]

5Y[0:3]

6Y[0:3]

7Y[0:3]

8Y[0:3]

V_CC

A3, A4, H4, H3, J3 J4, T4, T3

A5, A6, B5, B6

3-state output enable inputs (active LOW)

data input

C5, C6, D5, D6

E5, E6, F5, F6

G5, G6, H6, H5

J5, J6, K5, K6

L5, L6, M5, M6

N5, N6, P5, P6

R5, R6, T6, T5

A2, A1, B2, B1

data output

C2, C1, D2, D1

E2, E1, F2, F1

G2, G1, H1, H2

J2, J1, K2, K1

L2, L1, M2, M1

N2, N1, P2, P1

R2, R1, T1, T2

C3, C4, F3, F4, L3, L4, P3, P4

supply voltage

ground (0 V)

GND

B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3,

M4, N3, N4, R3, R4

74LVCH322244A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 December 2011

3 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

6. Functional description

Table 3:

Functional table^[1]

Input

nOE

L

Output

nAn

L

nYn

L

H

X

Z

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0

mA

V

[1]

V_I

+6.5

50

V_CC+ 0.5

+6.5

50

200

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0

output HIGH or LOW state

output 3-state

mA

V

[2]

V_O

0.5

-

V

I_O

output current

V_O= 0 V to V_CC

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

200

65

-

storage temperature

total power dissipation

+150

500

[3]

T_amb= 40 C to +125 C

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] Above 70 C the value of P_totderates linearly with 1.8 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

Unit

V

supply voltage

-

3.6

-

functional

V

V_I

input voltage

5.5

V_CC

5.5

V

V_O

output voltage

output HIGH or LOW state

output 3-state

0

V

0

V

T_amb

ambient temperature

in free air

40

-

+125

20

C

ns/V

t/V

input transition rise and fall rate

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

10

74LVCH322244A

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Product data sheet

Rev. 3 — 16 December 2011

4 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 1.2 V

1.08

-

1.08

-

V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

0.65  V_CC

-

0.65  V_CC

-

1.7

-

1.7

-

2.0

-

0.12

2.0

-

0.12

V_IL

LOW-level input V_CC= 1.2 V

voltage

-

V_CC= 1.65 V to 1.95 V

0.35  V_CC

0.7

0.35  V_CC

0.7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.8

V_OH

HIGH-level

output voltage

I_O= 100 A;

V_CC 0.2 V_CC

-

V_CC 0.3

-

V

V_CC= 1.65 V to 3.6 V

I_O= 2 mA; V_CC= 1.65 V

I_O= 4 mA; V_CC= 2.3 V

I_O= 6 mA; V_CC= 2.7 V

I_O= 12 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

-

1.05

1.65

2.05

2.0

-

V

V_OL

LOW-level

output voltage

I_O= 100 A;

-

0.2

-

0.3

V

V_CC= 1.65 V to 3.6 V

I_O= 2 mA; V_CC= 1.65 V

I_O= 4 mA; V_CC= 2.3 V

I_O= 6 mA; V_CC= 2.7 V

I_O= 12 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

0.55

5

0.8

V

[2]

I_I

input leakage

current

V_CC= 3.6 V;

V_I= 5.5 V or GND

0.1

20

A

I_OZ

I_OFF

I_CC

I_CC

OFF-state

output current

V_I= V_IHor V_IL; V_CC= 3.6

V; V_O= 5.5 V or GND;

-

0.1

0.1

5

5

10

40

-

20

A

power-off

leakage supply

V_CC= 0 V; V_Ior V_O= 5.5 V

supply current

V_CC= 3.6 V;

V_I= V_CCor GND; I_O= 0 A

160

additional

supply current

per input pin;

500

5000

V_CC= 2.7 V to 3.6 V;

V_I= V_CC 0.6 V; I_O= 0 A

C_I

input

capacitance

V_CC= 0 V to 3.6 V;

V_I= GND to V_CC

-

5.0

-

pF

[3][4]

I_BHL

bus hold LOW

current

V_CC= 1.65 V; V_I= 0.58 V

V_CC= 2.3 V; V_I= 0.7 V

V_CC= 3.0 V; V_I= 0.8 V

10

30

75

-

10

25

60

-

A

74LVCH322244A

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Product data sheet

Rev. 3 — 16 December 2011

5 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

10

Max

[3][4]

[3][5]

I_BHH

bus hold HIGH V_CC= 1.65 V; V_I= 1.07 V

10

30

-

A

current

V_CC= 2.3 V; V_I= 1.7 V

25

V_CC= 3.0 V; V_I= 2.0 V

75

60

I_BHLO

bus hold LOW

overdrive

current

V

_CC= 1.95 V

200

V_CC= 2.7 V

V_CC= 3.6 V

300

500

I_BHHO

bus hold HIGH

overdrive

current

V

_CC= 1.95 V

200

300

500

200

300

500

V_CC= 2.7 V

V_CC= 3.6 V

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

[2] The bus hold circuit is switched off when V_I> V_CC, allowing 5.5 V on the input terminal.

[3] Valid for data inputs only. Note that control inputs do not have a bus hold circuit.

[4] The specified sustaining current at the data input holds the input below the specified V_Ilevel.

[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.

Symbol Parameter

Conditions

T_amb= 40 C to +85 C 40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

t_en

t_dis

propagation

delay

nAn to nYn; see Figure 4

V_CC= 1.2 V

-

11.0

6.0

3.2

3.3

2.7

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

15.0

7.4

6.7

5.8

1.5

1.0

17.2

8.2

8.5

7.5

V_CC= 3.0 V to 3.6 V

nOE to nYn; see Figure 5

V_CC= 1.2 V

enable time

-

15.0

6.8

3.8

4.2

3.1

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.7

1.5

1.0

15.3

8.0

7.6

6.0

1.7

1.5

1.0

17.7

8.9

9.5

7.5

V_CC= 3.0 V to 3.6 V

nOE to nYn; see Figure 5

V_CC= 1.2 V

disable time

-

10.0

3.9

2.1

3.1

2.8

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.2

0.5

1.5

8.2

4.4

4.7

4.5

2.2

0.5

1.5

9.5

5.0

6.0

V_CC= 3.0 V to 3.6 V

74LVCH322244A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 December 2011

6 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.

Symbol Parameter

Conditions

T_amb= 40 C to +85 C 40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[3]

[4]

t_sk(o)

C_PD

output skew

time

V_CC= 3.0 V to 3.6 V

-

1.0

-

1.5

ns

power

dissipation

capacitance

per flip-flop; V_I= GND to V_CC

outputs enabled

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

-

4.8

8.3

-

pF

11.4

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs

11. AC waveforms

V

I

nAn input

GND

V

M

t

PHL

PLH

V

OH

nYn output

V

M

V

OL

mna474

V_M= 1.5 V at V_CC 2.7 V or

V_M= 0.5  V_CCat V_CC< 2.7 V.

_OLand V_OHare typical output voltage levels that occur with the output load.

V

Fig 4. Input (nAn) to output (nYn) propagation delay times

74LVCH322244A

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Product data sheet

Rev. 3 — 16 December 2011

7 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

V

I

nOE input

V

M

GND

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

mna478

V_M= 1.5 V at V_CC 2.7 V;

V_M= 0.5  V_CCat V_CC< 2.7 V.

V_X= V_OL+ 0.3 V at V_CC 2.7 V or

_X= V_OL+ 0.1 V at V_CC< 2.7 V.

V

V_Y= V_OH 0.3 V at V_CC 2.7 V or

V_Y= V_OH 0.1 V at V_CC< 2.7 V.

V

_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 5. 3-state enable and disable times

74LVCH322244A

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Product data sheet

Rev. 3 — 16 December 2011

8 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 8.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 6. Load circuitry for switching times

Table 8.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVCH322244A

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Product data sheet

Rev. 3 — 16 December 2011

9 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

12. Package outline

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

1/2 e

y

∅ v M

∅ w M

C

A B

C

1

e

b

T

R

P

N

e

M

L

K

J

H

G

F

e

2

1/2 e

E

D

C

B

A

ball A1

index area

1

2

3

4

5

6

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

v

w

y

1

D

E

1

2

1

2

max.

0.41

0.31

1.2

0.9

0.51

0.41

5.6

5.4

13.6

13.4

mm

1.5

4

12

0.1

0.2

0.8

0.15

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

00-03-04

03-02-05

SOT536-1

Fig 7. Package outline SOT536-1 (LFBGA96)

74LVCH322244A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 December 2011

10 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

13. Abbreviations

Table 9.

Acronym

CDM

DUT

Abbreviations

Description

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Machine Model

HBM

MM

TTL

Transistor-Transistor Logic

14. Revision history

Table 10: Revision history

Document ID

Release date

20111216

Data sheet status

Change notice

Supersedes

74LVCH322244A v.3

Modifications:

Product data sheet

-

74LVCH322244A v.2

• The format of this document has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.

74LVCH322244A v.2

74LVCH322244A v.1

20040519

Product specification

-

74LVCH322244A v.1

19991124

Product specification

-

74LVCH322244A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 December 2011

11 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

74LVCH322244A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 December 2011

12 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVCH322244A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 December 2011

13 of 14

74LVCH322244A

NXP Semiconductors

32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 13

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 December 2011

Document identifier: 74LVCH322244A


型号：	74LVCH322244AEC/G
厂家：	NXP
描述：	IC LVC/LCX/Z SERIES, OCTAL 4-BIT DRIVER, TRUE OUTPUT, PBGA96, 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96, Bus Driver/Transceiver 驱动输出元件逻辑集成电路
文件：	总14页 (文件大小：105K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVCH322244AEC/G [NXP]

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