74LVT162374DGG,512_技术文档

74LVT162374

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop with 30 Ω

termination resistors; 3-state

Rev. 03 — 17 January 2005

Product data sheet

1. General description

The 74LVT162374 is a high performance BiCMOS product designed for V_CCoperation at

3.3 V.

The 74LVT162374 is designed with 30 Ω series resistance in both the HIGH and LOW

states of the output. This design reduces line noise in applications such as memory

address drivers, clock drivers, and bus receivers/transmitters.

This device is a 16-bit edge-triggered D-type ﬂip-ﬂop featuring non-inverting 3-state

outputs. The device can be used as two 8-bit ﬂip-ﬂops or one 16-bit ﬂip-ﬂop. On the

positive transition of the clock (CP), the Q outputs of the ﬂip-ﬂop take on the logic levels

set up at the D inputs.

2. Features

■ 16-bit edge-triggered ﬂip-ﬂop

■ 3-state buffers

■ Output capability: +12 mA and −12 mA

■ TTL input and output switching levels

■ Input and output interface capability to systems at 5 V supply

■ Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

■ Live insertion and extraction permitted

■ Outputs include series resistance of 30 Ω making external resistors unnecessary

■ Power-up reset

■ Power-up 3-state

■ No bus current loading when output is tied to 5 V bus

■ Latch-up protection exceeds 500 mA per JESD78

■ ESD protection:

◆ MIL STD 883 method 3015: exceeds 2000 V

◆ Machine model: exceeds 200 V

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

3. Quick reference data

Table 1:

Quick reference data

T_amb= 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max Unit

t_PLH, t_PHLpropagation delay

nCP to nQn

C_L= 50 pF; V_CC= 3.3 V

-

3.0

-

ns

C_I

input capacitance

output capacitance

V_I= 0 V or 3.0 V

-

3

9

-

pF

C_O

outputs disabled;

V_O= 0 V or 3.0 V

I_CC

supply current

outputs disabled;

-

70

-

µA

V_CC= 3.6 V

4. Ordering information

Table 2:

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVT162374DGG −40 °C to +85 °C

TSSOP48

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

SOT362-1

74LVT162374DL

−40 °C to +85 °C

SSOP48

plastic shrink small outline package; 48 leads;

body width 7.5 mm

SOT370-1

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

2 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

5. Functional diagram

47 46 44 43 41 40 38 37

1

1EN

C3

1OE

1CP

2OE

2CP

48

24

25

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

2EN

C4

48

1

1CP

1OE

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

2

3

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

3D

1

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

5

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

6

8

2

3

5

6

8

9

11 12

9

11

12

13

14

16

17

19

20

22

23

36 35 33 32 30 29 27 26

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7

4D

2

25

24

2CP

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

13 14 16 17 19 20 22 23

001aac369

001aaa254

Fig 1. Logic symbol

Fig 2. IEC logic symbol

nD0

D

nD1

nD2

nD3

nD4

nD5

nD6

D

nD7

D

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

nCP

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

001aac371

Fig 3. Logic diagram

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

3 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

V

CC

27 Ω

output

27 Ω

001aac372

Fig 4. Output schematic (one output)

6. Pinning information

6.1 Pinning

1CP

1D0

1

2

3

4

5

6

7

8

9

48

47

1OE

1Q0

1Q1

GND

1Q2

1Q3

46 1D1

45 GND

44 1D2

43 1D3

V

42

41

40

39

38

CC

1D4

1D5

GND

1D6

CC

1Q4

1Q5

GND 10

1Q6 11

1Q7 12

2Q0 13

2Q1 14

GND 15

2Q2 16

2Q3 17

37 1D7

36 2D0

35 2D1

34 GND

33 2D2

32 2D3

162374

V

18

31 V

CC

2Q4 19

2Q5 20

30

29

2D4

2D5

21

22

23

24

28 GND

27 2D6

26 2D7

GND

2Q6

2Q7

2OE

25

2CP

001aac370

Fig 5. Pin conﬁguration

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

4 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

6.2 Pin description

Table 3:

Symbol

1OE

1Q0

1Q1

GND

1Q2

1Q3

V_CC

Pin description

1

Description

output enable input (active LOW)

data output

2

3

data output

4

ground (0 V)

data output

5

6

data output

7

supply voltage

data output

1Q4

1Q5

GND

1Q6

1Q7

2Q0

2Q1

GND

2Q2

2Q3

V_CC

8

9

data output

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

ground (0 V)

data output

ground (0 V)

data output

supply voltage

data output

2Q4

2Q5

GND

2Q6

2Q7

2OE

2CP

2D7

2D6

GND

2D5

2D4

V_CC

data output

ground (0 V)

data output

output enable input (active LOW)

clock pulse input (active rising edge)

data input

ground (0 V)

data input

supply voltage

data input

2D3

2D2

GND

2D1

2D0

1D7

1D6

GND

data input

ground (0 V)

data input

ground (0 V)

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

5 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

Table 3:

Symbol

1D5

Pin description

40

41

42

43

44

45

46

47

48

Description

data input

1D4

data input

V_CC

supply voltage

data input

1D3

1D2

data input

GND

1D1

ground (0 V)

data input

1D0

data input

1CP

clock pulse input (active rising edge)

7. Functional description

7.1 Function table

Table 4:

Function table^[1]

Operating mode

Input

Internal register Output

nQ0 to nQ7

nOE

L

nCP

↑

nDn

Load and read

register

l

L

↑

h

H

Hold

L

NC

↑

X

NC

nDn

NC

Z

Disable outputs

H

X

H

nDn

Z

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;

NC = no change;

X = don’t care;

Z = high-impedance OFF-state;

↑ = LOW-to-HIGH clock transition.

8. Limiting values

Table 5:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

GND (ground = 0 V)

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

−50

−0.5

Max

+4.6

-

Unit

V

supply voltage

input diode current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+7.0

-

I_OK

output diode current V_O< 0 V

output voltage output in OFF-state or

HIGH-state

mA

V

V_O

+7.0

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

6 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

Table 5:

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

GND (ground = 0 V)

Symbol

Parameter

Conditions

Min

Max

128

Unit

mA

°C

I_O

output current

output in LOW-state

output in HIGH-state

-

−64

T_stg

T_j

storage temperature

junction temperature

−65

+150

150

[2]

°C

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings

are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal

9. Recommended operating conditions

Table 6:

Recommended operating conditions

Conditions

Symbol Parameter

Min

2.7

0

Typ

Max

3.6

5.5

-

Unit

V

V_CC

V_I

supply voltage

-

input diode voltage

HIGH-level input voltage

LOW-level input voltage

V

V_IH

V_IL

I_OH

2.0

-

V

0.8

−12

V

HIGH-level output

current

-

mA

I_OL

LOW-level output current

-

12

10

mA

∆t/∆V

input transition rise or fall outputs enabled

rate

ns/V

T_amb

ambient temperature

−40

-

+85

°C

10. Static characteristics

Table 7:

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +85 °C^[1]

V_IK

input clamp voltage

V_CC= 2.7 V; I_IK= −18 mA

V_CC= 3.0 V; I_OH= −12 mA

V_CC= 3.0 V; I_OL= 12 mA

-

−0.85

−1.2

-

V

V_OH

V_OL

V_RST

HIGH-level output voltage

LOW-level output voltage

2.0

-

0.8

0.55

[2]

power-up output low voltage V_CC= 3.6 V; I_O= 1 mA;

V_I= GND or V_CC

0.1

I_LI

input leakage current

control pins

V_CC= 3.6 V; V_I= V_CCor GND

V_CC= 0 V or 3.6 V; V_I= 5.5 V

V_CC= 3.6 V; V_I= V_CC

-

0.1

0.4

0.1

−0.4

0.1

±1

µA

10

1

I/O data pins

V_CC= 3.6 V; V_I= 0 V

−5

I_OFF

output off current

V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

±100

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

7 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

Table 7:

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

75

Typ

135

−135

-

Max

Unit

µA

[4]

I_HOLD

bus hold current D inputs

V_CC= 3 V; V_I= 0.8 V

V_CC= 3 V; V_I= 2.0 V

V_CC= 0 V to 3.6 V; V_I= 3.6 V

-

−75

±500

-

µA

-

µA

I_EX

external current into output output in HIGH-state when

V_O> V_CC; measured at V_O= 5.5 V

and V_CC= 3.0 V

50

125

µA

[5]

I_PU, I_PD

power-up or power-down

3-state output current

V

_CC≤ 1.2 V; V_O= 5.0 V to V_CC

;

-

1

±100

µA

V_I= GND or V_CC; nOE and

nOE = don’t care

I_OZH

I_OZL

I_CC

3-state output HIGH current V_CC= 3.6 V; V_O= 3.0 V;

V_I= V_IHor V_IL

-

0.5

5

µA

3-state output LOW current V_CC= 3.6 V; V_O= 0.5 V;

V_I= V_IHor V_IL

+0.5

−5

quiescent supply current

V_CC= 3.6 V; V_I= GND or V_CC

I_O= 0 A

;

outputs HIGH

outputs LOW

outputs disabled

-

0.07

4

0.12

6

mA

[6]

[7]

0.07

0.1

0.12

0.2

∆I_CC

additional supply current per V_CC= 3 V to 3.6 V; one input at

input pin

V_CC− 0.6 V; other inputs at

V_CCor GND

C_I

input capacitance

output capacitance

V_I= 0 V or 3.0 V

-

3

9

-

pF

C_O

outputs disabled; V_O= 0 V or 3.0 V

[1] All typical values are at V_CC= 3.3 V and T_amb= 25 °C.

[2] For valid test results, data must not be loaded into the ﬂip-ﬂops (or latches) after applying power.

[3] Unused pins at V_CCor GND.

[4] This is the bus-hold overdrive current required to force the input to the opposite logic state.

[5] This parameter is valid for any V_CCbetween 0 V and 1.2 V with a transition time of up to 10 ms. From V_CC= 1.2 V to V_CC= 3.3 V ± 0.3 V

a transition time of 100 µs is permitted. This parameter is valid for T_amb= 25 °C only.

[6] I_CCis measured with outputs pulled to V_CCor GND.

[7] This is the increase in supply current for each input at the speciﬁed voltage level other than V_CCor GND.

Table 8:

Dynamic characteristics

GND = 0 V; t_r= t_f= 2.5 ns; C_L= 50 pF; R_L= 500 Ω; for test circuit see Figure 10.

Symbol

T_amb= −40 °C to +85 °C^[1]

f_maxmaximum clock frequency

t_PLH

Parameter

Conditions

Min

Typ

Max

Unit

V_CC= 3.3 V ± 0.3 V; see Figure 6

see Figure 6

150

-

MHz

propagation delay

nCP to nQn

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

-

3.0

-

5.3

6.2

ns

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

8 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

Table 8:

Dynamic characteristics …continued

GND = 0 V; t_r= t_f= 2.5 ns; C_L= 50 pF; R_L= 500 Ω; for test circuit see Figure 10.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_PHL

propagation delay

nCP to nQn

see Figure 6

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

-

3.0

-

4.9

5.1

ns

t_PZH

t_PZL

t_PHZ

t_PLZ

output enable time to

HIGH-level

see Figure 7

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

-

3.5

-

5.6

6.9

ns

output enable time to

LOW-level

see Figure 8

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

-

3.2

-

4.9

6.0

ns

output disable time from

HIGH-level

see Figure 7

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

-

3.5

-

5.4

5.7

ns

output disable time from

LOW-level

see Figure 8

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

-

3.2

-

5.0

5.1

ns

[1] All typical values are at V_CC= 3.3 V and T_amb= 25 °C.

Table 9:

Dynamic characteristics set-up requirements

GND = 0 V; t_r= t_f= 2.5 ns; C_L= 50 pF; R_L= 500 Ω.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +85 °C^[1]

t_su(H), t_su(L)set-up time nDn to nCP

see Figure 9

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

2.0

0.7

-

ns

t_h(H), t_h(L)

hold time nDn to nCP

nCP pulse width HIGH

nCP pulse width LOW

see Figure 9

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

0.8

0.1

0

-

ns

t_W(H)

see Figure 6

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

0.6

-

ns

t_W(L)

see Figure 6

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

3.0

1.6

-

ns

[1] All typical values are at V_CC= 3.3 V and T_amb= 25 °C.

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

9 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

12. Waveforms

1/f

max

2.7 V

nCP

nQn

V

M

0 V

t

W(L)

W(H)

t

PLH

t

PHL

V

OH

V

M

V

OL

001aac373

V_M= 1.5 V; V_I= GND to 3.0 V.

V_OLand V_OHare typical voltage output drop that occur with the output load.

Fig 6. Propagation delay clock input to output, clock pulse width and maximum clock

frequency

2.7 V

V

t

V

M

nOE

nQn

M

t

PZH

PHZ

V

OH

− 0.3 V

OH

V

M

0 V

001aac374

V_M= 1.5 V; V_I= GND to 3.0 V.

V_OHis typical voltage output drop that occur with the output load.

Fig 7. 3-state output enable time to HIGH-level and output disable time from HIGH-level

2.7 V

V

M

nOE

M

t

PLZ

PZL

3.0 V

V

M

V

+ 0.3 V

nQn

OL

V

OL

001aac375

V_M= 1.5 V; V_I= GND to 3.0 V.

V_OLis typical voltage output drop that occur with the output load.

Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

10 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

2.7 V

nDn

nCP

V

t

V

t

V

M

0 V

t

su(H)

h(H)

su(L)

h(L)

2.7 V

V

M

0 V

001aac376

V_M= 1.5 V; V_I= GND to 3.0 V.

Remark: The shaded areas indicate when the input is permitted to change for predictable

output performance.

Fig 9. Data set-up and hold times

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

(t )

f

t

(t )

TLH r

THL

t

(t )

t

(t )

THL f

TLH

r

V

I

90 %

positive

pulse

V

M

V

M

10 %

0 V

t

W

001aac221

V_M= 1.5 V.

a. Input pulse deﬁnition

V

EXT

V

CC

R

L

V

I

V

O

PULSE

GENERATOR

D.U.T.

C

L

R

L

R

T

mna616

Test data is given in Table 10.

Deﬁnitions:

R_L= Load resistor.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= Test voltage for switching times.

b. Test circuit

Fig 10. Load circuitry for switching times

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

11 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

Table 10: Test data

Supply

voltage

Repetition rate Input

t_W

Load

C_L

V_EXT

t_r, t_f

R_L

t_PHZ, t_PZHt_PLZ, t_PZLt_PLH, t_PHL

2.7 V

≤ 10 MHz

500 ns ≤ 2.5 ns 50 pF 500 Ω GND

6 V

open

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

12 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

13. Package outline

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

E

D

A

X

c

H

v

M

A

y

E

Z

48

25

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

24

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

12.6

12.4

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.8

0.4

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT362-1

MO-153

Fig 11. Package outline SOT362-1 (TSSOP48)

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

13 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

SOT370-1

D

E

A

X

c

y

H

v

M

A

E

Z

25

48

Q

A

2

A

(A )

3

1

θ

pin 1 index

L

p

L

24

1

detail X

w

M

b

p

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

Q

v

w

y

Z

θ

p

1

2

3

max.

8^o

0^o

0.4

0.2

2.35

2.20

0.3

0.2

0.22 16.00

0.13 15.75

7.6

7.4

10.4

10.1

1.0

0.6

1.2

1.0

0.85

0.40

mm

2.8

0.25

0.635

1.4

0.25

0.18

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT370-1

MO-118

Fig 12. Package outline SOT370-1 (SSOP48)

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

14 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

14. Revision history

Table 11: Revision history

Document ID

74LVT162374_3

Modiﬁcations:

Release date Data sheet status

20050117 Product data sheet

Change notice Doc. number

Supersedes

-

9397 750 14401 74LVT162374_2

• The format of this data sheet is redesigned to comply with the current presentation and

information standard of Philips Semiconductors.

• Section 2 “Features”: Changed JEDEC Std 17 into JESD78

• Table 1 “Quick reference data”:Changed t_PLHand t_PHLpropagation delays nCP to nQn to 3.0 ns

• Table 9 “Dynamic characteristics set-up requirements”: Changed the minimum values of t_h(H)

and t_h(L)hold time nDn to nCP to 0.8 ns

74LVT162374_2

74LVT162374_1

20040922

19990923

Product speciﬁcation

-

9397 750 14087 74LVT162374_1

9397 750 06508

-

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

15 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

15. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Deﬁnitions

17. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14401

Product data sheet

Rev. 03 — 17 January 2005

16 of 17

74LVT162374

Philips Semiconductors

3.3 V 16-bit edge-triggered D-type ﬂip-ﬂop

19. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 6

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended operating conditions. . . . . . . . 7

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Contact information . . . . . . . . . . . . . . . . . . . . 16

9

10

11

12

13

14

15

16

17

18

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 17 January 2005

Document number: 9397 750 14401

Published in The Netherlands


型号：	74LVT162374DGG,512
厂家：	NXP
描述：	74LVT162374 - 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ohm termination resistors; 3-state TSSOP 48-Pin
文件：	总17页 (文件大小：80K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVT162374DGG,512 [NXP]

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