74LVT16373 [NXP]
3.3V LVT 16-bit transparent D-type latch 3-State; 3.3V LVT 16位透明D型锁存三态
| 型号： | 74LVT16373 |
| 厂家： | 
NXP |
| 描述： | 3.3V LVT 16-bit transparent D-type latch 3-State |
| 文件： | 总10页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVT16373A
3.3V LVT 16-bit transparent D-type latch
(3-State)
Product specification
1998 Feb 19
Supersedes data of 1994 Dec 15
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
FEATURES
• 16-bit transparent latch
• 3-State buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product
designed for V operation at 3.3V.
CC
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When enable (E) input is High, the
Q outputs follow the data (D) inputs. When enable is taken Low, the
Q outputs are latched at the levels of the D inputs one setup time
prior to the High-to-Low transition.
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
= 25°C
t
t
Propagation delay
nDx to nQx
C = 50pF;
L
PLH
PHL
1.9
ns
V
CC
= 3.3V
C
Input capacitance
Output capacitance
Total supply current
V = 0V or 3.0V
3
9
pF
pF
µA
IN
I
C
Outputs disabled; V = 0V or 3.0V
O
OUT
CCZ
I
Outputs disabled; V = 3.6V
70
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT370-1
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
74LVT16373A DL
VT16373A DL
74LVT16373A DGG
VT16373A DGG
SOT362-1
LOGIC SYMBOL
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
47 46 44 43 41 40 38 37
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
1D0 – 1D7
2D0 – 2D7
Data inputs
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
1LE
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
1Q0 – 1Q7
2Q0 – 2Q7
Data outputs
48
1
1OE
Output enable
inputs
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1, 24
1OE, 2OE
(active-Low)
Enable inputs
(active-High)
2
3
5
6
8
9
11 12
48, 25
1E, 2E
GND
36 35 33 32 30 29 27 26
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
Ground (0V)
Positive
supply voltage
V
CC
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13 14 16 17 19 20 22 23
SA00044
2
1998 Feb 19
853-1780 18989
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
LOGIC SYMBOL (IEEE/IEC)
PIN CONFIGURATION
1
1EN
C3
1
2
48
47
1OE
1Q0
1Q1
GND
1Q2
1Q3
1LE
1D0
1OE
1LE
2OE
2LE
48
24
25
2EN
C4
3
46 1D1
GND
1D2
4
45
44
5
47
46
44
43
41
40
38
37
36
2
3
3D
1
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
6
43 1D3
7
42
41
40
39
38
37
36
35
34
33
32
31
30
V
V
CC
5
CC
8
1Q4
1Q5
1D4
1D5
6
9
8
GND
GND
10
11
12
13
14
15
16
17
18
19
9
1Q6
1Q7
2Q0
2Q1
GND
1D6
1D7
2D0
2D1
GND
11
12
13
4D
2
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q2
2Q3
2D2
2D3
V
V
CC
CC
2Q4
2D4
2Q5 20
29 2D5
21
22
23
24
28
27
26
25
GND
2Q6
GND
2D6
SW00010
2Q7
2OE
2D7
2LE
SA00043
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
E
D
D
E
D
E
D
E
D
D
D
E
Q
E
Q
Q
Q
Q
E
Q
E
Q
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00046
3
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
FUNCTION TABLE
INPUTS
OUTPUTS
nQ0 – nQ7
INTERNAL
REGISTER
OPERATING MODE
nOE
nE
nDx
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
↓
↓
l
h
L
H
L
H
Latch and read register
Hold
L
L
X
NC
NC
H
H
L
H
X
nDx
NC
nDx
Z
Z
Disable outputs
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low E transition
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
V
DC supply voltage
–0.5 to +4.6
–50
CC
IK
I
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–0.5 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +7.0
128
I
DC output current
mA
OUT
Output in High state
–64
T
stg
Storage temperature range
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
2.7
0
MAX
3.6
V
CC
DC supply voltage
Input voltage
V
V
V
I
5.5
V
High-level input voltage
Input voltage
2.0
V
IH
V
0.8
–32
32
V
IL
I
High-level output current
Low-level output current
mA
mA
OH
I
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
64
∆t/∆v
10
ns/V
T
amb
–40
+85
°C
4
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
V
1
MIN
TYP
–.85
MAX
V
IK
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7V; I = –18mA
–1.2
IK
= 2.7 to 3.6V; I = –100µA
V
CC
-0.2
V
CC
OH
V
High-level output voltage
= 2.7V; I = –8mA
2.4
2.5
2.3
V
OH
OH
= 3.0V; I = –32mA
2.0
OH
= 2.7V; I = 100µA
0.07
0.3
0.2
0.5
0.4
0.5
0.55
0.55
±1
OL
= 2.7V; I = 24mA
OL
V
Low–level output voltage
= 3.0V; I = 16mA
0.25
0.3
V
OL
OL
= 3.0V; I = 32mA
OL
= 3.0V; I = 64mA
0.4
OL
5
V
RST
Power-up output Low voltage
Input leakage current
Output off current
= 3.6V; I = 1mA; V = GND or V
CC
0.1
V
O
I
= 3.6V; V = V or GND
Control pins
0.1
I
CC
= 0 or 3.6V; V = 5.5V
0.4
10
I
I
I
µA
= 3.6V; V = V
0.1
1
I
CC
4
Data pins
= 3.6V; V = 0
-0.4
0.1
-5
I
I
= 0V; V or V = 0 to 4.5V
±100
µA
µA
OFF
I
O
= 3V; V = 0.8V
75
135
-135
I
7
= 3V; V = 2.0V
–75
I
Bus Hold current D inputs
I
HOLD
= 0V to 3.6V; V = 3.6V
±500
CC
Current into an output in the
I
V
= 5.5V; V = 3.0V
50
1
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
O
CC
I
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
= 3.6V; V = 3.0V; V = V or V
0.5
0.5
5
–5
OZH
CC
CC
CC
CC
CC
CC
O
I
IH
IL
IL
µA
I
= 3.6V; V = 0.5V; V = V or V
O I IH
OZL
I
I
= 3.6V; Outputs High, V = GND or V I 0
CC, O =
0.07
4.0
0.12
6
CCH
I
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
I
6
= 3.6V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.07
0.12
CCZ
I
Additional supply current per
= 3V to 3.6V; One input at V -0.6V,
CC
∆I
0.1
0.2
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND.
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 3.3V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I is measured with outputs pulled to V or GND.
CCZ
CC
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
5
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T = –40°C to +85°C.
amb
R
F
L
L
LIMITS
= 3.3V ±0.3V
SYMBOL
PARAMETER
WAVEFORM
V
CC
V
CC
= 2.7V
UNIT
1
MIN
TYP
MAX
MAX
t
t
Propagation delay
nDx to nQx
0.5
0.5
1.8
1.9
3.9
3.9
4.5
4.5
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
nE to nQx
0.5
0.5
2.1
2.2
4.8
4.8
5.4
5.4
PLH
PHL
t
Output enable time
to High and Low level
4
5
0.1
0.1
2.8
2.6
4.5
4.3
5.1
4.7
PZH
t
PZL
t
Output disable time
from High and Low Level
4
5
0.1
0.1
3.3
3.0
4.5
4.3
5.1
4.7
PHZ
t
PLZ
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC SETUP REQUIREMENTS
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
= 3.3V ±0.3V
SYMBOL
t (H)
PARAMETER
WAVEFORM
V
V
CC
= 2.7V
UNIT
CC
MIN
TYP
MIN
Setup time
nDx to nE
1.5
2.0
0.1
0.2
1.0
2.0
S
3
3
1
ns
ns
ns
t (L)
S
t (H)
Hold time
nDx to nE
1.0
1.5
0
0
1.0
2.0
h
t (L)
h
nE pulse width
High
t (H)
W
1.5
0.5
1.5
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
2.7V
2.7V
0V
V
V
V
V
M
nDx
nE
M
M
M
nE
V
V
V
t
0V
M
M
M
t
(H)
t (L)
s
t
(H)
t
(L)
s
h
h
t
(H)
w
2.7V
t
PHL
PLH
V
V
OH
V
V
M
M
nQx
0V
V
V
M
M
NOTE: The shaded areas indicate when the input is per-
mitted to change for predictable output performance.
OL
SW00011
SW00013
Waveform 1. Propagation Delay, Enable to
Output, and Enable Pulse Width
Waveform 3. Data Setup and Hold Times
2.7V
0V
2.7V
0V
V
V
M
nOE
nQx
M
t
V
V
M
M
t
nDx
nQx
t
PZH
PHZ
t
PLH
PHL
V
OH
V
V
OH
OL
V
-0.3V
OH
V
M
V
V
M
M
0V
SW00014
SW00012
Waveform 4. 3-State Output Enable time to High Level
and Output Disable Time from High Level
Waveform 2. Propagation Delay for Data to Outputs
6
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
2.7V
nOE
V
V
M
M
t
0V
3V
t
PZL
PLZ
V
M
nQx
V
+0.3V
OL
V
OL
SW00015
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORMS
6V
V
t
W
CC
AMP (V)
90%
90%
OPEN
GND
NEGATIVE
PULSE
V
V
M
10%
M
10%
V
V
OUT
IN
R
R
L
L
0V
(t
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
)
THL
F
TLH
R
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
Input Pulse Definition
t
/t
GND
6V
PHZ PZH
t
/t
PLZ PZL
t
/t
open
PLH PHL
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
2.7V
Rep. Rate
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74LVT16
≤10MHz
500ns ≤2.5ns ≤2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SW00003
7
1998 Feb 19
Philips Semiconductors Low Voltage Products
Product specification
3.3V LVT 16-bit transparent D-type latch
(3-State)
74LVT16373A
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
8
1998 Feb 19
Philips Semiconductors Low Voltage Products
Product specification
3.3V LVT 16-bit transparent D-type latch
(3-State)
74LVT16373A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
9
1998 Feb 19
Philips Semiconductors
Product specification
3.3V LVT 16-bit transparent D-type latch
(3-State)
74LVT16373A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03554
Document order number:
Philips
Semiconductors
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