74LVT16374ADGG,118_技术文档

INTEGRATED CIRCUITS

74LVT16374A

3.3V LVT 16-bit edge-triggered D-type

flip-flop (3-State)

Product data sheet

2004 Sep 16

Supersedes data of 2002 Nov 01

Philips

Semiconductors

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

FEATURES

• 16-bit edge-triggered flip-flop

• 3-State buffers

• Output capability: +64 mA/–32 mA

• TTL input and output switching levels

• Input and output interface capability to systems at 5 V supply

DESCRIPTION

The 74LVT16374A is a high-performance BiCMOS product

designed for V operation at 3.3 V.

CC

This device is a 16-bit edge-triggered D-type flip-flop featuring

non-inverting 3-State outputs. The device can be used as two 8-bit

flip-flops or one 16-bit flip-flop. On the positive transition of the clock

(CP), the Q outputs of the flip-flop take on the logic levels set up at

the D inputs.

• Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

• Live insertion/extraction permitted

• Power-up reset

• Power-up 3-State

• No bus current loading when output is tied to 5 V bus

• Latch-up protection exceeds 500 mA per JEDEC Std 17

• ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

QUICK REFERENCE DATA

CONDITIONS

SYMBOL

PARAMETER

TYPICAL

UNIT

T

amb

= 25 °C

t

Propagation delay

nCP to nQx

C = 50 pF;

L

PLH

PHL

2.9

ns

V

CC

= 3.3 V

C

Input capacitance

Output pin capacitance

Total supply current

V = 0 V or 3.0 V

3

9

pF

µA

IN

I

C

Outputs disabled; V = 0 V or 3.0 V

O

OUT

CCZ

I

Outputs disabled; V = 3.6 V

70

CC

ORDERING INFORMATION

Package

Type number

Name

Description

plastic shrink small outline package; 48 leads; body width 7.5 mm

Temperature Version

Range (°C)

74LVT16374ADL

74LVT16374ADGG

74LVT16374AEV

SSOP48

–40 to +85

SOT370-1

SOT362-1

SOT702-1

TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm

VFBGA56 plastic very thin fine-pitch ball grid array package; 56 balls;

body 4.5 × 7 × 0.65 mm

2

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

LOGIC SYMBOL (SSOP AND TSSOP PACKAGES)

PIN CONFIGURATION (SSOP AND TSSOP

PACKAGE OPTIONS)

47 46 44 43 41 40 38 37

1OE

1Q0

!Q1

1

2

3

4

5

6

7

8

9

48 1CP

47 1D0

46 1D1

45 GND

44 1D2

43 1D3

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

48

1

1CP

1OE

GND

1Q2

1Q3

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

V

42

V

CC

2

3

5

6

8

9

11 12

1Q4

1Q5

41 1D4

40 1D5

39 GND

38 1D6

37 1D7

36 2D0

35 2D1

34 GND

33 2D2

32 2D3

36 35 33 32 30 29 27 26

GND 10

1Q6 11

1Q7 12

2Q0 13

2Q1 14

GND 15

2Q2 16

2Q3 17

2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7

25

24

2CP

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

13 14 16 17 19 20 22 23

SW00018

V

18

31

V

CC

2Q4 19

2Q5 20

GND 21

2Q6 22

2Q7 23

2OE 24

30 2D4

29 2D5

28 GND

27 2D6

26 2D7

25 2CP

LOGIC SYMBOL (IEEE/IEC)

1

1OE

1CP

2OE

2CP

1EN

C1

2EN

C2

48

24

25

SW00017

47

46

2

3

5

1D

1

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

44

43

41

6

8

9

40

38

11

12

37

36

35

13

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2D

2

14

16

2D1

2D2

2D3

2D4

2D5

2D6

2D7

33

32

17

19

30

29

20

22

23

27

26

SW00016

3

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

PIN DESCRIPTION (SSOP AND TSSOP PACKAGE

OPTIONS)

EV PACKAGE TERMINAL PLACEMENT, TOP VIEW

1

2

3

4

5

6

PIN NUMBER

SYMBOL

FUNCTION

A

B

C

D

E

F

47, 46, 44, 43, 41, 40,

38, 37 36, 35, 33, 32,

30, 29, 27, 26

1D0 to 1D7

2D0 to 2D7

Data inputs

2, 3, 5, 6, 8, 9, 11, 12

13, 14, 16, 17, 19, 20,

22, 23

1Q0 to 1Q7

2Q0 to 2Q7

Data outputs

Output enable inputs

(active-LOW)

1, 24

1OE, 2OE

1CP, 2CP

GND

Clock pulse inputs (active

rising edge)

48, 25

G

H

J

4, 10, 15, 21, 28, 34,

39, 45

Ground (0 V)

7, 18, 31, 42

V

CC

Positive supply voltage

K

SR0243

TERMINAL ASSIGNMENTS FOR 74LVT16374A IN VFBGA

1

2

3

4

5

6

A

B

C

D

E

F

1OE

1Q1

1Q3

1Q5

1Q7

2Q0

2Q2

2Q4

2Q6

2OE

NC

1CP

1D1

1D3

1D5

1D7

2D0

2D2

2D4

2D6

2CP

1Q0

1Q2

1Q4

1Q6

2Q1

2Q3

2Q5

2Q7

NC

GND

Vcc

GND

Vcc

GND

1D0

1D2

1D4

1D6

2D1

2D3

2D5

2D7

NC

G

H

J

GND

Vcc

GND

Vcc

GND

NC

GND

NC

K

FUNCTION TABLE

INPUTS

nCP

INTERNAL

REGISTER

OUTPUTS

OPERATING MODE

nOE

nDx

nQ0 to nQ7

L

↑

l

h

L

H

L

H

Load and read register

Hold

L

↑

X

NC

H

↑

X

nDx

NC

nDx

Z

Disable outputs

H

h

L

l

=

HIGH voltage level

HIGH voltage level one set-up time prior to the HIGH-to-LOW E transition

LOW voltage level

LOW voltage level one set-up time prior to the HIGH-to-LOW E transition

NC= No change

X

Z

↑

=

Don’t care

High-impedance “off” state

LOW-to-HIGH clock transition

Not a LOW-to-HIGH clock transition

↑

4

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

LOGIC DIAGRAM

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

D

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP Q

nCP

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

SW00019

1, 2

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

CONDITIONS

RATING

UNIT

V

CC

I

IK

DC supply voltage

–0.5 to +4.6

–50

DC input diode current

V < 0 V

I

mA

V

3

V

I

DC input voltage

–0.5 to +7.0

–50

I

DC output diode current

V

O

< 0 V

mA

V

OK

3

V

OUT

DC output voltage

Output in Off or HIGH state

Output in LOW state

–0.5 to +7.0

128

I

DC output current

mA

OUT

Output in HIGH state

–64

T

stg

Storage temperature range

–65 to +150

°C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

UNIT

MIN

2.7

0

MAX

3.6

V

CC

DC supply voltage

Input voltage

V

I

5.5

V

HIGH-level input voltage

Input voltage

2.0

V

IH

V

0.8

–32

32

V

IL

I

HIGH-level output current

LOW-level output current

mA

OH

I

OL

mA

LOW-level output current; current duty cycle ≤ 50 %; f ≥ 1 kHz

Input transition rise or fall rate; Outputs enabled

Operating free-air temperature range

64

∆t/∆v

10

ns/V

T

amb

–40

+85

°C

5

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

Input clamp voltage

TEST CONDITIONS

Temp = –40 °C to +85 °C UNIT

1

MIN

TYP

MAX

V

IK

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.7 V; I = –18 mA

–0.85

–1.2

V

IK

= 2.7 to 3.6 V; I = –100 µA

V

CC

–0.2

V

CC

OH

V

OH

HIGH-level output voltage

= 2.7 V; I = –8 mA

2.4

2.0

2.5

2.3

OH

= 3.0 V; I = –32 mA

OH

= 2.7 V; I = 100 µΑ

0.07

0.3

0.2

0.5

0.4

0.5

0.55

±1

OL

= 2.7 V; I = 24 mA

OL

V

OL

LOW-level output voltage

= 3.0 V; I = 16 mA

0.25

0.3

V

OL

= 3.0 V; I = 32 mA

OL

= 3.0 V; I = 64 mA

0.4

OL

5

V

RST

Power-up output LOW voltage

Input leakage current

Output off current

= 3.6 V; I = 1 mA; V = GND or V

CC

0.1

V

O

I

= 3.6 V; V = V or GND

Control pins

0.1

I

CC

= 0 V or 3.6 V; V = 5.5 V

0.4

10

I

µA

= 3.6 V; V = V

0.1

1

I

CC

4

Data pins

= 3.6 V; V = 0 V

–0.4

0.1

–5

I

= 0 V; V or V = 0 V to 4.5 V

±100

µA

OFF

I

O

= 3 V; V = 0.8 V

75

135

–135

I

7

I

Bus Hold current D inputs

= 3 V; V = 2.0 V

–75

HOLD

I

= 0 V to 3.6 V; V = 3.6 V

±500

CC

Current into an output in the

I

V

= 5.5 V; V = 3.0 V

50

1

125

µA

EX

O

CC

HIGH state when V > V

O

CC

Power up/down 3-State output

≤ 1.2 V; V = 0.5 V to V ; V = GND or V

CC

;

CC

O

CC

I

±100

PU/PD

3

current

OE/OE = Don’t care

I

3-State output HIGH current

3-State output LOW current

V

= 3.6 V; V = 3.0 V; V = V or V

0.5

0.07

4

5

–5

0.12

6

OZH

CC

O

I

IH

IL

µA

I

= 3.6 V; V = 0.5 V; V = V or V

O I IH

OZL

I

= 3.6 V; Outputs HIGH, V = GND or V I

= 0 mA

;

CCH

I

CC, O

I

Quiescent supply current

= 3.6 V; Outputs LOW, V = GND or V I

CC, O

mA

CCL

I

= 3.6 V; Outputs Disabled; V = GND or V

I

CC

I

0.07

0.1

0.12

0.2

CCZ

6

I

O

= 0 mA

Additional supply current per

V

= 3 V to 3.6 V; One input at V – 0.6 V,

CC CC

∆I

mA

CC

2

input pin

Other inputs at V or GND

CC

NOTES:

1. All typical values are at V = 3.3 V and T

= 25 °C.

amb

CC

2. This is the increase in supply current for each input at the specified voltage level other than V or GND

CC

3. This parameter is valid for any V between 0 V and 1.2 V with a transition time of up to 10msec. From V = 1.2 V to V = 3.3 V ± 0.3 V a

CC

transition time of 100 µsec is permitted. This parameter is valid for T

= 25 °C only.

amb

4. Unused pins at V or GND.

CC

5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

6. I is measured with outputs pulled to V or GND.

CCZ

CC

7. This is the bus hold overdrive current required to force the input to the opposite logic state.

6

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

AC CHARACTERISTICS

GND = 0 V; t = t = 2.5 ns; C = 50 pF; R = 500 Ω; T

= –40 °C to +85 °C.

R

F

L

amb

LIMITS

SYMBOL

PARAMETER

WAVEFORM

V

CC

= 3.3 V ± 0.3 V

V

CC

= 2.7 V

UNIT

1

MIN

TYP

MAX

f

Maximum clock frequency

1

150

MHz

ns

max

t

Propagation delay

nCP to nQx

1.5

2.9

3.0

5.0

5.6

PLH

PHL

t

Output enable time

to HIGH and LOW level

3

4

1.5

3.2

3.0

4.8

4.6

6.0

5.2

PZH

PZL

ns

t

Output disable time

from HIGH and LOW Level

3

4

1.5

3.9

3.4

5.4

4.6

6.0

5.0

PHZ

t

PLZ

NOTE:

1. All typical values are at V = 3.3 V and T

= 25 °C.

CC

amb

AC SETUP REQUIREMENTS

GND = 0 V; t = t = 2.5 ns; C = 50 pF; R = 500 Ω; T

= –40 °C to +85 °C.

R

F

L

amb

LIMITS

= 3.3 V ± 0.3 V

SYMBOL

t (H)

PARAMETER

WAVEFORM

V

CC

= 2.7 V

UNIT

CC

MIN

TYP

MIN

Setup time

nDx to nCP

2.0

0.7

2.0

S

2

1

ns

t (L)

S

t (H)

Hold time

nDx to nCP

0.8

0

0.1

h

t (L)

h

t (H)

nCP pulse width

HIGH or LOW

1.5

3.0

0.6

1.6

1.5

3.0

W

tw(L)

AC WAVEFORMS

V

M

= 1.5 V, V = GND to 3.0 V

IN

1/f

MAX

2.7 V

0 V

2.7 V

0 V

V

M

V

M

t

nOE

nQx

nCP

nQx

M

t

(H)

PZH

PHZ

t

W

(L)

w

t

PLH

PHL

V

OH

V

OH

OL

V

– 0.3 V

0 V

V

OH

M

V

M

SW00020

SW00014

Waveform 1. Propagation delay, clock input to output,

clock pulse width, and maximum clock frequency

Waveform 3. 3-State Output Enable time to HIGH level and

Output Disable time from HIGH level

2.7 V

V

M

nDx

nOE

nQx

V

M

0 V

M

t (H)

t (L)

s

t

(H)

t (L)

h

0 V

s

h

t

PLZ

PZL

2.7 V

3 V

nCP

V

M

V

M

V

+0.3 V

OL

0 V

V

OL

NOTE: The shaded areas indicate when the input is

permitted to change for predictable output performance.

SW00021

SW00015

Waveform 2. Data setup and hold times

Waveform 4. 3-State Output Enable time to LOW level and

Output Disable time from LOW level

7

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

TEST CIRCUIT AND WAVEFORMS

6 V

V

t

W

CC

AMP (V)

90%

OPEN

NEGATIVE

PULSE

V

M

10%

M

10%

GND

R

L

V

OUT

0 V

(t

IN

PULSE

GENERATOR

D.U.T.

t

(t

)

t

)

THL

F

TLH

R

)

(t )

F

R

C

TLH

R

THL

T

L

AMP (V)

90%

M

90%

POSITIVE

PULSE

V

M

Test Circuit for 3-State Outputs

10%

t

W

0 V

SWITCH POSITION

V

= 1.5 V

M

TEST

SWITCH

Input Pulse Definition

t

/t

GND

6 V

PHZ PZH

t

/t

PLZ PZL

t

/t

open

PLH PHL

INPUT PULSE REQUIREMENTS

DEFINITIONS

R = Load resistor; see AC CHARACTERISTICS for value.

L

FAMILY

Amplitude

2.7 V

Rep. Rate

t

F

W

R

C = Load capacitance includes jig and probe capacitance;

L

see AC CHARACTERISTICS for value.

74LVT16

≤10 MHz

500 ns ≤2.5 ns ≤2.5 ns

R = Termination resistance should be equal to Z

T

of

OUT

pulse generators.

SW00003

8

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

SOT370-1

9

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

10

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls;

body 4.5 x 7 x 0.65 mm

SOT702-1

11

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

REVISION HISTORY

Rev

Date

Description

_5

20040916

Product data sheet (9397 750 14077). Supersedes data of 2002 Nov 01 (9397 750 10649).

Modifications:

• AC Setup Requirements table on page 7:

– V = 3.3 V ± 0.3 V

CC

change t (H) and t (L) setup time nDx to nCP Min. from 2.5 ns to 2.0 ns

s

change t (H) and t (L) hold time nDx to nCP Min. from 0.5 ns to 0.8 ns

h

– V = 2.7 V

CC

change t (H) and t (L) setup time nDx to nCP Min. from 2.5 ns to 2.0 ns

s

change t (H) and t (L) hold time nDx to nCP Min. from 0 ns to 0.1 ns

h

_4

20021101

Product data (9397 750 10649); supersedes Product specification 74LVT16374A_3 of 1999 Oct 18 (9397 750

06514)

Engineering Change Notice 853–1781 29140 (date: 20021101)

12

2004 Sep 16

Philips Semiconductors

Product data sheet

3.3V 16-bit edge-triggered D-type flip-flop

(3-State)

74LVT16374A

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data sheet

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data sheet

Product data sheet

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 09-04

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document number:

9397 750 14077

Philips

Semiconductors

13

2004 Sep 16


型号：	74LVT16374ADGG,118
厂家：	NXP
描述：	74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48-Pin 驱动信息通信管理光电二极管逻辑集成电路触发器
文件：	总13页 (文件大小：115K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVT16374ADGG,118 [NXP]

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