74LVT16500A [NXP]
3.3V 18-bit universal bus transceiver 3-State; 3.3V 18位通用总线收发器三态
| 型号： | 74LVT16500A |
| 厂家： | 
NXP |
| 描述： | 3.3V 18-bit universal bus transceiver 3-State |
| 文件： | 总14页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVT16500A
3.3V 18-bit universal bus transceiver
(3-State)
Product specification
1998 Feb 19
Supersedes data of 1997 Jun 12
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
FEATURES
DESCRIPTION
• 18-bit bidirectional bus interface
• 3-State buffers
The 74LVT16500A is a high-performance BiCMOS product
designed for V operation at 3.3V.
CC
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
high-impedance state.
• No bus current loading when output is tied to 5V bus
• Negative edge-triggered clock inputs
• Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA. The output enables are complimentary (OEAB is
active High, and OEBA is active Low).
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
and 200V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
= 25°C
t
t
Propagation delay
An to Bn or Bn to An
C = 50pF;
L
PLH
PHL
1.9
ns
V
CC
= 3.3V
C
Input capacitance (Control pins)
I/O pin capacitance
V = 0V or 3.0V
3
9
pF
pF
µA
IN
I
C
Outputs disabled; V = 0V or 3.0V
I/O
I/O
I
Total supply current
Outputs disabled; V = 3.6V
70
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
74LVT16500A DL
VT16500A DL
74LVT16500A DGG
VT16500A DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
OEAB
NAME AND FUNCTION
1
A-to-B Output enable input
27
OEBA
B-to-A Output enable input (active low)
A-to-B/B-to-A Latch enable input
2, 28
55,30
LEAB/LEBA
CPAB/CPBA
A-to-B/B-to-A Clock input (active falling edge)
Data inputs/outputs (A side)
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
A0-A17
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
B0-B17
GND
Data inputs/outputs (B side)
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Ground (0V)
V
CC
Positive supply voltage
2
1998 Feb 19
853-1789 18989
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
OEAB
LEAB
A0
1
2
56
GND
1
EN1
2C3
55
54
53
52
CPAB
B0
55
2
3
C3
GND
A1
4
GND
B1
G2
5
27
EN4
A2
6
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B2
30
28
5C6
7
V
V
CC
CC
C6
G5
A3
8
B3
A4
9
B4
A5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B5
3
54
3D
1
1
1
GND
A6
GND
B6
4
6D
5
6
52
51
49
A7
B7
A8
B8
8
9
A9
B9
48
47
A10
A11
GND
A12
A13
A14
B10
B11
GND
B12
B13
B14
10
12
13
14
45
44
43
15
42
16
17
41
40
V
V
CC
CC
19
20
38
37
A15
A16
B15
B16
21
23
24
26
36
34
33
31
GND 25
A17 26
OEBA 27
GND
B17
CPBA
GND
LEBA
28
SW00035
SW00036
LOGIC SYMBOL
30 28 27 55
2
1
3
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B0
A0
A1
5
B1
6
B2
A2
8
B3
A3
B4
A4
9
B5
A5
10
12
13
14
15
16
17
19
20
21
23
24
26
B6
A6
B7
A7
B8
A8
B9
A9
B10
B11
B12
B13
B14
B15
B16
B17
A10
A11
A12
A13
A14
A15
A16
A17
SW00034
3
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
FUNCTION TABLE
INPUTS
OUTPUTS
Internal
OPERATING MODE
Registers
OEAB
LEAB
CPAB
An
X
h
I
Bn
Z
L
L
H
↓
X
X
H
L
Disabled
X
Z
Disabled, Latch data
Disabled, Hold data
Disabled, Clock data
L
↓
X
Z
L
L
L
L
H
H
↓
H or L
X
h
I
NC
H
L
Z
L
↓
Z
L
↓
Z
H
H
H
H
H
H
H
H
X
H
L
h
I
H
L
H
L
Transparent
X
X
H
L
H
L
Latch data & display
Clock data & display
Hold data & display
↓
X
↓
L
L
L
L
h
I
H
L
H
L
↓
H or L
H or L
X
X
H
L
H
L
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h
L
I
= High voltage level one set-up time prior to the Enable or Clock transition
= Low voltage level
= Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X
Z
↓
= Don’t care
= High Impedance ”off” state
= High-to-Low Enable or Clock transition
4
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
LOGIC DIAGRAM
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
54
B1
A1
ID
C1
CLK
ID
C1
CLK
To 17 other channels
SW00234
5
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
DC supply voltage
–0.5 to +4.6
–50
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–0.5 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +7.0
128
I
DC output current
mA
OUT
Output in High state
–64
T
stg
Storage temperature range
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
LIMITS
SYMBOL
UNIT
MIN
2.7
0
MAX
3.6
V
CC
DC supply voltage
Input voltage
V
V
V
I
5.5
V
High-level input voltage
Input voltage
2.0
V
IH
V
0.8
–32
32
V
IL
I
High-level output current
Low-level output current
mA
OH
I
OL
mA
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
64
∆t/∆v
10
ns/V
T
amb
–40
+85
°C
6
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
V
1
MIN
TYP
–.85
MAX
V
IK
Input clamp voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 2.7V; I = –18mA
–1.2
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IK
= 2.7 to 3.6V; I = –100µA
V
CC
-0.2
V
CC
OH
V
High-level output voltage
= 2.7V; I = –8mA
2.4
2.0
2.55
2.30
0.07
0.3
V
OH
OH
= 3.0V; I = –32mA
OH
= 2.7V; I = 100µA
0.2
0.5
0.4
0.5
0.55
0.55
±1
OL
= 2.7V; I = 24mA
OL
V
Low-level output voltage
Power-up output low voltage
Input leakage current
Output off current
= 3.0V; I = 16mA
0.25
0.3
V
V
OL
OL
= 3.0V; I = 32mA
OL
= 3.0V; I = 64mA
0.36
0.1
OL
5
V
RST
= 3.6V; I = 1mA; V = GND or V
O I CC
= 3.6V; V = V or GND
0.1
I
CC
Control pins
I/O Data pins
= 0 or 3.6V; V = 5.5V
0.1
10
I
I
I
= 3.6V; V = 5.5V
1.0
20
µA
I
4
= 3.6V; V = V
0.1
10
I
CC
= 3.6V; V = 0
0.1
-5
I
I
= 0V; V or V = 0 to 4.5V
1.0
±100
µA
µA
OFF
I
O
= 3V; V = 0.8V
75
130
–130
I
Bus Hold current
A or B outputs7
I
V
V
= 3V; V = 2.0V
-75
HOLD
CC
I
= 0V to 3.6V; V = 3.6V
±500
CC
CC
Current into an output in the
I
V
= 5.5V; V = 3.0V
50
40
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
O
CC
I
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
I
V
V
V
V
= 3.6V; Outputs High, V = GND or V I
= 0
= 0
0.07
4
0.12
6
CCH
CC
CC
CC
CC
I
CC, O
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I
CC, O
mA
mA
CCL
CCZ
I
6
= 3.6V; Outputs Disabled; V = GND or V
I = 0
CC, O
0.07
0.12
I
Additional supply current per
= 3V to 3.6V; One input at V -0.6V,
CC
∆I
0.1
0.2
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 3.3V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I is measured with outputs pulled to V or GND.
CCZ
CC
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
7
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T = –40°C to +85°C.
amb
R
F
L
L
LIMITS
= 3.3V ±0.3V
SYMBOL
PARAMETER
WAVEFORM
V
CC
V
CC
= 2.7V
UNIT
1
MIN
TYP
MAX
MAX
f
Maximum clock frequency
1
2
150
350
MHz
ns
MAX
t
t
Propagation delay
An to Bn or Bn to An
0.5
0.5
1.9
1.9
4.2
4.2
5.4
5.4
PLH
PHL
t
t
Propagation delay
CPAB to Bn or CPBA to An
1.0
1.0
3.2
3.2
5.4
5.4
6.4
6.4
PLH
PHL
1
3
ns
ns
ns
ns
t
t
Propagation delay
LEAB to Bn or LEBA to An
1.0
1.0
2.4
2.9
5.4
5.4
6.4
6.4
PLH
PHL
t
Output enable time
to High and Low level
5
6
1.0
1.0
2.4
2.2
3.9
3.9
4.6
5.2
PZH
t
PZL
t
Output disable time
from High and Low Level
5
6
1.0
1.0
2.8
3.2
5.2
5.2
5.6
5.6
PHZ
t
PLZ
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC SETUP REQUIREMENTS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
UNIT
MIN
TYP
MIN
ts(H)
ts(L)
Setup time, High or Low
An to CPAB or Bn to CPBA
1.8
1.8
1.0
0.7
1.5
1.5
4
4
4
4
ns
ns
ns
ns
th(H)
th(L)
Hold time, High or Low
An to CPAB or Bn to CPBA
0
0
0
0
0
0
ts(H)
ts(L)
Setup time, High or Low
An to LEAB or Bn to CPBA
1.8
1.8
1.1
0.8
1.5
1.5
th(H)
th(L)
Hold time, High or Low
An to LEAB or Bn to LEBA
0
0
0
0
0
0
tw(H)
tw(L)
Pulse width, High or Low
CPAB or CPBA
1.2
1.2
0.8
0.8
1.5
1.5
1
3
ns
ns
tw(H)
LEAB or LEBA pulse width, High
1.2
0.8
1.5
8
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
AC WAVEFORMS
V
M
= 1.5V, V = GND to 2.7V
IN
1/f
MAX
3.0V or V
whichever is
less
CC
2.7V
0V
nA , nB
x
CEAB
CEBA
x
V
V
M
V
V
M
M
M
CPBA or
CPAB
V
V
M
M
0V
t (H)
S
t (H)
h
t (L)
h
t (L)
S
t
(L)
t (H)
W
W
t
PLH
t
PHL
CPAB or
CPBA
V
OH
3.0V or V
CC
whichever is
less
An or Bn
V
M
LEAB
or
LEBA
V
V
M
V
M
M
0V
V
OL
SW00038
SW00039
Waveform 4. Data Setup and Hold Times
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
2.7V
0V
OEBA
OEAB
V
V
M
M
2.7V
V
V
M
An or Bn
M
t
t
t
PHZ
PZH
0V
V
V
t
OH
PLH
PHL
V
–0.3V
OH
V
M
OH
An or Bn
V
V
M
M
An or Bn
V
SW00032
OL
SW00029
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 2. Propagation Delay, Transparent Mode
2.7V
2.7V
OEBA
OEAB
V
V
M
M
V
V
V
M
M
M
LEAB or
LEBA
0V
3V
0V
t
(H)
W
t
PLH
t
t
PLZ
PZL
t
PHL
V
OH
An or Bn
An or Bn
V
M
V
V
M
M
V
+0.3V
OL
V
OL
V
OL
SW00030
SW00033
Waveform 3. Propagation Delay, Enable to Output, and Enable
Pulse Width
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
9
1998 Feb 19
Philips Semiconductors
Product specification
3.3V 18-bit universal bus transceiver (3-State)
74LVT16500A
TEST CIRCUIT AND WAVEFORMS
6.0V
V
t
W
AMP (V)
90%
CC
90%
Open
NEGATIVE
PULSE
V
V
M
10%
M
GND
10%
R
R
L
V
V
OUT
0V
(t
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
)
THL
F
TLH
R
R
T
)
(t )
F
C
L
TLH
R
THL
L
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
6V
Input Pulse Definition
t
t
PLZ/ PZL
t
t
Open
GND
PLH/ PHL
t
/t
PHZ PZH
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
R = Load resistor; see AC CHARACTERISTICS for value.
L
Amplitude
2.7V
Rep. Rate
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance:
L
74LVT16
≤10MHz
500ns ≤2.5ns ≤2.5ns
See AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SW00040
10
1998 Feb 19
Philips Semiconductors
Product specification
3.3V LVT 18-bit universal bus transceiver (3-State)
74LVT16500A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5mm
SOT371-1
11
1998 Feb 19
Philips Semiconductors
Product specification
3.3V LVT 18-bit universal bus transceiver (3-State)
74LVT16500A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
12
1998 Feb 19
Philips Semiconductors
Product specification
3.3V LVT 18-bit universal bus transceiver (3-State)
74LVT16500A
NOTES
13
1998 Feb 19
Philips Semiconductors
Product specification
3.3V LVT 18-bit universal bus transceiver (3-State)
74LVT16500A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03556
Document order number:
Philips
Semiconductors
相关型号：
74LVT16500ADGG-T
IC LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56, Bus Driver/Transceiver
NXP
©2020 ICPDF网 联系我们和版权申明