74LVT241PW,112 [NXP]
74LVT241 - 3.3 V octal buffer/line driver; 3-state TSSOP2 20-Pin;
| 型号： | 74LVT241PW,112 |
| 厂家： | 
NXP |
| 描述： | 74LVT241 - 3.3 V octal buffer/line driver; 3-state TSSOP2 20-Pin PC 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVT241
3.3 V octal buffer/line driver; 3-state
Rev. 03 — 7 May 2008
Product data sheet
1. General description
The 74LVT241 high-performance BiCMOS device combines low static and dynamic power
dissipation with high speed and high output drive.
This device is an octal buffer that is ideal for driving bus lines. The device features two
output enables (1OE, 2OE), each controlling four of the 3-state outputs.
2. Features
I 3-state buffers
I Octal bus interface
I Input and output interface capability to systems at 5 V supply
I TTL input and output switching levels
I Output capability: +64 mA/−32 mA
I Latch-up protection exceeds 500 mA per JESD78 class II level A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
I Live insertion/extraction permitted
I Power-up 3-state
I No bus current loading when output is tied to 5 V bus
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT241D
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVT241DB
74LVT241PW
74LVT241BQ
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
4. Functional diagram
1Y0
1A0
1A1
1A2
2
4
6
18
16
14
12
1Y1
1Y2
1Y3
1A3
8
1
1
EN
1OE
18
2
16
14
12
4
6
8
2Y0
2Y1
2Y2
2Y3
2A0
2A1
2A2
17
15
13
3
5
7
9
19
11
EN
9
2A3
11
19
7
5
3
13
15
17
2OE
mna772
mna773
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
2 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
74LVT241
terminal 1
index area
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1A0
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
1
2
20
19
18
17
16
15
14
13
12
11
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND
V
CC
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
2A3
3
4
5
74LVT241
6
(1)
GND
7
8
9
001aah735
10
Transparent top view
001aah734
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 3. Pin configuration for SO20 and (T)SSOP20
Fig 4. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE
Pin description
Pin
Description
1
output enable input (active LOW)
data input
1A0 to 1A3
2A0 to 2A3
GND
2, 4, 6, 8
17, 15, 13, 11
data input
10
ground (0 V)
1Y0 to 1Y3
2Y0 to 2Y3
2OE
18, 16, 14, 12
data output
3, 5, 7, 9
19
data output
output enable input (active HIGH)
supply voltage
VCC
20
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
3 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
6. Functional description
Table 3.
Function table
Inputs
Outputs
1OE
L
2OE
H
1An
L
2An
L
1Yn
L
2Yn
L
L
H
H
H
H
H
H
L
X
X
Z
Z
[1] H = HIGH voltage level;
L = LOW voltage level;
X = Don’t care;
Z = High impedance “OFF” state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).[1]
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−50
−50
-
Max
+4.6
+7.0
+7.0
-
Unit
V
supply voltage
[2]
[2]
input voltage
V
VO
output voltage
output in OFF or HIGH state
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
mA
mA
mA
mA
°C
IOK
VO < 0 V
-
IO
output in LOW state
output in HIGH state
128
-
−64
−65
-
Tstg
Tj
storage temperature
junction temperature
total power dissipation
+150
+150
500
°C
[3]
Ptot
Tamb = −40 °C to +85 °C
-
mW
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
[2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Conditions
Symbol Parameter
Min
2.7
0
Max
3.6
5.5
-
Unit
V
VCC
VI
supply voltage
input voltage
V
IOH
HIGH-level output current
−32
mA
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
4 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
Table 5.
Recommended operating conditions …continued
Symbol Parameter
Conditions
Min
Max
32
Unit
mA
mA
°C
IOL
LOW-level output current
-
current duty cycle ≤ 50 %; fi ≥ 1 kHz
-
64
Tamb
ambient temperature
in free air
−40
+85
10
∆t/∆V
input transition rise and fall rate output enabled
0
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
−1.2
Typ[1]
−0.9
Max Unit
VIK
VIH
VIL
input clamping voltage
VCC = 2.7 V; IIK = –18 mA
-
-
V
V
HIGH-level input voltage
LOW-level input voltage
2.0
-
-
-
0.8
V
V
V
V
V
V
V
V
V
VOH
HIGH-level
VCC = 2.7 V to 3.6 V; IOH = −100 µA
VCC = 2.7 V; IOH = −8 mA
VCC − 0.2 VCC − 0.1 -
output voltage
2.4
2.0
2.5
2.2
0.1
0.3
0.25
0.3
0.4
-
VCC = 3.0 V; IOH = −32 mA
-
VOL
LOW-level output voltage VCC = 2.7 V; IOL = 100 µA
VCC = 2.7 V; IOL = 24 mA
0.2
0.5
0.4
0.5
0.55
-
-
-
-
VCC = 3.0 V; IOL = 16 mA
VCC = 3.0 V; IOL = 32 mA
VCC = 3.0 V; IOL = 64 mA
II
input leakage current
control and data pins
VCC = 0 V or 3.6 V; VI = 5.5 V
control pins
-
-
1
10
µA
µA
VCC = 3.6 V; VI = VCC or GND
data pins
0.1
±1
[2]
VCC = 3.6 V; VI = VCC
VCC = 3.6 V; VI = 0 V
-
0.1
−1
1
1
µA
µA
µA
µA
µA
µA
−5
-
-
IOFF
IBHL
IBHH
IBHLO
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
±100
bus hold LOW current
bus hold HIGH current
VCC = 3.0 V; VI = 0.8 V
VCC = 3.0 V; VI = 2.0 V
VCC = 3.6 V; VI = 0 V to 3.6 V
75
-
150
−150
-
-
−75
[3]
[3]
bus hold LOW
overdrive current
500
-
IBHHO
bus hold HIGH
VCC = 3.6 V; VI = 0 V to 3.6 V
-
-
−500
µA
overdrive current
ILO
output leakage current
VO = 5.5 V; VCC = 3.0 V; output HIGH
-
-
60
125
µA
µA
[4]
IO(pu/pd) power-up/power-down
output current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC;
±1
±100
VI = GND or VCC; 1OE, 2OE = don’t care
IOZ
OFF-state output current VCC = 3.6 V; VO = 3.0 V
-
1
5
-
µA
µA
VCC = 3.6 V; VO = 0.5 V
−5
−1
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
5 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ[1]
Max Unit
ICC
supply current
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
outputs HIGH
-
-
-
-
0.12
0.19
mA
mA
mA
mA
outputs LOW
3
12
[5]
[6]
outputs disabled
0.12
0.1
0.19
0.25
∆ICC
additional supply current per input pin; VCC = 3.0 V to 3.6 V;
one input = VCC − 0.6 V other inputs at
V
CC or GND
CI
input capacitance
1OE and 2OE inputs; outputs disabled;
VI = 0 V or 3.0 V
-
-
4
8
-
-
pF
pF
CI/O
input/output capacitance at input/output data pins, outputs disabled;
I/O = 0 V or 3.0 V
V
[1] All typical values are measured at Tamb = 25 °C.
[2] Unused pins at VCC or GND.
[3] This is the bus hold overdrive current required to force the input to the opposite logic state.
[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 ms is permitted. This parameter is valid for Tamb = +25 °C only.
[5] ICC with the outputs disabled is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8; Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ[1]
Max Unit
tPLH
tPHL
tPZH
LOW to HIGH propagation delay
1An to 1Yn, 2An to 2Yn;
see Figure 5
VCC = 2.7 V
-
-
4.0
3.8
ns
ns
VCC = 3.3 V ± 0.3 V
1.0
2.8
HIGH to LOW propagation delay
1An to 1Yn, 2An to 2Yn;
see Figure 5
VCC = 2.7 V
-
-
4.0
3.8
ns
ns
VCC = 3.3 V ± 0.3 V
1.0
2.8
OFF-state to HIGH propagation delay 1OE to 1Yn; see Figure 6
VCC = 2.7 V
-
-
5.0
4.4
ns
ns
VCC = 3.3 V ± 0.3 V
2OE to 2Yn; see Figure 7
VCC = 2.7 V
1.0
3.2
-
-
5.6
5.1
ns
ns
VCC = 3.3 V ± 0.3 V
1.0
3.8
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
6 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8; Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ[1]
Max Unit
tPZL
tPHZ
tPLZ
OFF-state to LOW propagation delay 1OE to 1Yn; see Figure 6
VCC = 2.7 V
-
-
4.9
4.3
ns
ns
VCC = 3.3 V ± 0.3 V
1.0
3.1
2OE to 2Yn; see Figure 7
VCC = 2.7 V
-
-
5.4
5.0
ns
ns
VCC = 3.3 V ± 0.3 V
1.0
3.8
HIGH to OFF-state propagation delay 1OE to 1Yn; see Figure 6
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
-
-
5.4
5.2
ns
ns
2.0
3.6
2OE to 2Yn; see Figure 7
VCC = 2.7 V
-
-
5.0
4.5
ns
ns
VCC = 3.3 V ± 0.3 V
1.0
3.1
LOW to OFF-state propagation delay 1OE to 1Yn; see Figure 6
VCC = 2.7 V
-
-
4.3
4.2
ns
ns
VCC = 3.3 V ± 0.3 V
1.6
2.9
2OE to 2Yn; see Figure 7
VCC = 2.7 V
-
-
4.3
4.0
ns
ns
VCC = 3.3 V ± 0.3 V
1.0
2.8
[1] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V.
11. Waveforms
V
I
V
1An, 2An input
GND
M
t
t
PLH
PHL
V
OH
V
1Yn, 2Yn output
M
V
OL
mna774
See Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (1An, 2An) to output (1Yn, 2Yn) propagation delays and output transition times
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
7 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
V
I
1OE input
V
M
t
GND
3.0 V
t
PLZ
PZL
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aah813
See Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. 3-state output enable and disable times
V
I
2OE input
V
M
t
GND
3.0 V
t
PLZ
PZL
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
output
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aah814
See Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. 3-state output enable and disable times
Table 8.
VCC
Measurement points
Input
VM
Output
VX
VY
OH − 0.3 V
VM
2.7 V to 3.6 V
1.5 V
VOL + 0.3 V
V
1.5 V
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
8 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for switching times
Table 9.
Input
VI
Test data
Load
RL
VEXT
fi
tW
tr, tf
CL
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
2.7 V
≤ 10 MHz
500 ns
≤ 2.5 ns
500 Ω
50 pF
6 V
open
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
9 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 9. Package outline SOT163-1 (SO20)
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
10 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 10. Package outline SOT339-1 (SSOP20)
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
11 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 11. Package outline SOT360-1 (TSSOP20)
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
12 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 12. Package outline SOT764-1 (DHVQFN20)
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
13 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
CDM
Description
Bipolar Complementary Metal Oxide Semiconductor
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74LVT241_3
Modifications:
Release date
Data sheet status
Change notice
ECN07_046
Supersedes
20080507
Product data sheet
74LVT241_2
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• DHVQFN20 package added Section 3 “Ordering information” and Section 12 “Package outline”.
74LVT241_2
74LVT241_1
19980219
Product specification
-
74LVT241_1
19960529
Product specification
-
-
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
14 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
15 of 16
74LVT241
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 May 2008
Document identifier: 74LVT241_3
相关型号：
74LVT241PWDH-T
IC LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP1-20, Bus Driver/Transceiver
NXP
©2020 ICPDF网 联系我们和版权申明