74LVT573 [NXP]
3.3V Octal D-type transparent latch 3-State; 3.3V八路D型透明锁存器三态
| 型号： | 74LVT573 |
| 厂家： | 
NXP |
| 描述： | 3.3V Octal D-type transparent latch 3-State |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVT573
3.3V Octal D-type transparent latch
(3-State)
Product specification
1998 Feb 19
Supersedes data of 1995 Nov 14
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
FEATURES
DESCRIPTION
The LVT573 is a high-performance BiCMOS product designed for
VCC operation at 3.3V. This device is an octal transparent latch
coupled to eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (E) and Output
Enable (OE) control gates. The 74LVT573 has a broadside pinout
configuration to facilitate PC board layout and allow easy interface
with microprocessors.
• Inputs and outputs on opposite side of package allow easy
interface to microprocessors
• 3-State output buffers
• Common output enable
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• Live insertion/extraction permitted
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• Power-up 3-State
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
When OE is Low, the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
• Power-up reset
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
2.5
2.7
PLH
PHL
C = 50pF; V = 3.3V
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or 3.0V
4
8
pF
pF
IN
I
C
Outputs disabled; V = 0V or 3.0V
O
OUT
CCZ
I
Outputs disabled; V = 3.6V
.13
mA
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LVT573 D
DWG NUMBER
SOT163-1
20-Pin Plastic SOL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVT573 D
74LVT573 DB
74LVT573 PW
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
74LVT573 DB
SOT339-1
74LVT573PW DH
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
Output enable input
(active-Low)
1
OE
2, 3, 4, 5, 6, 7, 8, 9
D0-D7
Q0-Q7
Data inputs
OE
D0
1
2
3
4
5
20
19
18
17
16
V
CC
19, 18, 17, 16, 15,
14, 13, 12
Q0
Data outputs
D1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
Enable input
(active-High)
11
E
D2
D3
10
20
GND
Ground (0V)
D4
6
7
15
14
13
12
11
V
CC
Positive supply voltage
D5
D6
8
D7
9
GND
10
SV00031
2
1998 Feb 19
853–1750 18988
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
C1
2
3
4
5
6
7
8
9
2
19
1D
D0 D1 D2 D3 D4 D5 D6 D7
3
4
18
17
11
1
E
5
6
16
15
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
7
8
14
13
19 18 17 16 15 14 13 12
SV00032
9
12
SV00033
FUNCTION TABLE
INPUTS
OUTPUTS
Q0 – Q7
INTERNAL
REGISTER
OPERATING MODE
OE
E
Dn
L
L
H
H
L
H
L
H
L
H
Enable and read register
Latch and read register
L
L
↓
↓
I
h
L
H
L
H
L
L
X
X
NC
NC
NC
Z
Hold
H
X
Disable outputs
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low E transition
LOGIC DIAGRAM
D0
2
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
D
D
E
D
E
D
E
D
E
D
E
D
E
D
E
E
Q
Q
Q
Q
Q
Q
Q
Q
11
1
E
OE
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SV00034
3
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +4.6
–50
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–0.5 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +7.0
128
I
DC output current
mA
OUT
Output in High state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
2.7
0
MAX
3.6
V
CC
DC supply voltage
Input voltage
V
V
V
I
5.5
V
High-level input voltage
Input voltage
2.0
V
IH
V
0.8
–32
32
V
IL
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz
Input transition rise or fall rate; outputs enabled
Operating free-air temperature range
64
∆t/∆v
10
ns/V
T
amb
–40
+85
°C
4
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
Input clamp voltage
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
V
1
MIN
TYP
MAX
V
IK
V
V
V
V
V
V
V
V
V
V
= 2.7V; I = –18mA
–0.9
–1.2
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IK
= 2.7 to 3.6V; I = –100µA
V
-0.2
V
CC
-0.1
OH
CC
V
OH
High-level output voltage
= 2.7V; I = –8mA
2.4
2.5
V
OH
= 3.0V; I = –32mA
2.0
2.2
0.1
OH
= 2.7V; I = 100µA
0.2
0.5
OL
= 2.7V; I = 24mA
0.3
OL
V
OL
Low-level output voltage
= 3.0V; I = 16mA
0.25
0.3
0.4
V
OL
= 3.0V; I = 32mA
0.5
OL
= 3.0V; I = 64mA
0.4
0.55
0.55
OL
5
V
RST
Power-up output low voltage
Input leakage current
Output off current
= 3.6V; I = 1mA; V = GND or V
CC
0.13
V
O
I
V
CC
V
CC
V
CC
= 0 or 3.6V; V = 5.5V
1
10
±1
1
I
= 3.6V; V = V or GND
Control pins
±0.1
0.1
I
CC
CC
I
I
µA
= 3.6V; V = V
I
4
Data pins
V
= 3.6V; V = 0
–1
1
-5
CC
CC
I
I
V
= 0V; V or V = 0 to 4.5V
±100
µA
µA
OFF
I
O
V
CC
V
CC
V
CC
= 3V; V = 0.8V
75
150
I
7
= 3V; V = 2.0V
–75
–150
I
Bus Hold current A inputs
I
HOLD
= 0V to 3.6V; V = 3.6V
±500
CC
Current into an output in the
I
V
= 5.5V; V = 3.0V
60
1
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
O
CC
I
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
= 3.6V; V = 3V; V = V or V
IH
1
–1
5
OZH
CC
CC
CC
CC
CC
O
I
IL
µA
I
= 3.6V; V = 0.5V; V = V or V
IH
–5
OZL
O
I
IL
I
= 3.6V; Outputs High, V = GND or V I 0
CC, O =
0.13
3
0.19
12
CCH
I
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
I
5
I
V
= 3.6V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.13
0.19
CCZ
I
Additional supply current per
V
= 3V to 3.6V; One input at V -0.6V,
CC CC
∆I
0.1
0.2
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 3.3V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only
amb
4. Unused pins at V or GND.
CC
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
6. I is measured with outputs pulled to V or GND.
CCZ
CC
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
5
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
= 3.3V ± 0.3V
SYMBOL
PARAMETER
WAVEFORM
V
CC
V
CC
= 2.7V
UNIT
1
MIN
TYP
MAX
MAX
t
t
Propagation delay
Dn to Qn
1.0
1.0
2.5
2.7
4.2
4.3
4.7
5.2
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
E to Qn
1.6
2.5
3.5
4.3
5.6
6.5
6.3
7.2
PLH
PHL
t
t
Output enable time
to High and Low level
4
5
1.0
1.3
2.8
3.3
5.1
5.5
6.2
6.6
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
2.0
1.5
3.7
3.0
5.7
4.6
6.7
5.1
PHZ
PLZ
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω; T = –40°C to +85°C.
amb
R
F
L
L
LIMITS
= 3.3V ± 0.3V
SYMBOL
PARAMETER
WAVEFORM
V
CC
V
CC
= 2.7V
UNIT
MIN
MAX
MIN
t (H)
t (L)
S
0.7
0.7
0.6
0.6
S
Setup time, High or Low, Dn to E
3
ns
T (H)
T (L)
H
1.6
1.6
1.8
1.8
H
Hold time, High or Low, Dn to E
E pulse width High
3
1
ns
ns
T (H)
W
3.3
3.3
AC WAVEFORMS
V
M
= 1.5V, V = GND to 2.7V
IN
2.7V
0V
2.7V
E
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
Dn
0V
t
w
(H)
t (H)
s
t (L)
s
t (H)
h
t (L)
h
t
t
PLH
PHL
V
2.7V
OH
OL
1.5V
E
1.5V
1.5V
Qn
V
0V
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00035
Waveform 1. Propagation Delay, Enable to Output, and Enable
Pulse Width
SV00118
Waveform 3. Data Setup and Hold Times
2.7V
1.5V
1.5V
Dn
Qn
0V
t
t
PHL
PLH
V
OH
1.5V
1.5V
V
OL
SV00117
Waveform 2. Propagation Delay for Data to Outputs
6
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
2.7V
2.7V
1.5V
1.5V
OE
Qn
1.5V
t
1.5V
OE
Qn
0V
0V
3V
t
t
PHZ
PZH
t
PZL
PLZ
V
OH
V
–0.3V
OH
1.5V
1.5V
V
+0.3V
OL
0V
V
OL
SV00119
SV00120
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
6.0V
V
CC
t
W
AMP (V)
Open
GND
90%
90%
NEGATIVE
PULSE
V
V
M
V
V
OUT
M
10%
R
R
IN
L
10%
90%
PULSE
GENERATOR
D.U.T.
0V
(t
t
t
(t
(t
)
t
TLH
)
THL
F
R
R
T
C
L
L
)
t
(t )
TLH
R
THL F
AMP (V)
90%
M
Test Circuit for 3-State Outputs
POSITIVE
PULSE
V
V
M
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
Open
6V
Input Pulse Definition
t
/t
PLH PHL
t
/t
PLZ PZL
t
/t
GND
PHZ PZH
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
R = Load resistor; see AC CHARACTERISTICS for value.
L
Amplitude
Rep. Rate
t
t
R
t
F
W
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74LVT
2.7V
v10MHz
500ns v2.5ns v2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SV00092
7
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
8
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
9
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
10
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
NOTES
11
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch
(3-State)
74LVT573
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03538
Document order number:
Philips
Semiconductors
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