74LVT574PW,112 [NXP]
74LVT(H)574 - 3.3 V octal D-type flip-flop; 3-state TSSOP2 20-Pin;
| 型号： | 74LVT574PW,112 |
| 厂家： | 
NXP |
| 描述： | 74LVT(H)574 - 3.3 V octal D-type flip-flop; 3-state TSSOP2 20-Pin 驱动 信息通信管理 光电二极管 逻辑集成电路 触发器 |
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74LVT574; 74LVTH574
3.3 V octal D-type flip-flop; 3-state
Rev. 7 — 22 November 2011
Product data sheet
1. General description
The 74LVT574; 74LVTH574 is a high-performance product designed for VCC operation at
3.3 V.
This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The
two sections of the device are controlled independently by the clock (pin CP) and output
enable (pin OE) control gates. The state of each Dn input (one setup time before the
LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Qn output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active LOW output enable (pin OE) controls all eight 3-state buffers independent of
the clock operation.
When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the
outputs are in the high-impedance OFF-state, which means they will neither drive nor load
the bus.
2. Features and benefits
Inputs and outputs arranged for easy interfacing to microprocessors
3-state outputs for bus interfacing
Common output enable control
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-state
Latch-up protection
JESD78 class II exceeds 500 mA
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT574D
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
SOT339-1
SOT360-1
74LVTH574D
74LVT574DB
74LVTH574DB
74LVT574PW
74LVTH574PW
74LVT574BQ
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
4. Functional diagram
1
EN2
11
11
C1
CP
2
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
19
1D
2
3
4
5
6
7
8
9
3
4
5
18
17
16
6
7
8
9
15
14
13
12
OE
1
mna798
001aae466
Fig 1. Logic symbol
Fig 2. IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae467
Fig 3. Logic diagram
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
2 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
74LVT574
74LVTH574
terminal 1
index area
74LVT574
74LVTH574
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
20
19
18
17
16
15
14
13
12
11
OE
D0
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
3
D1
4
D2
5
D3
6
D4
(1)
GND
7
D5
8
D6
9
D7
001aah711
10
GND
001aae758
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input
Fig 4. Pin configuration for SO20, and (T)SSOP20
Fig 5. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
output enable input (active LOW)
data input
D0 to D7
GND
2, 3, 4, 5, 6, 7, 8, 9
10
ground (0 V)
CP
11
clock pulse input (active rising edge)
data output
Q0 to Q7
VCC
19, 18, 17, 16, 15, 14, 13, 12
20
supply voltage
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
3 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
6. Functional description
6.1 Function table
Table 3.
Function table [1]
Operating mode
Control
Input
Internal register Output
Qn
OE
CP
Dn
l
Load and read register
L
L
L
h
H
H
NC
Z
Hold
L
NC
X
NC
NC
Dn
Disable outputs
H
L or H
X
Dn
Z
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH clock transition;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
Max
+4.6
+7.0
+7.0
50
50
128
64
+150
150
500
Unit
V
supply voltage
0.5
[1]
[1]
input voltage
0.5
V
VO
output voltage
output in OFF-state or HIGH-state
VI < 0 V
0.5
V
IIK
input clamping current
output clamping current
output current
-
mA
mA
mA
mA
C
IOK
VO < 0 V
-
IO
output in LOW-state
output in HIGH-state
-
-
Tstg
Tj
storage temperature
junction temperature
total power dissipation
65
[2]
[3]
-
-
C
Ptot
Tamb = 40 C to +85 C
mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] For SO20 packages: above 70 C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
4 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
Max
3.6
5.5
-
Unit
V
VCC
VI
supply voltage
2.7
input voltage
0
V
VIH
VIL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
2.0
V
-
0.8
32
32
V
-
mA
mA
mA
C
ns/V
-
current duty cycle 50 %; fi 1 kHz
in free air
-
64
Tamb
ambient temperature
40
+85
10
t/V
input transition rise and fall rate
outputs enabled
-
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Unit
Min
Typ[1]
Max
VIK
input clamping voltage
VCC = 2.7 V; IIK = 18 mA
1.2
0.9
-
-
-
-
V
V
V
V
VOH
HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = 100 A
VCC 0.2 VCC 0.1
VCC = 2.7 V; IOH = 8 mA
2.4
2.0
2.5
2.2
VCC = 3.0 V; IOH = 32 mA
VOL
LOW-level output voltage VCC = 2.7 V
IOL = 100 A
-
-
0.1
0.3
0.2
0.5
V
V
IOL = 24 mA
VCC = 3.0 V
IOL = 16 mA
-
-
-
-
0.25
0.3
0.4
0.5
V
V
V
V
IOL = 32 mA
IOL = 64 mA
0.4
0.55
0.55
[2]
[3]
VOL(pu) power-up LOW-level
output voltage
VCC = 3.6 V; IO = 1 mA; VI = GND or VCC
0.13
II
input leakage current
all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V
control pins; VCC = 3.6 V; VI = VCC or GND
data pins; VCC = 3.6 V
-
-
1
10
A
A
0.1
1
VI = VCC
-
5
-
0.1
1
1
-
A
A
VI = 0 V
IOFF
ILO
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
1
100 A
[4]
output leakage current
bus hold LOW current
bus hold HIGH current
VO = 5.5 V and VCC = 3.0 V; output HIGH
VCC = 3.0 V; VI = 0.8 V
-
60
125
-
A
A
A
A
IBHL
IBHH
IBHHO
75
-
150
150
-
[4]
[4]
VCC = 3.0 V; VI = 2.0 V
75
500
bus hold HIGH
VCC = 3.6 V; VI = 0 V to 3.6 V
-
overdrive current
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
5 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Unit
Min
Typ[1]
Max
IBHLO
bus hold LOW
VCC = 3.6 V; VI = 0 V to 3.6 V
500
-
-
A
overdrive current
[5]
IO(pu/pd) power-up/power-down
output current
VCC 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC; OE = don’t care
;
-
1
100 A
IOZ
OFF-state output current VCC = 3.6 V; VI = VIH or VIL
output HIGH: VO = 3.0 V
-
1
1
5
-
A
A
output LOW: VO = 0.5 V
5
ICC
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH
outputs LOW
outputs disabled
-
-
-
-
0.13
3
0.19 mA
12 mA
0.19 mA
[6]
[7]
0.13
0.1
ICC
additional supply current per input pin; VCC = 3 V to 3.6 V; one input
0.2
mA
at VCC 0.6 V and other inputs at VCC or
GND
CI
input capacitance
output capacitance
VI = 0 V or 3.0 V
-
-
4
8
-
-
pF
pF
CO
outputs disabled; VO = 0 V or 3.0 V
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at VCC or GND.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V
a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only.
[6] ICC is measured with outputs pulled to VCC or GND.
[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 10.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Unit
Min
Typ[1]
Max
tPLH
tPHL
tPZH
LOW to HIGH propagation delay
CP to Qn; see Table 6
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
1.7
-
3.6
-
5.4
6.2
ns
ns
HIGH to LOW propagation delay
CP to Qn; see Table 6
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
2.4
-
4.3
-
5.9
6.6
ns
ns
OFF-state to HIGH propagation delay OE to Qn; see Figure 7
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
1.0
-
2.9
-
4.8
5.9
ns
ns
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
6 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions
Tamb = 40 C to +85 C Unit
Min
Typ[1]
Max
tPZL
tPHZ
tPLZ
tsu
OFF-state to LOW propagation delay OE to Qn; see Figure 8
VCC = 3.0 V to 3.6 V
1.3
-
3.4
-
5.1
6.2
ns
ns
VCC = 2.7 V
HIGH to OFF-state propagation delay OE to Qn; see Figure 7
VCC = 3.0 V to 3.6 V
1.9
-
4.0
-
5.5
5.9
ns
ns
VCC = 2.7 V
LOW to OFF-state propagation delay OE to Qn; see Figure 8
VCC = 3.0 V to 3.6 V
1.7
-
3.2
-
4.5
4.5
ns
ns
VCC = 2.7 V
[2]
[3]
[4]
set-up time
Dn to CP; see Figure 9
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
2.0
2.4
-
-
-
-
ns
ns
th
hold time
Dn to CP; see Figure 9
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
0.3
0
-
-
-
-
ns
ns
tW
pulse width
CP input; see Figure 6
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
3.3
3.3
150
-
-
-
-
-
-
ns
ns
fmax
maximum frequency
CP input; VCC = 3.0 V to 3.6 V;
see Figure 6
MHz
[1] Typical values are at VCC = 3.3 V and Tamb = 25 C.
[2] tsu is the same as tsu(H) and tsu(L)
[3] th is the same as th(H) and th(L)
[4] tW is the same as tWH and tWL
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
7 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
11. Waveforms
1 / f
max
V
I
CP input
V
M
GND
t
t
WL
WH
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aac445
Measurement points are given in Table 8
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay clock input (CP) to output (Qn), pulse width clock (CP) and maximum clock frequency
V
V
I
I
V
V
OE input
GND
V
M
M
V
M
t
OE input
GND
M
t
t
PZH
t
PHZ
PZL
PLZ
V
3.0 V
OH
V
Y
Qn output
GND
V
Qn output
V
M
M
V
X
V
OL
001aae468
001aae469
Measurement points are given in Table 8
Measurement points are given in Table 8
VOL and VOH are typical voltage output levels that occur
with the output load.
VOL and VOH are typical voltage output levels that occur
with the output load.
Fig 7. Output enable time to HIGH-state and output
disable time from HIGH-state
Fig 8. Output enable time to LOW-state and output
disable time from LOW-state
V
l
V
V
V
V
M
Dn input
CP input
M
M
M
GND
t
t
t
t
h(L)
su(H)
h(H)
su(L)
V
l
V
V
M
M
GND
001aac738
Measurement points are given in Table 8
Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data setup and hold times
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
8 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
Table 8.
Input
VM
Measurement points
Output
VM
VX
VOL + 0.3 V
VY
1.5 V
1.5 V
VOH 0.3 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 10. Load circuitry for switching times
Table 9.
Input
VI
Test data
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
2.7 V
10 MHz
500 ns
2.5 ns
50 pF
500
6 V
open
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
9 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 11. Package outline SOT163-1 (SO20)
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
10 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 12. Package outline SOT339-1 (SSOP20)
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
11 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 13. Package outline SOT360-1 (TSSOP20)
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
12 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 14. Package outline SOT764-1 (DHVQFN20)
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
13 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
DUT
Description
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
MOS
TTL
Metal Oxide Semiconductor
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20111122
Data sheet status
Change notice
Supersedes
74LVT_LVTH574 v.7
Modifications:
Product data sheet
-
74LVT_LVTH574 v.6
• Legal pages updated.
74LVT_LVTH574 v.6
74LVT_LVTH574 v.5
74LVT_LVTH574 v.4
74LVT_LVTH574 v.3
74LVT574 v.2
20110912
20110727
20080911
20060323
19980219
19951114
Product data sheet
-
-
-
-
-
-
74LVT_LVTH574 v.5
74LVT_LVTH574 v.4
74LVT_LVTH574 v.3
74LVT574 v.2
74LVT574 v.1
-
Product data sheet
Product data sheet
Product data sheet
product specification
product specification
74LVT574 v.1
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
14 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
15 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT_LVTH574
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 22 November 2011
16 of 17
74LVT574; 74LVTH574
NXP Semiconductors
3.3 V octal D-type flip-flop; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 November 2011
Document identifier: 74LVT_LVTH574
相关型号：
74LVT574SJ
LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20
ROCHESTER
74LVT574SJX
LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20
ROCHESTER
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