74LVTH125PW,118 [NXP]
74LVT(H)125 - 3.3 V quad buffer; 3-state TSSOP 14-Pin;
| 型号： | 74LVTH125PW,118 |
| 厂家： | 
NXP |
| 描述： | 74LVT(H)125 - 3.3 V quad buffer; 3-state TSSOP 14-Pin 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
Rev. 06 — 6 March 2006
Product data sheet
1. General description
The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for VCC
operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving
bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each
controlling one of the 3-state outputs.
2. Features
I Quad bus interface
I 3-state buffers
I Output capability: +64 mA and −32 mA
I TTL input and output switching levels
I Input and output interface capability to systems at 5 V supply
I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
I Live insertion and extraction permitted
I No bus current loading when output is tied to 5 V bus
I Power-up 3-state
I Latch-up protection:
N JESD78: exceeds 500 mA
I ESD protection:
N MIL STD 883 method 3015: exceeds 2000 V
N Machine model: exceeds 200 V
3. Quick reference data
Table 1.
Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max Unit
tPLH
LOW-to-HIGH propagation CL = 50 pF; VCC = 3.3 V
delay nA to nY
-
2.7
-
ns
tPHL
HIGH-to-LOW propagation CL = 50 pF; VCC = 3.3 V
delay nA to nY
-
2.9
-
ns
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
Table 1.
Quick reference data …continued
GND = 0 V; Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
4
Max Unit
Ci
input capacitance
VI = 0 V or 3.0 V
-
-
-
-
pF
pF
Co
output capacitance
outputs disabled;
VO = 0 V or 3.0 V
8
ICC
quiescent supply current
outputs disabled;
-
0.13
-
mA
VCC = 3.6 V
4. Ordering information
Table 2.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT125D
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVT125DB
74LVT125PW
74LVT125BQ
SSOP14
TSSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
SOT402-1
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74LVTH125D
−40 °C to +85 °C
−40 °C to +85 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT337-1
SOT402-1
74LVTH125DB
SSOP14
TSSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
74LVTH125PW −40 °C to +85 °C
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74LVTH125BQ
−40 °C to +85 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
2 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
5. Functional diagram
1A
1Y
2Y
3Y
4Y
3
6
2
2
1
3
1
1OE
2A
1
5
EN1
5
6
4
2OE
3A
4
9
9
8
8
10
3OE
4A
10
12
12
11
13
11
4OE
13
mna229
mna228
Fig 1. Logic symbol
Fig 2. IEC logic symbol
nY
nA
nOE
mna227
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
3
4
5
6
7
14
13
12
11
10
9
1OE
V
CC
1A
1Y
4OE
4A
2
3
4
5
6
13
12
11
10
9
1A
1Y
4OE
4A
2OE
2A
125
4Y
2OE
2A
125
4Y
3OE
3A
(1)
GND
3OE
3A
2Y
2Y
8
GND
3Y
001aac477
001aac476
Transparent top view
(1) The die substrate is attached to the
exposed die pad using conductive die
attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14, SSOP14
and TSSOP14
Fig 5. Pin configuration DHVQFN14
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
3 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
6.2 Pin description
Table 3.
Symbol
1OE
1A
Pin description
Pin
1
Description
1 output enable input (active LOW)
2
1 data input
1Y
3
1 data output
2OE
2A
4
2 output enable input (active LOW)
2 data input
5
2Y
6
2 data output
GND
3Y
7
ground (0 V)
8
3 data output
3A
9
3 data input
3OE
4Y
10
11
12
13
14
3 output enable input (active LOW)
4 data output
4A
4 data input
4OE
VCC
4 output enable input (active LOW)
supply voltage
7. Functional description
7.1 Function table
Table 4.
Control
nOE
Function table[1]
Input
nA
L
Output
nY
L
L
H
H
Z
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
4 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+4.6
+7.0
+7.0
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
IIK
IOK
IO
input clamping current
VI < 0 V
-
−50
−50
128
−64
+150
150
mA
mA
mA
mA
°C
output clamping current VO < 0 V
-
output current
output in LOW-state
output in HIGH-state
-
-
Tstg
Tj
storage temperature
junction temperature
−65
[2]
-
°C
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Conditions
Symbol Parameter
Min
Typ
Max
3.6
5.5
-
Unit
V
VCC
VI
supply voltage
2.7
-
-
-
-
-
-
-
input voltage
0
V
VIH
VIL
IOH
IOL
HIGH-state input voltage
LOW-state input voltage
HIGH-state output current
2.0
V
-
-
-
-
0.8
−32
32
V
mA
mA
mA
LOW-state output current none
current duty cycle ≤ 50 %;
f ≥ 1 kHz
64
∆t/∆V
input transition rise and
fall rate
0
-
-
10
ns/V
Tamb
ambient temperature
in free air
−40
+85
°C
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
5 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIK
input clamping voltage
IIK = −18 mA; VCC = 2.7 V
IOH = −100 µA;
-
−0.9
−1.2
V
V
VOH
HIGH-state output voltage
VCC − 0.2 VCC − 0.1 -
VCC = 2.7 V to 3.6 V
IOH = −8 mA; VCC = 2.7 V
IOH = −32 mA; VCC = 3.0 V
VCC = 2.7 V
2.4
2.0
2.5
2.2
-
-
V
V
VOL
LOW-state output voltage
IOL = 100 µA
-
-
0.1
0.3
0.2
0.5
V
V
IOL = 24 mA
VCC = 3.0 V
IOL = 16 mA
-
-
-
0.25
0.3
0.4
V
V
V
IOL = 32 mA
0.5
IOL = 64 mA
0.4
0.55
ILI
input leakage current
all input pins
control pins
VCC = 0 V or 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = VCC or GND
VCC = 3.6 V
-
-
1
10
µA
µA
±0.1
±1
[2]
[3]
data pins
VI = VCC
-
-
-
0.1
−1
1
1
µA
µA
µA
VI = 0 V
−5
IOFF
power-off leakage current
bus hold current data input
VCC = 0 V; VI or VO = 0 V to 4.5 V
VCC = 3 V
±100
IHOLD
VI = 0.8 V
75
150
-
-
µA
µA
VI = 2.0 V
−75
−150
VCC = 0 V to 3.6 V
VI = 3.6 V
±500
-
-
µA
µA
IEX
external current into output
output in HIGH-state when
VO > VCC; VO = 5.5 V and
-
60
125
VCC = 3.0 V
[4]
IO(pu/pd) power-up/power-down output
current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
±1
±100
µA
VI = GND or VCC
;
nOE = don’t care
IOZ
OFF-state output current
VCC = 3.6 V; VI = VIH or VIL
output HIGH: VO = 3.0 V
output LOW: VO = 0.5 V
-
-
1
5
µA
µA
−1
−5
ICC
quiescent supply current
VCC = 3.6 V; VI = GND or VCC
IO = 0 A
;
outputs HIGH
outputs LOW
outputs disabled
-
-
-
0.13
2
0.19
7
mA
mA
mA
[5]
0.13
0.19
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
6 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[6]
∆ICC
additional quiescent supply
current
per input pin; VCC = 3 V to 3.6 V;
one input at VCC − 0.6 V and
other inputs at VCC or GND
-
0.1
0.2
mA
Ci
input capacitance
output capacitance
VI = 0 V or 3.0 V
-
-
4
8
-
-
pF
pF
Co
outputs disabled;
VO = 0 V or 3.0 V
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
[2] Unused pins at VCC or GND.
[3] This is the bus hold overdrive current required to force the input to the opposite logic state.
[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.0 V to
3.6 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[5] ICC is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
LOW-to-HIGH propagation delay nAn to nY see Figure 6
VCC = 2.7 V
-
-
4.5
4.0
ns
ns
VCC = 3.0 V to 3.6 V
1.0
2.7
HIGH-to-LOW propagation delay nAn to nY see Figure 6
VCC = 2.7 V
-
-
4.9
3.9
ns
ns
VCC = 3.0 V to 3.6 V
see Figure 7
1.0
2.9
output enable time nOE to nY
output enable time nOE to nY
output disable time nOE to nY
output disable time nOE to nY
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
-
-
6.0
4.7
ns
ns
1.0
3.4
VCC = 2.7 V
-
-
6.5
4.7
ns
ns
VCC = 3.0 V to 3.6 V
see Figure 7
1.1
3.4
VCC = 2.7 V
-
-
5.7
5.1
ns
ns
VCC = 3.0 V to 3.6 V
see Figure 7
1.8
3.7
VCC = 2.7 V
-
-
4.0
4.5
ns
ns
VCC = 3.0 V to 3.6 V
1.3
2.6
[1] Typical values are at VCC = 3.3 V and Tamb = 25 °C.
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
7 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
12. Waveforms
V
I
nA input
V
M
V
M
GND
t
t
PLH
PHL
V
OH
V
V
M
nY output
M
V
OL
mnb072
VM = 1.5 V.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Propagation delay input (nA) to output (nY)
V
I
nOE input
nY output
nY output
V
M
t
GND
t
PZL
PLZ
V
CC
V
V
M
M
V
+ 0.3 V
OL
V
OL
t
t
PHZ
PZH
V
OH
V
− 0.3 V
OH
0 V
001aac475
VM = 1.5 V.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. Enable and disable times of 3-state outputs
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
8 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 8. Load circuitry for switching times
Table 9.
Input
VI
Test data
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH tPLZ, tPZL tPLH, tPHL
2.7 V
≤ 10 MHz 500 ns
≤ 2.5 ns 50 pF
500 Ω
GND
6 V
open
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
9 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
13. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 9. Package outline SOT108-1 (SO14)
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
10 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 10. Package outline SOT337-1 (SSOP14)
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
11 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 11. Package outline SOT402-1 (TSSOP14)
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
12 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 12. Package outline SOT762-1 (DHVQFN14)
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
13 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Transistor-Transistor Logic
TTL
15. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVT_LVTH125_6 20060306
Product data sheet
-
74LVT125_5 (9397 750 14703)
Modifications:
• Section 4: Added type numbers 74LVTH125D, 74LVTH125DB, 74LVTH125PW and
74LVTH125BQ.
74LVT125_5
74LVT125_4
74LVT125_3
74LVT125_2
74LVT125_1
20050210
20050207
20040624
19980219
-
Product data sheet
Product data sheet
Product data sheet
Product specification
-
-
-
-
-
-
74LVT125_4 (9397 750 14552)
74LVT125_3 (9397 750 13535)
74LVT125_2 (9397 750 03514)
74LVT125_1
-
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
14 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
malfunction of a Philips Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is for the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
15 of 16
74LVT125; 74LVTH125
Philips Semiconductors
3.3 V quad buffer; 3-state
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.
Date of release: 6 March 2006
Document identifier: 74LVT_LVTH125_6
相关型号：
74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25ヘ Series Resistors in the Outputs
FAIRCHILD
74LVTH162240MEA
Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25ヘ Series Resistors in the Outputs
FAIRCHILD
74LVTH162240MEX
Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25ohm Series Resistors in the Outputs
FAIRCHILD
74LVTH162240MEX
Bus Driver, LVT Series, 4-Func, 4-Bit, Inverted Output, BICMOS, PDSO48, 0.300 INCH, MO-118, SSOP-48
ROCHESTER
74LVTH162240MTD
Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25ヘ Series Resistors in the Outputs
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明