74LVTH244ADB,118 [NXP]
74LVT(H)244A - 3.3 V octal buffer/line driver; 3-state SSOP2 20-Pin;
| 型号： | 74LVTH244ADB,118 |
| 厂家： | 
NXP |
| 描述： | 74LVT(H)244A - 3.3 V octal buffer/line driver; 3-state SSOP2 20-Pin 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
Rev. 04 — 3 September 2008
Product data sheet
1. General description
The 74LVT244A; 74LVTH244A is a high-performance BiCMOS product designed for VCC
operation at 3.3 V.
This device is an octal buffer that is ideal for driving bus lines. The device features two
output enables (1OE, 2OE), each controlling four of the 3-state outputs.
2. Features
I Octal bus interface
I 3-state buffers
I Output capability: +64 mA and −32 mA
I TTL input and output switching levels
I Input and output interface capability to systems at 5 V supply
I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
I Live insertion and extraction permitted
I Power-up 3-state
I No bus current loading when output is tied to 5 V bus
I Latch-up protection
N JESD78 Class II exceeds 500 mA
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT244AD
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVTH244AD
74LVT244ADB
74LVTH244ADB
74LVT244APW
74LVTH244APW
74LVT244ABQ
74LVTH244ABQ
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1
very thin quad flat package; no leads;
20 terminals; body 2.5 × 4.5 × 0.85 mm
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
4. Functional diagram
1Y0
1A0
1A1
1A2
2
4
6
18
16
14
12
1Y1
1Y2
1Y3
1
EN
18
2
1A3
16
14
12
4
6
8
8
1
1OE
2Y0
2Y1
2Y2
2Y3
2A0
2A1
2A2
11
13
15
9
7
5
3
19
11
EN
9
7
5
3
13
15
17
2A3
17
19
mna826
2OE
mna825
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
2 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
74LVT244A
74LVTH244A
terminal 1
index area
74LVT244A
74LVTH244A
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1A0
2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0
2OE
1Y0
2A3
1Y1
2A2
1Y2
2A1
1Y3
1
2
20
19
18
17
16
15
14
13
12
11
1OE
1A0
2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0
GND
V
CC
2OE
1Y0
2A3
1Y1
2A2
1Y2
2A1
1Y3
2A0
3
4
5
6
(1)
GND
7
8
9
001aah764
10
001aae510
Transparent top view
(1) The die substrate is attached to this pad using a
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 3. Pin configuration for SO20 and (T)SSOP20
Fig 4. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
Pin description
Pin
Description
1, 19
output enable input (active low)
data input
1A0, 1A1, 1A2, 1A3
2Y0, 2Y1, 2Y2, 2Y3
GND
2, 4, 6, 8
9, 7, 5, 3
10
data output
ground (0 V)
2A0, 2A1, 2A2, 2A3
11, 13, 15, 17 data input
1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output
VCC
20
supply voltage
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
3 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
6. Functional description
6.1 Function table
Table 3.
Control
nOE
Function table [1]
Input
nAn
L
Output
nYn
L
L
H
H
H
X
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+4.6
+7.0
+7.0
Unit
V
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
IIK
IOK
IO
input clamping current
output clamping current
output current
VI < 0 V
-
−50
−50
128
−64
+150
150
500
mA
mA
mA
mA
°C
VO < 0 V
-
output in LOW-state
output in HIGH-state
-
-
Tstg
Tj
storage temperature
junction temperature
total power dissipation
−65
[2]
[3]
-
°C
Ptot
Tamb = −40 to +85 °C
mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Operating conditions
Symbol Parameter
Conditions
Min
2.7
0
Typ
Max
3.6
Unit
V
VCC
VI
supply voltage
-
-
-
input voltage
5.5
V
IOH
HIGH-level output current
-
−32
mA
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
4 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
Table 5.
Operating conditions …continued
Symbol Parameter
Conditions
Min
Typ
Max
32
Unit
mA
mA
°C
IOL
LOW-level output current
none
-
-
-
-
-
current duty cycle ≤ 50 %; fi ≥ 1 kHz
-
64
Tamb
ambient temperature
in free-air
−40
+85
10
∆t/∆V
input transition rise and fall rate outputs enabled
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max Unit
Tamb = −40 °C to +85 °C [1]
VIK
VIH
VIL
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
VCC = 2.7 V; IIK = −18 mA
−1.2
2.0
-
−0.9
-
-
V
V
V
V
V
V
V
V
V
V
V
-
-
0.8
-
VOH
VCC = 2.7 V to 3.6 V; IOH = −100 µA
VCC = 2.7 V to 3.6 V; IOH = −8 mA
VCC = 3.0 V; IOH = −32 mA
VCC = 2.7 V; IOL = 100 µA
VCC = 2.7 V; IOL = 24 mA
VCC = 3.0 V; IOL = 16 mA
VCC = 3.0 V; IOL = 32 mA
VCC = 3.0 V; IOL = 64 mA
all input pins
VCC − 0.2 VCC − 0.1
2.4
2.5
2.2
0.1
0.3
0.25
0.3
0.4
-
2.0
-
VOL
LOW-level output voltage
input leakage current
-
-
-
-
-
0.2
0.5
0.4
0.5
0.55
II
VCC = 0 V or 3.6 V; VI = 5.5 V
control pins
-
-
0.1
10
µA
µA
VCC = 3.6 V; VI = VCC or GND
data pins
±0.1
±1
[2]
[3]
VCC = 3.6 V; VI = VCC
VCC = 3.6 V; VI = 0 V
-
−5
-
0.1
−1
1
µA
µA
−
IOFF
IBHL
IBHH
IBHLO
power-off leakage current
bus hold LOW current
bus hold HIGH current
VCC = 0 V; VI or VO = 0 V to 4.5 V
VCC = 3 V; VI = 0.8 V
1
±100 µA
µA
−75 µA
µA
75
−
150
−150
-
-
VCC = 3 V; VI = 2.0 V
bus hold LOW
nAn input;
500
-
overdrive current
V
CC = 0 V to 3.6 V; VI = 3.6 V
nAn input;
VCC = 0 V to 3.6 V; VI = 3.6 V
IBHHO
ILO
bus hold HIGH
overdrive current
-
-
-
-
−500 µA
125 µA
±100 µA
output leakage current
nYn output in HIGH-state when
VO > VCC; VO = 5.5 V; VCC = 3.0 V
60
±1
[4]
IO(pu/pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC;
VI = GND or VCC; nOE = don’t care
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
5 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
IOZ OFF-state output current
Conditions
Min
Typ
Max Unit
VCC = 3.6 V; VI = VIH or VIL
VO = 3.0 V
-
1
5
µA
µA
VO = 0.5 V
−5
−1
−
ICC
supply current
VCC = 3.6 V; VI = GND or VCC
IO = 0 A
;
output HIGH
output LOW
-
-
-
-
0.13
3
0.19 mA
12 mA
0.19 mA
[5]
[6]
outputs disabled
0.13
0.1
∆ICC
additional supply current
per input pin; VCC = 3.0 V to 3.6 V;
one input at VCC − 0.6 V and other
inputs at VCC or GND
0.2
mA
CI
input capacitance
output capacitance
VI = 0 V or 3.0 V
-
-
4
8
-
-
pF
pF
CO
outputs disabled; VO = 0 V or 3.0 V
[1] All typical values are at Tamb = 25 °C.
[2] Unused pins at VCC or GND.
[3] This is the bus hold overdrive current required to force the input to the opposite logic state.
[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[5] ICC is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C [1]
tPLH
tPHL
tPZH
tPZL
tPHZ
LOW to HIGH
propagation delay
nAn to nYn; see Figure 5
VCC = 2.7 V
-
-
5.0
4.1
ns
ns
VCC = 3.0 V to 3.6 V
nAn to nYn; see Figure 5
VCC = 2.7 V
1
2.5
HIGH to LOW
propagation delay
-
-
5.1
4.1
ns
ns
VCC = 3.0 V to 3.6 V
see Figure 6
1
2.6
OFF-state to HIGH
propagation delay
VCC = 2.7 V
-
-
6.3
5.2
ns
ns
VCC = 3.0 V to 3.6 V
see Figure 6
1
3.2
OFF-state to LOW
propagation delay
VCC = 2.7 V
-
-
6.7
5.2
ns
ns
VCC = 3.0 V to 3.6 V
see Figure 6
1.1
3.1
HIGH to OFF-state
propagation delay
VCC = 2.7 V
-
-
6.3
5.6
ns
ns
VCC = 3.0 V to 3.6 V
1.9
3.3
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
6 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPLZ
LOW to OFF-state
propagation delay
see Figure 6
VCC = 2.7 V
-
-
5.6
5.1
ns
ns
VCC = 3.0 V to 3.6 V
1.8
3.3
[1] All typical values are at VCC = 3.3 V and Tamb = 25 °C.
11. Waveforms
V
I
nAn input
GND
V
M
V
M
t
t
PLH
PHL
V
OH
V
V
M
nYn output
M
V
OL
mna171
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay input (nAn) to output (nYn) propagation delays
V
I
nOE input
nYn output
nYn output
V
M
t
GND
3.0 V
t
PZL
PLZ
V
V
M
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
0 V
001aae464
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. 3-state output enable and disable times
Table 8.
Input
VM
Measurement points
Output
VM
VX
VY
VOH − 0.3 V
1.5 V
1.5 V
VOL + 0.3 V
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
7 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
DD
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aai546
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 7. Load circuitry for switching times
Table 9.
Input
VI
Test data
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
2.7 V
≤ 10 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
6 V
open
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
8 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 8. Package outline SOT163-1 (SO20)
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
9 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 9. Package outline SOT339-1 (SSOP20)
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
10 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 10. Package outline SOT360-1 (TSSOP20)
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
11 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 11. Package outline SOT764-1 (DHVQFN20)
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
12 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
DUT
Description
BIpolar Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVT_LVTH244A_4 20080903
Product data sheet
-
74LVT_LVTH244A_3
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3 “Ordering information” and Section 12 “Package outline” DHVQFN20 package
added.
74LVT_LVTH244A_3 20060315
Product specification
Product specification
-
-
74LVT244A_2
74LVT244A_1
74LVT244A_2
19980219
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
13 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT_LVTH244A_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 3 September 2008
14 of 15
74LVT244A; 74LVTH244A
NXP Semiconductors
3.3 V octal buffer/line driver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 September 2008
Document identifier: 74LVT_LVTH244A_4
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