74LVTH322245EC [NXP]
3.3 V 32-bit bus transceiver with 30 W termination resistors; 3-state; 3.3伏的32位总线收发器和30瓦的终端电阻;三态
| 型号： | 74LVTH322245EC |
| 厂家： | 
NXP |
| 描述： | 3.3 V 32-bit bus transceiver with 30 W termination resistors; 3-state |
| 文件： | 总12页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVTH322245
3.3 V 32-bit bus transceiver with 30 Ω termination resistors;
3-state
Rev. 01 — 24 January 2007
Product data sheet
1. General description
The 74LVTH322245 is a high-performance BiCMOS product designed for VCC operation
at 3.3 V. The 74LVTH322245 is designed with 30 Ω series resistance in both the HIGH
and LOW states of the output. This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus receivers/transmitters. The
74LVTH322245 is a 32-bit transceiver featuring non-inverting 3-state bus compatible
outputs in both send and receive directions. The device features four output enable (nOE)
inputs for easy cascading and four send/receive (nDIR) inputs for direction control.
Pin nOE controls the outputs so that the buses are effectively isolated. Bus hold on data
inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features
I 32-bit bidirectional bus interface
I 3-state buffers
I Output capability: +12 mA and −12 mA
I TTL input and output switching levels
I Input and output interface capability to systems at 5 V supply
I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
I Live insertion and extraction permitted
I Outputs include series resistance of 30 Ω making external resistors unnecessary
I Power-up 3-state
I No bus current loading when output is tied to 5 V bus
I Latch-up protection:
N JESD78 Class II level A exceeds 500 mA
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVTH322245EC −40 °C to +125 °C
LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
4. Functional diagram
2DIR
H3
1DIR
A3
1OE
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2OE
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
A4
A2
A1
B2
B1
C2
C1
D2
D1
H4
E2
E1
F2
F1
G2
G1
H1
H2
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1A0
A5
E5
E6
F5
F6
G5
G6
H6
H5
1A1
A6
1A2
B5
1A3
B6
1A4
C5
1A5
C6
1A6
D5
1A7
D6
3DIR
J3
4DIR
T3
3OE
3B0
3B1
3B2
3B3
3B4
3B5
3B6
3B7
4OE
4B0
4B1
4B2
4B3
4B4
4B5
4B6
J4
T4
N2
N1
P2
P1
R2
R1
T1
T2
3A0
J5
4A0
4A1
4A2
4A3
4A4
4A5
4A6
4A7
N5
N6
P5
P6
R5
R6
T6
T5
J2
3A1
J6
J1
3A2
K5
K2
K1
L2
L1
M2
M1
3A3
K6
3A4
L5
3A5
L6
3A6
M5
3A7
M6
4B7
mna476
Fig 1. Logic symbol
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
2 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
V
CC
27 Ω
V
CC
output
27 Ω
data
input
to internal circuit
mna473
001aah684
Fig 2. Schematic of each output
Fig 3. Bus hold circuit
5. Pinning information
5.1 Pinning
mna475
6
5
4
3
2
1
1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A6 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A6
1A0 1A2 1A4 1A6 2A0 2A2 2A4 2A7 3A0 3A2 3A4 3A6 4A0 4A2 4A4 4A7
1OE GND
1DIR GND
V
V
GND GND
GND GND
V
V
GND 2OE 3OE GND
GND 2DIR 3DIR GND
V
V
GND GND
GND GND
V
V
GND 4OE
GND 4DIR
CC
CC
CC
CC
CC
CC
CC
CC
1B0 1B2 1B4 1B6 2B0 2B2 2B4 2B7 3B0 3B2 3B4 3B6 4B0 4B2 4B4 4B7
1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B6 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Ball
Description
nDIR (n = 1 to 4)
nOE (n = 1 to 4)
1A[0:7]
A3, H3, J3, T3
A4, H4, J4, T4
direction control
output enable input (active LOW)
input or output
A5, A6, B5, B6, C5, C6, D5, D6
A2, A1, B2, B1, C2, C1, D2, D1
E5, E6, F5, F6, G5, G6, H6, H5
E2, E1, F2, F1, G2, G1, H1, H2
J5, J6, K5, K6, L5, L6, M5, M6
J2, J1, K2, K1, L2, L1, M2, M1
1B[0:7]
input or output
2A[0:7]
input or output
2B[0:7]
input or output
3A[0:7]
input or output
3B[0:7]
input or output
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
3 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
Table 2.
Symbol
4A[0:7]
4B[0:7]
GND
Pin description …continued
Ball
Description
N5, N6, P5, P6, R5, R6, T6, T5
N2, N1, P2, P1, R2, R1, T1, T2
input or output
input or output
B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V)
M3, M4, N3, N4, R3, R4
VCC
C3, C4, F3, F4, L3, L4, P3, P4
supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
nOE
L
Input/output
nAn
nDIR
nBn
L
nAn = nBn
inputs
inputs
L
H
X
nBn = nAn
Z
H
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)[1][2]
Symbol Parameter
Conditions
Min
−0.5
−0.5
−0.5
−50
−50
-
Max
+4.6
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
[3]
[3]
input voltage
V
VO
IIK
output voltage
output in OFF or HIGH-state
VI < 0 V
V
input clamping current
output clamping current
output current
mA
mA
mA
mA
°C
°C
IOK
IO
VO < 0 V
-
output in LOW-state
output in HIGH-state
128
-
−64
−65
-
Tstg
Tj
storage temperature
junction temperature
+150
150
[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond indicated under Section 8 “Recommended operating conditions” is not implied. Exposure
to absolute-maximum-rated conditions for extended periods may affect device reliability.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
4 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
2.7
0
Typ
Max
3.6
5.5
-
Unit
V
VCC
VI
supply voltage
-
-
-
-
-
-
-
input voltage
V
IOH
HIGH-level output current
LOW-level output current
ambient temperature
−12
-
mA
mA
°C
IOL
12
Tamb
∆t/∆V
Ptot
in free air
−40
-
+85
10
input transition rise and fall rate outputs enabled
total power dissipation
ns/V
mW
[1]
-
1000
[1] Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIK
VIH
VIL
VOH
VOL
II
input clamping voltage
VCC = 2.7 V; IIK = −18 mA
−1.2
2.0
-
−0.85
-
V
V
V
V
V
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
input leakage current
-
-
-
0.8
-
VCC = 3.0 V; IOH = −12 mA
VCC = 3.0 V; IOL = 12 mA
control pins
2.0
-
2.5
0.3
0.8
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
input/output data pins; VCC = 3.6 V
VI = VCC
-
-
0.1
0.1
±1
µA
µA
10
[2]
-
0.5
−0.1
0.1
75
10
µA
µA
µA
µA
µA
VI = 0 V
−5
-
-
IOFF
ILO
power-off leakage current
output leakage current
VCC = 0 V; VI or VO = 0 V to 4.5 V
output HIGH; VO = 5.5 V; VCC = 3.0 V
±100
125
±100
-
[4]
IO(pu/pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
40
VI = GND or VCC; nOE = don’t care
IBHL
bus hold LOW current
bus hold HIGH current
VCC = 3 V; VI = 0.8 V
75
-
135
−135
-
-
µA
µA
µA
IBHH
IBHLO
VCC = 3 V; VI = 2.0 V
−75
[3]
[3]
bus hold LOW overdrive
current
VCC = 0 V to 3.6 V; VI = 3.6 V
500
-
IBHHO
ICC
bus hold HIGH overdrive
current
VCC = 0 V to 3.6 V; VI = 3.6 V
-
-
−500
µA
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH
-
-
-
0.14
8.4
0.24
12
mA
mA
mA
outputs LOW
[5]
outputs disabled
0.14
0.24
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
5 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[6]
∆ICC
additional supply current
per input pin; VCC = 3 V to 3.6 V;
one input at VCC − 0.6 V; other inputs
at VCC or GND
-
0.1
0.2
mA
CI
input capacitance
control pins; VO = 0 V or 3.0 V
-
-
3
9
-
-
pF
pF
CI/O
input/output capacitance
input/output data pins; outputs
disabled; VCC = 3.6 V; IO = 0 A;
VI = GND or VCC
[1] All typical values are at VCC = 3.3 V and Tamb = 25 °C unless otherwise specified.
[2] Unused pins at VCC or GND.
[3] This is the bus-hold overdrive current required to force the input to the opposite logic state.
[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[5] ICC is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 7.
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
Tamb = −40 °C to +85 °C
tPLH
LOW to HIGH propagation delay
nAn to nBn or nBn to nAn;
see Figure 5
VCC = 2.7 V
-
-
3.9
3.5
ns
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
tPHL
HIGH to LOW propagation delay
nAn to nBn or nBn to nAn;
see Figure 5
VCC = 2.7 V
-
-
3.9
3.5
ns
ns
VCC = 3.0 V to 3.6 V
1.0
2.2
tPZH
tPZL
tPHZ
tPLZ
OFF-state to HIGH propagation delay nOE to nAn or nBn; see Figure 6
VCC = 2.7 V
-
-
6.4
5.3
ns
ns
VCC = 3.0 V to 3.6 V
1.5
3.5
OFF-state to LOW propagation delay nOE to nAn or nBn; see Figure 6
VCC = 2.7 V
-
-
5.0
4.4
ns
ns
VCC = 3.0 V to 3.6 V
1.5
3.2
HIGH to OFF-state propagation delay nOE to nAn or nBn; see Figure 6
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
-
-
5.1
4.8
ns
ns
1.5
3.5
LOW to OFF-state propagation delay nOE to nAn or nBn; see Figure 6
VCC = 2.7 V
-
-
5.9
6.7
ns
ns
VCC = 3.0 V to 3.6 V
1.5
4.3
[1] All typical values are at VCC = 3.3 V and Tamb = 25 °C.
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
6 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
11. Waveforms
V
I
nAn, nBn
input
V
M
GND
t
t
PHL
PLH
V
OH
nBn, nAn
output
V
M
mna477
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Input to output propagation delays
V
I
V
nOE input
M
GND
3.0 V
t
t
PZL
PLZ
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aah683
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. enable and disable times
Table 8. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VOL + 0.3 V
VY
OH − 0.3 V
2.7 V to 3.6 V
1.5 V
1.5 V
V
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
7 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
t
W
V
I
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
Table 9.
Input
VI
Test data
VEXT
Load
RL
fi
tW
tr, tf
CL
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
2.7 V
≤ 10 MHz
500 ns
≤ 2.5 ns
500 Ω
50 pF
6 V
open
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
8 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2 e
y
y
v M
w M
C
C
A B
C
1
e
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2 e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
Fig 8. Package outline SOT536-1 (LFBGA96)
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
9 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
DUT
Description
Bipolar Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20080124
Data sheet status
Change notice
Supersedes
74LVTH322245_1
Product data sheet
-
-
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
10 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVTH322245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 24 January 2007
11 of 12
74LVTH322245
NXP Semiconductors
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 January 2007
Document identifier: 74LVTH322245_1
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