74LVU04BQ,115 [NXP]
74LVU04 - Hex inverter QFN 14-Pin;
| 型号： | 74LVU04BQ,115 |
| 厂家： | 
NXP |
| 描述： | 74LVU04 - Hex inverter QFN 14-Pin 栅 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVU04
Hex unbuffered inverter
Rev. 7 — 18 September 2014
Product data sheet
1. General description
The 74LVU04 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HCU04.
The 74LVU04 is a general purpose hex inverter. Each of the six inverters is a single stage
with unbuffered outputs.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Linear amplifier
Crystal oscillator
Astable multivibrator
74LVU04
NXP Semiconductors
Hex unbuffered inverter
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVU04N
74LVU04D
40 C to +125 C
40 C to +125 C
DIP14
SO14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVU04DB
74LVU04PW
74LVU04BQ
40 C to +125 C
40 C to +125 C
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
SOT402-1
SOT762-1
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
5. Functional diagram
ꢀ
ꢀ
ꢂ
ꢁ
ꢀ<
ꢁ<
ꢂ<
ꢃ<
ꢄ<
ꢅ<
ꢀ
ꢀ
ꢀ$
ꢁ$
ꢂ$
ꢃ$
ꢄ$
ꢅ$
ꢁ
ꢃ
ꢀ
ꢂ
ꢃ
ꢄ
ꢅ
ꢅ
ꢄ
ꢀ
ꢀ
ꢀ
ꢆ
ꢇ
V
V
V
CC
CC
CC
ꢇ
ꢆ
ꢀꢀ
ꢀꢂ
ꢀꢈ
ꢀꢁ
ꢀꢀ
ꢀꢂ
ꢀꢈ
ꢀꢁ
100 Ω
170 Ω
nA
nY
001aah110
PQDꢀꢁꢂ
PQDꢀꢁꢀ
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Circuit diagram (one
inverter)
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
2 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
6. Pinning information
6.1 Pinning
74LVU04
terminal 1
index area
74LVU04
2
3
4
5
6
13
12
11
10
9
1Y
6A
6Y
5A
5Y
4A
1
2
3
4
5
6
7
14
13
12
11
10
9
2A
2Y
3A
3Y
1A
1Y
V
CC
6A
6Y
5A
5Y
4A
4Y
2A
(1)
CC
V
2Y
3A
3Y
001aah109
GND
8
Transparent top view
001aah108
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC
.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Symbol
1A
Pin description
Pin
1
Description
data input
1Y
2
data output
data input
2A
3
2Y
4
data output
data input
3A
5
3Y
6
data output
ground (0 V)
data output
data input
GND
4Y
7
8
4A
9
5Y
10
11
12
13
14
data output
data input
5A
6Y
data output
data input
6A
VCC
supply voltage
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
3 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
7. Functional description
Table 3.
Function table[1]
Input nA
Output nY
L
H
L
H
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
20
50
25
50
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
+150
Tamb = 40 C to +125 C
DIP14 package
[2]
[3]
[4]
[5]
-
-
-
-
750
500
500
500
mW
mW
mW
mW
SO14 package
(T)SSOP14 package
DHVQFN14 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70 C.
[3] Ptot derates linearly with 8 mW/K above 70 C.
[4]
Ptot derates linearly with 5.5 mW/K above 60 C.
[5] Ptot derates linearly with 4.5 mW/K above 60 C.
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
4 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
[1]
supply voltage
1.0
3.3
VI
input voltage
0
-
VCC
VCC
+125
500
200
100
50
V
VO
output voltage
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
+25
C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
10. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input voltage
VCC = 1.2 V
1.0
-
-
-
-
-
-
-
-
-
1.0
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.6
-
-
1.6
-
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.4
2.4
0.8VCC
-
0.8VCC
-
VIL
LOW-level input voltage
-
-
-
-
0.2
0.4
0.5
0.2VCC
-
-
-
-
0.2
0.4
0.5
0.2VCC
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.2 V
-
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
1.8
2.5
2.8
4.3
2.4
3.6
1.8
2.5
2.8
4.3
2.2
3.5
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
5 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.40
0.55
1.0
0.2
0.2
0.2
0.2
0.50
0.65
1.0
V
0
V
0
V
0
V
0.25
0.35
-
V
V
II
input leakage current
supply current
VI = VCC or GND;
VCC = 5.5 V
A
ICC
CI
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
20.0
-
-
-
40
-
A
input capacitance
3.5
pF
[1] Typical values are measured at Tamb = 25 C.
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1] Max
Min
Max
[2]
tpd
propagation delay nA, nB to nY; see Figure 6
VCC = 1.2 V
-
-
-
-
-
-
-
35
12
9
-
14
10
-
-
-
-
-
-
-
-
-
17
13
-
ns
ns
ns
ns
ns
ns
pF
VCC = 2.0 V
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
6
7
8
10
9
VCC = 4.5 V to 5.5 V
-
7
[4]
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
18
-
-
capacitance
VI = GND to VCC
[1] All typical values are measured at Tamb = 25 C.
[2] pd is the same as tPLH and tPHL
t
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
6 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
12. Waveforms
9
,
9
9
0
Q$ꢉLQSXW
0
*1'
W
W
3+/
3/+
9
2+
9
0
9
0
Q<ꢉRXWSXW
9
PQDꢀꢁꢁ
2/
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The input (nA) to output (nY) propagation delays
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
0.5VCC
2.7 V to 3.6 V
4.5 V
9
&&
9
9
2
,
38/6(ꢉ
*(1(5$725
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&
/ꢉ
ꢄꢈꢉS)
5
/ꢉ
ꢀꢉNȍ
5
7
ꢃꢃꢄDDDꢅꢅꢀ
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 7. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
VCC
Input
VI
tr, tf
< 2.7 V
VCC
2.7 V
VCC
2.5 ns
2.5 ns
2.5 ns
2.7 V to 3.6 V
4.5 V
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
7 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
13. Transfer characteristics
001aah111
001aah112
1.2
300
I
2.0
5
V
I
CC
O
(V)
V
O
(mA)
V
V
O
O
CC
(V)
(μA)
1.6
4
3
2
1
0
0.8
200
1.2
0.8
0.4
0
I
CC
I
CC
0.4
100
0
0
1.2
0
0.4
0.8
0
0.4
0.8
1.2
1.6
2.0
V (V)
I
V (V)
I
Tamb = 25 C.
Tamb = 25 C.
Fig 8. VCC = 1.2 V; IO = 0 A
Fig 9. VCC = 2.0 V; IO = 0 A
001aah113
3.0
18
V
O
I
CC
(V)
(mA)
V
O
2.0
12
5
ELDV
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I
CC
9
&&
1.0
6
ꢈꢊꢃꢋꢉ)
ꢀꢈꢈꢉ)
LQSXW
RXWSXW
9
,
$
,
2
ꢌIꢉ ꢉꢀꢉN+]ꢍ
0
0
3.0
0
1.0
2.0
*1'
PQDꢃꢆꢃ
V (V)
I
Tamb = 25 C.
IO
--------
VI
gfs
=
fi = 1 kHz at VO is constant
Fig 10. VCC = 3.0 V; IO = 0 A
Fig 11. Test set-up for measuring forward
transconductance
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
8 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
001aah114
40
g
fs
(mA/V)
30
20
10
0
0
1
2
3
4
V
CC
(V)
Tamb = 25 C.
Fig 12. Forward transconductance as a function of the supply voltage
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
9 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
14. Application information
Some applications are:
• Linear amplifier (see Figure 13)
• In crystal oscillator design (see Figure 14)
• Astable multivibrator (see Figure 15)
Remark: All values given are typical unless otherwise specified.
5ꢁ
5ꢀ
9
&&
5ꢁ
ꢀꢉ)
5ꢀ
8ꢈꢃ
8ꢈꢃ
&ꢀ
&ꢁ
=
/
RXW
PQDꢃꢆꢂ
PQDꢃꢆꢀ
Maximum Vo(p-p) = VCC 1.5 V centered at 0.5VCC
.
C1 = 47 pF (typical)
C2 = 22 pF (typical)
Gol
Gv = –
---------------------------------------
1 +
R1 = 1 M to 10 M (typical)
R1
------
1 + Gol
R2 optimum value depends on the frequency and
required stability against changes in VCC or average
minimum ICC (ICC is typically 2 mA at VCC = 3 V and
fi = 1 MHz).
R2
G
ol = open loop gain
Gv = voltage gain
See Table 10 and Table 11
CI, see Figure 16
R1 3 k, R2 1 M
ZL > 10 k; Gol = 20 (typical)
Typical unity gain bandwidth product is 5 MHz.
Fig 13. Linear amplifier
Fig 14. Crystal oscillator
Table 10. External components for oscillator (f < 1 MHz)
All values given are typical and must be used as an initial set-up.
Frequency
R1
R2
C1
C2
10 kHz to 15.9 kHz
16 kHz to 24.9 kHz
25 kHz to 54.9 kHz
55 kHz to 129.9 kHz
130 kHz to 199.9 kHz
200 kHz to 349.9 kHz
350 kHz to 600 kHz
2.2 M
2.2 M
2.2 M
2.2 M
2.2 M
2.2 M
2.2 M
220 k
220 k
100 k
100 k
47 k
47 k
47 k
56 pF
56 pF
56 pF
47 pF
47 pF
47 pF
47 pF
20 pF
10 pF
10 pF
5 pF
5 pF
5 pF
5 pF
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
10 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
Table 11. Optimum value for R2
Frequency
R2
Optimum for
3 kHz
2.0 k
8.0 k
1.0 k
4.7 k
0.5 k
2.0 k
0.5 k
1.0 k
-
minimum required ICC
minimum influence due to change in VCC
minimum required ICC
6 kHz
minimum influence due to change in VCC
minimum required ICC
10 kHz
14 kHz
>14 kHz
minimum influence due to change in VCC
minimum required ICC
minimum influence due to change in VCC
replace R2 by C3 with a typical value of 35 pF
001aah116
80
input
capacitance
(pF)
60
(1)
40
(2)
(3)
20
U04
U04
R
S
R
C
0
0
1
2
3
input voltage (V)
001aah115
V
V
CC = 1.2 V
CC = 2.0 V
1
T
1
-- ---------------
f =
2.2RC
VCC = 3.0 V
RS 2 R
The average ICC (mA) is approximately
Tamb = 25 C.
3.5 + 0.05 x f (MHz) x C (pF) at VCC = 3.0 V.
Fig 15. Astable multivibrator
Fig 16. Input capacitance as function of input voltage
74LVU04
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
11 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
15. Package outline
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Fig 17. Package outline SOT27-1 (DIP14)
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
12 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
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Fig 18. Package outline SOT108-1 (SO14)
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
13 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
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Fig 19. Package outline SOT337-1 (SSOP14)
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
14 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
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Fig 20. Package outline SOT402-1 (TSSOP14)
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
15 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
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Fig 21. Package outline SOT762-1 (DHVQFN14)
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
16 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
16. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 13. Revision history
Document ID
74LVU04 v.7
Modifications:
74LVU04 v.6
74LVU04 v.5
74LVU04 v.4
74LVU04 v.3
74LVU04 v.1
Release date
20140918
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVU04 v.6
• Descriptive title changed to Hex unbuffered inverter.
20071220
20010111
20001218
19980420
19970212
Product data sheet
Product specification
Product specification
Product specification
Product specification
-
-
-
-
-
74LVU04 v.5
74LVU04 v.4
74LVU04 v.3
74LVU04 v.1
-
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
17 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
18.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
18 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
19 of 20
74LVU04
NXP Semiconductors
Hex unbuffered inverter
20. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Transfer characteristics . . . . . . . . . . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
8
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 September 2014
Document identifier: 74LVU04
相关型号：
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