83C751_技术文档

INTEGRATED CIRCUITS

83C752/87C752

80C51 8-bit microcontroller family

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM,

low pin count

Product specification

1998 May 01

Supersedes data of 1998 Jan 19

IC20 Data Handbook

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

DESCRIPTION

• Small package sizes

The Philips 83C752/87C752 offers many of the advantages of the

– 28-pin DIP

80C51 architecture in a small package and at low cost.

– 28-pin PLCC

The 8XC752 Microcontroller is fabricated with Philips high-density

CMOS technology. Philips epitaxial substrate minimizes CMOS

– 28-pin SSOP

• Wide oscillator frequency range

latch-up sensitivity.

• Low power consumption:

– Normal operation: less than 11mA @ 5V, 12MHz

The 8XC752 contains a 2k × 8 ROM (83C752) EPROM (87C752), a

64 × 8 RAM, 21 I/O lines, a 16-bit auto-reload counter/timer, a

fixed-priority level interrupt structure, a bidirectional inter-integrated

circuit (I C) serial bus interface, an on-chip oscillator, a five channel

multiplexed 8-bit A/D converter, and an 8-bit PWM output.

– Idle mode

2

– Power-down mode

• 2k × 8 ROM (83C752)

2

The onboard inter-integrated circuit (I C) bus interface allows the

EPROM (87C752)

2

8XC752 to operate as a master or slave device on the I C small

area network. This capability facilitates I/O and RAM expansion,

access to EEPROM, processor-to-processor communication, and

efficient interface to a wide variety of dedicated I C peripherals.

• 64 × 8 RAM

• 16-bit auto reloadable counter/timer

• 5-channel 8-bit A/D converter

• 8-bit PWM output/timer

• Fixed-rate timer

2

The EPROM version of this device, the 87C752, is available in both

quartz-lid erasable and plastic one-time programmable (OTP)

packages. Once the array has been programmed, it is functionally

equivalent to the masked ROM 83C752. Thus, unless explicitly

stated otherwise, all references made to the 83C752 apply equally

to the 87C752.

• Boolean processor

• CMOS and TTL compatible

The 83C752 supports two power reduction modes of operation

referred to as the idle mode and the power-down mode.

• Well suited for logic replacement, consumer and industrial

applications

FEATURES

• Available in erasable quartz lid or One-Time Programmable plastic

packages

• 80C51 based architecture

2

• Inter-integrated Circuit (I C) serial bus interface

PART NUMBER SELECTION

ROM

EPROM

TEMPERATURE RANGE °C

FREQUENCY

DRAWING

AND PACKAGE

NUMBER

SOT341-1

SOT117-2

SOT341-1

SOT117-2

SOT261-3

SOT117-2

S83C752–1DB

S87C752–1DB

OTP

0 to +70, 28-pin Plastic Shrink Small Outline Package

0 to +70, 28-pin Plastic Dual In-line Package

–40 to +85, 28-pin Plastic Dual In-line Package

0 to +70, 28-pin Plastic Shrink Small Outline Package

0 to +70, 28-pin Plastic Dual In-line Package

–40 to +85, 28-pin Plastic Dual In-line Package

0 to +70, 28-pin Plastic Leaded Chip Carrier

–40 to +85, 28-pin Plastic Leaded Chip Carrier

0 to +70, 28-pin Plastic Leaded Chip Carrier

–40 to +85, 28-pin Plastic Leaded Chip Carrier

–55 to +125, 28-pin Plastic Leaded Chip Carrier

–55 to +125, 28-pin Plastic Dual In-line Package

3.5 to 12MHz

3.5 to 16MHz

3.5 to 12MHz

3.5 to 16MHz

3.5 to 12MHz

S83C752–1N28 S87C752–1N28

S83C752–2N28 S87C752–2N28

S83C752–4DB

S87C752–4DB

S83C752–4N28 S87C752–4N28

S83C752–5N28 S87C752–5N28

S83C752–1A28 S87C752–1A28

S83C752–2A28 S87C752–2A28

S83C752–4A28 S87C752–4A28

S83C752–5A28 S87C752–5A28

S83C752–6A28 S87C752–6A28

S83C752–6N28 S87C752–6N28

NOTE:

1. OTP = One Time Programmable EPROM.

2

1998 May 01

853-1443 19328

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

BLOCK DIAGRAM

P0.0–P0.4

PORT 0

DRIVERS

V

2

CC

SS

I C

PWM

CONTROL

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

ROM/

EPROM

RAM

STACK

POINTER

B

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

PCON I2CFG I2STA TCON

ALU

I2DAT I2CON

IE

TH0

RTH

TL0

RTL

PC

INCRE-

MENTER

PSW

INTERRUPT, SERIAL

PORT AND TIMER BLOCKS

PROGRAM

COUNTER

TIMING

AND

RST

DPTR

CONTROL

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

ADC

X1

X2

AV

CC

P1.0–P1.7

SS

P3.0–P3.7

SU00319

3

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

PIN CONFIGURATIONS

P3.4/A4

V

28

27

26

25

1

2

CC

P3.5/A5

P3.6/A6

P3.7/A7

P3.3/A3

P3.2/A2/A10

3

4

5

P3.1/A1/A9

P3.0/A0/A8

24 P0.4/PWM OUT

23 P0.3

PLASTIC

DUAL

IN-LINE

PACKAGE

AND

SHRINK

SMALL

OUTLINE

6

7

8

P0.2/V

PP

22 P1.7/T0/D7

21 P1.6/INT1/D6

20 P1.5/INT0/D5

P0.1/SDA/OE–PGM

P0.0/SCL/ASEL

PACKAGE

RST

X2

9

19 AV

CC

10

11

12

18

AV

X1

SS

17 P1.4/ADC4/D4

V

SS

P1.0/ADC0/D0 13

P1.1/ADC1/D1 14

16 P1.3/ADC3/D3

15 P1.2/ADC2/D2

4

1

26

5

25

19

PLASTIC

LEADED

CHIP

CARRIER

11

12

18

1

2

3

4

5

6

7

8

Function

P3.4/A4

P3.3/A3

P3.2/A2/A10

P3.1/A1/A9

P3.0/A0/A8

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Function

P1.2/ADC2/D2

P1.3/ADC3/D3

P1.4/ADC4/D4

AV

SS

CC

P0.2/V

P1.5/INT0/D5

P1.6/INT1/D6

P1.7/T0/D7

P0.3

P0.4/PWM OUT

P3.7/A7

PP

P0.1/SDA/OE-PGM

P0.0/SCL/ASEL

RST

X2

X1

9

10

11

12

13

14

V

P3.6/A6

P3.5/A5

SS

P1.0/ADC0/D0

P1.1/ADC1/D1

V

CC

SU00318

4

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

PIN DESCRIPTION

MNEMONIC

PIN NO.

12

TYPE

NAME AND FUNCTION

V

I

Circuit Ground Potential.

Supply voltage during normal, idle, and power-down operation.

SS

CC

V

28

P0.0–P0.4

8–6

23, 24

I/O

Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0–P0.2 are open drain. Port 0.0–P0.2 pins that have

1s written to them float, and in that state can be used as high-impedance inputs. P0.3–P0.4 are

2

bidirectional I/O port pins with internal pull-ups. Port 0 also serves as the serial I C interface. When this

2

feature is activated by software, SCL and SDA are driven low in accordance with the I C protocol.

2

These pins are driven low if the port register bit is written with a 0 or if the I C subsystem presents a 0.

The state of the pin can always be read from the port register by the program. Port 0.3 and 0.4 have

internal pull-ups that function identically to port 3. Pins that have 1s written to them are pulled high by

the internal pull-ups and can be used as inputs.

2

To comply with the I C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the

electrical characteristics listed in the tables that follow. While these differ from “standard TTL”

characteristics, they are close enough for the pins to still be used as general-purpose I/O in non-I C

2

applications.

6

7

I

V

(P0.2) – Programming voltage input. (See Note 2.)

PP

OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.

OE/PGM = 1 output enabled (verify mode).

OE/PGM = 0 program mode.

8

I

ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.

ASEL = 0 low address byte available on port 3.

ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).

P1.0–P1.7

13–17,

20–22

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to

them are pulled high by the internal pull-ups and can be used as inputs. P0.3–P0.4 pins are

bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will

source current because of the internal pull-ups. (See DC Electrical Characteristics: I ). Port 1 also

IL

serves the special function features of the SC80C51 family as listed below:

20

21

22

I

INT0 (P1.5): External interrupt.

INT1 (P1.6): External interrupt.

T0 (P1.7): Timer 0 external input.

ADC0 (P1.0)–ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D

converter. These pins can be used as outputs only if the A/D function has been disabled. These pins

can be used as inputs while the A/D converter is enabled.

13–17

Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the

value to program into the selected address during the program mode.

P3.0–P3.7

RST

5–1,

27–25

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to

them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are

externally being pulled low will source current because of the pull-ups. (See DC Electrical

Characteristics: I ). Port 3 also functions as the address input for the EPROM memory location to be

IL

programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.

9

I

Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An

internal diffused resistor to V permits a power-on RESET using only an external capacitor to V

.

SS

CC

After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device

in the programming state allowing programming address, data and V to be applied for programming

PP

or verification purposes. The RESET serial sequence must be synchronized with the X1 input.

X1

11

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1

also serves as the clock to strobe in a serial bit stream into RESET to place the device in the

programming state.

X2

10

19

18

O

I

Crystal 2: Output from the inverting oscillator amplifier.

Analog supply voltage and reference input.

Analog supply and reference ground.

1

AV

CC

1

I

SS

NOTE:

1. AV (reference ground) must be connected to 0V (ground). AV (reference input) cannot differ from V by more than ±0.2V, and must be

SS

CC

in the range 4.5V to 5.5V.

2. When P0.2 is at or close to 0V, it may affect the internal ROM operation. We recommend that P0.2 be tied to V via a small pull-up

CC

(e.g., 2kΩ).

5

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

OSCILLATOR CHARACTERISTICS

DIFFERENCES BETWEEN THE 8XC752 AND

X1 and X2 are the input and output, respectively, of an inverting

amplifier which can be configured for use as an on-chip oscillator.

THE 80C51

Program Memory

To drive the device from an external clock source, X1 should be

driven while X2 is left unconnected. There are no requirements on

the duty cycle of the external clock signal, because the input to the

internal clock circuitry is through a divide-by-two flip-flop. However,

minimum and maximum high and low times specified in the data

sheet must be observed.

On the 8XC752, program memory is 2048 bytes long and is not

externally expandable, so the 80C51 instructions MOVX, LJMP, and

LCALL are not implemented. If these instructions are executed, the

appropriate number of instruction cycles will take place along with

external fetches; however, no operation will take place. The LJMP

may not respond to all program address bits. The only fixed

locations in program memory are the addresses at which execution

is taken up in response to reset and interrupts, which are as follows:

Program Memory

IDLE MODE

The 8XC752 includes the 80C51 power-down and idle mode

features. In idle mode, the CPU puts itself to sleep while all of the

on-chip peripherals except the A/D and PWM stay active. The

functions that continue to run while in the idle mode are Timer 0, the

Event

Reset

Address

000

003

00B

013

01B

023

02B

033

External INT0

Counter/timer 0

External INT1

Timer I

2

I C interface including Timer I, and the interrupts. The instruction to

invoke the idle mode is the last instruction executed in the normal

operating mode before the idle mode is activated. The CPU

contents, the on-chip RAM, and all of the special function registers

remain intact during this mode. The idle mode can be terminated

either by any enabled interrupt (at which time the process is picked

up at the interrupt service routine and continued), or by a hardware

reset which starts the processor in the same manner as a power-on

reset. Upon powering-up the circuit, or exiting from idle mode,

sufficient time must be allowed for stabilization of the internal analog

reference voltages before an A/D conversion is started.

2

I C serial

ADC

PWM

Memory Organization

The 8XC752 manipulates operands in three memory address

spaces. The first is the program memory space which contains

program instructions as well as constants such as look-up tables.

The program memory space contains 2k bytes in the 8XC752.

Special Function Registers

The second memory space is the data memory array which has a

logical address space of 128 bytes. However, only the first 64 (0 to

3FH) are implemented in the 8XC752.

The special function registers (directly addressable only) contain all

of the 8XC751 registers except the program counter and the four

register banks. Most of the 21 special function registers are used to

control the on-chip peripheral hardware. Other registers include

arithmetic registers (ACC, B, PSW), stack pointer (SP) and data

pointer registers (DPH, DPL). Nine of the SFRs are bit addressable.

The third memory space is the special function register array having

a 128-byte address space (80H to FFH). Only selected locations in

this memory space are used (see Table 2). Note that the

architecture of these memory spaces (internal program memory,

internal data memory, and special function registers) is identical to

the 80C51, and the 8XC752 varies only in the amount of memory

physically implemented.

Data Pointer

The data pointer (DPTR) consists of a high byte (DPH) and a low

byte (DPL). In the 80C51 this register allows the access of external

data memory using the MOVX instruction. Since the 83C752 does

not support MOVX or external memory accesses, this register is

generally used as a 16-bit offset pointer of the accumulator in a

MOVC instruction. DPTR may also be manipulated as two

independent 8-bit registers.

The 8XC752 does not directly address any external data or program

memory spaces. For this reason, the MOVX instructions in the

80C51 instruction set are not implemented in the 83C752, nor are

the alternate I/O pin functions RD and WR.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the instruction

to invoke power-down is the last instruction executed. Only the

contents of the on-chip RAM are preserved. A hardware reset is the

only way to terminate the power-down mode. The control bits for the

reduced power modes are in the special function register PCON.

Table 1. External Pin Status During Idle and

Power-Down Modes

MODE

Port 0*

Port 1

Port 2

Idle

Power-down

Data

*

Except for PWM output (P0.4).

6

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

ALTERNATE

OUTPUT

FUNCTION

ALTERNATE

OUTPUT

FUNCTION

READ

LATCH

READ

LATCH

V

DD

INTERNAL

PULL-UP

INT. BUS

D

Q

INT. BUS

D

Q

P1.X

LATCH

P0.X

LATCH

P1.X

P0.X

WRITE TO

LATCH

WRITE TO

LATCH

CL

READ

ALTERNATE INPUT

FUNCTION

ALTERNATE INPUT

FUNCTION

SU00306

Figure 1. Port Bit Latches and I/O Buffers

I/O Ports

Counter/Timer Subsystem

The I/O pins provided by the 83C752 consist of port 0, port 1, and

port 3.

The 8XC752 has one counter/timer called timer/counter 0. Its

operation is similar to mode 2 operation on the 80C51, but is

extended to 16 bits with 16 bits of autoload. The controls for this

counter are centralized in a single register called TCON.

Port 0

Port 0 is a 5-bit bidirectional I/O port and includes alternate functions

on some pins of this port. Pins P0.3 and P0.4 are provided with

internal pullups while the remaining pins (P0.0, P0.1, and P0.2) have

open drain output structures. The alternate functions for port 0 are:

2

A watchdog timer, called Timer I, is for use with the I C subsystem.

2

In I C applications, this timer is dedicated to time-generation and

bus monitoring of the I C. In non-I C applications, it is available for

use as a fixed time-base.

2

P0.0

P0.1

P0.4

SCL – the I C bus clock

2

Interrupt Subsystem—Fixed Priority

SDA – the I C bus data

The IP register and the 2-level interrupt system of the 80C51 are

eliminated. The interrupt structure is a seven-source, one-level

interrupt system similar to the 8XC751. Simultaneous interrupt

conditions are resolved by a single-level, fixed priority as follows:

PWM – the PWM output

2

If the alternate functions, I C and PWM, are not being used, then

these pins may be used as I/O ports.

Highest priority:

Pin INT0

Port 1

Counter/timer flag 0

Pin INT1

PWM

Port 1 is an 8-bit bidirectional I/O port whose structure is identical to

the 80C51, but also includes alternate input functions on all pins.

The alternate pin functions for port 1 are:

Timer I

Serial I C

2

P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs

P1.5 INT0 - external interrupt 0 input

P1.6 INT1 - external interrupt 1 input

P1.7 - T0 - timer 0 external input

Lowest priority:

ADC

The vector addresses are as follows:

Source

INT0

TF0

INT1

TIMER I

SIO

Vector Address

0003H

If the alternate functions INT0, INT1, or T0 are not being used, these

pins may be used as standard I/O ports. It is necessary to connect

000BH

0013H

001BH

0023H

002BH

0033H

AV and AV to V and V , respectively, in order to use these

CC

SS

CC

SS

pins as standard I/O pins. When the A/D converter is enabled, the

analog channel connected to the A/D may not be used as a digital

input; however, the remaining analog inputs may be used as digital

inputs. They may not be used as digital outputs. While the A/D is

enabled, the analog inputs are floating.

ADC

PWM

Interrupt Control Registers

Port 3

The 80C51 interrupt enable register is modified to take into account

the different interrupt sources of the 8XC752.

Port 3 is an 8-bit bidirectional I/O port whose structure is identical to

the 80C51. Note that the alternate functions associated with port 3

of the 80C51 have been moved to port 1 of the 83C752 (as

applicable). See Figure 1 for port bit configurations.

7

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

Interrupt Enable Register

Pulse Width Modulation Output (P0.4)

The PWM outputs pulses of programmable length and interval. The

repetition frequency is defined by an 8-bit prescaler which generates

the clock for the counter. The prescaler register is PWMP. The

prescaler and counter are not associated with any other timer. The

8-bit counter counts modulo 255, that is from 0 to 254 inclusive. The

value of the 8-bit counter is compared to the contents of a compare

register, PWM. When the counter value matches the contents of this

register, the output of the PWM is set high. When the counter reaches

zero, the output of the PWM is set low. The pulse width ratio (duty

cycle) is defined by the contents of the compare register and is in the

range of 0 to 1 programmed in increments of 1/255. The PWM output

can be set to be continuously high by loading the compare register

with 0 and the output can be set to be continuously low by loading the

compare register with 255. The PWM output is enabled by a bit in a

special function register, PWENA. When enabled, the pin output is

driven with a fully active pull-up. That is, when the output is high, a

strong pull-up is continuously applied. when disabled, the pin

functions as a normal bidirectional I/O pin, however, the counter

remains active.

MSB

EA

LSB

EX0

EAD

ETI

ES

EPWM

EX1

ET0

Position Symbol

Function

IE.7

IE.6

IE.5

IE.4

IE.3

IE.2

IE.1

IE.0

EA

EAD

ETI

Global interrupt disable when EA = 0

A/D conversion complete

Timer I

2

ES

I C serial port

EPWM

EX1

ET0

EX0

PWM counter overflow

External interrupt 1

Timer 0 overflow

External interrupt 0

Serial Communications

The 8XC752 contains an I C serial communications port instead of

the 80C51 UART. The I C serial port is a single bit hardware

interface with all of the hardware necessary to support multimaster

and slave operations. Also included are receiver digital filters and

timer (timer I) for communication watch-dog purposes. The I C

serial port is controlled through four special function registers; I C

control, I C data, I C status, and I C configuration.

2

The PWM function is disabled during RESET and remains disabled

after reset is removed until re-enabled by software. The PWM output

is high during power down and idle. The counter is disabled during

idle. The repetition frequency of the PWM is given by:

2

The I C bus uses two wires (SDA and SCL) to transfer information

between devices connected to the bus. The main technical features

of the bus are:

f

= f

/ 2 (1 + PWMP) 255

OSC

PWM

The low/high ratio of the PWM signal is PWM / (255 – PWM) for

PWM not equal to 255. For PWM = 255, the output is always low.

• Bidirectional data transfer between masters and slaves

• Serial addressing of slaves

The repetition frequency range is 92Hz to 23.5kHz for an oscillator

frequency of 12MHz.

• Acknowledgment after each transferred byte

• Multimaster bus

An interrupt will be asserted upon PWM counter overflow if the

interrupt is not masked off.

• Arbitration between simultaneously transmitting master without

The PWM output is an alternative function of P0.4. In order to use

this port as a bidirectional I/O port, the PWM output must be

disabled by clearing the enable/disable bit in PWENA. In this case,

the PWM subsystem can be used as an interval timer by enabling

the PWM interrupt.

corruption of serial data on bus

• With 82B715, communication distance is extended to beyond 100

feet (30M)

2

A large family of I C compatible ICs is available. See the I C section

for more details on the bus and available ICs.

2

The 83C752 I C subsystem includes hardware to simplify the

2

software required to drive the I C bus. This circuitry is the same as

that on the 83C751. (See the 83C751 section for a detailed

discussion of this subsystem).

8

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

Table 2.

8XC752 Special Function Registers

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

ADDRESS MSB

RESET

VALUE

SYMBOL

LSB

ACC*

Accumulator

A/D result

E0H

84H

A0H

F0H

E7

E6

E5

E4

E3

E2

E1

E0

00H

AADR2 AADR1 AADR0 C0H

ADAT#

ADCON# A/D control

–

ENADC

F5

ADCI

F4

ADCS

F3

B*

B register

F7

F6

F2

F1

F0

00H

DPTR:

Data pointer

(2 bytes)

DPL

DPH

Data pointer low

Data pointer high

82H

83H

00H

DF

DE

DD

0

DC

TIRUN

9C

DB

–

DA

–

D9

D8

CT0

98

2

SLAVEN MASTRQ

I CFG*#

I C configuration

D8H/RD

WR

CT1

0000xx00B

SLAVEN MASTRQ

CLRTI

9D

–

9F

RDAT

CXA

RDAT

XDAT

FF

9E

ATN

IDLE

0

9B

STR

CSTR

0

9A

STP

CSTP

0

99

2

MASTER

I CON*#

I C control

98H/RD

WR

DRDY

CDR

0

ARL

CARL

0

–

81H

80H

XSTR

0

XSTP

0

2

I DAT#

I C data

99H/RD

WR

X

FE

IDLE

AE

EAD

–

FD

FC

FB

FA

F9

F8

2

MAKSTR

MAKSTP

I STA*#

I C status

F8H

ADH

80H

–

XDATA XACTV

XSTR

A9

XSTP x0100000B

A8

AF

AD

ETI

–

AC

ES

AB

EPWM

83

AA

EX1

82

IE*#

Interrupt enable

Port 0

EA

ET0

81

EX0

80

00H

–

84

xxx11111B

P0*#

–

PWM0

–

SDA

SCL

97

T0

B7

–

96

INT1

B6

95

INT0

B5

–

94

ADC4

B4

93

ADC3

B3

92

ADC2

B2

91

ADC1

B1

90

ADC0

B0

FFH

P1*#

Port 1

90H

B0H

87H

P3*

Port 3

FFH

PCON#

Power control

–

PD

D1

IDL

D0

xxxx0000B

D7

CY

D6

AC

D5

F0

D4

D3

D2

PSW*

Program status word

PWM compare

D0H

8EH

FEH

8FH

8BH

8DH

81H

8AH

8CH

RS1

RS0

OV

–

P

00H

PWCM#

xxxxxxxxB

FEH

00H

PWENA# PWM enable

–

PWE

PWMP#

RTL#

RTH#

SP

PWM prescaler

Timer low reload

Timer high reload

Stack pointer

Timer low

00H

07H

TL#

00H

TH#

Timer high

00H

8F

8E

8D

TF

8C

TR

8B

8A

89

88

TCON*#

Timer control

88H

GATE

C/T

IE0

IT0

IE1

IT1

00H

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

9

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

Position Symbol

ADCON.5 ENADC Enable A/D function when ENADC = 1. Reset

forces ENADC = 0.

Function

Special Function Register Addresses

Special function registers for the 8XC752 are identical to those of

the 80C51, except for the changes listed below:

ADCON.4 ADCI

ADC interrupt flag. This flag is set when an

ADC conversion is complete. If IE.6 = 1, an

interrupt is requested when ADCI = 1. The

ADCI flag is cleared when conversion data is

read. This flag is read only.

ADC start. Setting this bit starts an A/D

conversion. Once set, ADCS remains high

throughout the conversion cycle. On

completion of the conversion, it is reset just

before the ADCI interrupt flag is cleared.

ADCS cannot be reset by software. ADCS

should not be used to monitor the A/D

converter status. ADCI should be used for this

purpose.

80C51 special function registers not present in the 8XC752 are

TMOD (89), P2 (A0) and IP (B8). The 80C51 registers TH1, TL1,

SCON, and SBUF are replaced with the 8XC752 registers RTH,

RTL, I2CON, and I2DAT, respectively. Additional special function

registers are I2CFG (D8) and I2STA (FB), ADCON (A0), ADAT (84),

PWM (8E), PWMP (8F), and PWENA (FE). See Table 3.

ADCON.3 ADCS

A/D Converter

The analog input circuitry consists of a 5-input analog multiplexer and

an A to D converter with 8-bit resolution. The conversion takes 40

machine cycles, i.e., 40µs at 12MHz oscillator frequency. The A/D

converter is controlled using the ADCON control register. Input

channels are selected by the analog multiplexer through ADCON

register bits 0–2.

ADCON.2 AADR2 Analog input select.

ADCON.1 AADR1 Analog input select.

ADCON.0 AADR0 Analog input select. This binary coded

address selects one of the five analog input

port pins of P1 to be input to the converter. It

can only be changed when ADCI and ADCS

are both low. AADR2 is the most significant

bit.

The 83C752 contains a five-channel multiplexed 8-bit A/D converter.

The conversion requires 40 machine cycles (40µs at 12MHz

oscillator frequency).

The A/D converter is controlled by the A/D control register, ADCON.

Input channels are selected by the analog multiplexer by bits

ADCON.0 through ADCON.2. The ADCON register is not bit

addressable.

The completion of the 8-bit ADC conversion is flagged by ADCI in

the ADCON register, and the result is stored in the special function

register ADAT.

ADCON Register

MSB

LSB

An ADC conversion in progress is unaffected by an ADC start. The

result of a completed conversion remains unaffected provided ADCI

remains at a logic 1. While ADCS is a logic 1 or ADCI is a logic 1, a

new ADC START will be blocked and consequently lost. An ADC

conversion in progress is aborted when the idle or power-down

mode is entered. The result of a completed conversion (ADCI = logic

1) remains unaffected when entering the idle mode. See Figure 2 for

an A/D input equivalent circuit.

X

ENADC

ADCI

ADCS

AADR2

AADR1

AADR0

ADCI ADCS

Operation

ADC not busy, a conversion can be started.

ADC busy, start of a new conversion is blocked.

Conversion completed, start of a new conversion is

blocked.

0

1

0

1

0

1

Not possible.

The analog input pins ADC0-ADC4 may be used as digital inputs

and outputs when the A/D converter is disabled by a 0 in the

ENADC bit in ADCON. When the A/D is enabled, the analog input

channel that is selected by the ADDR2-ADDR0 bits in ADCON

cannot be used as a digital input. Reading the selected A/D channel

as a digital input will always return a 1. The unselected A/D inputs

may always be used as digital inputs. Unselected analog inputs will

be floating and may not be used as digital outputs.

INPUT CHANNEL SELECTION

ADDR2

ADDR1

ADDR0

INPUT PIN

0

1

0

1

0

1

0

1

0

P1.0

P1.1

P1.2

P1.3

P1.4

The A/D reference inputs on the 8XC752 are tied together with the

analog supply pins AV and AV . This means that the reference

CC

SS

voltage on the A/D cannot be varied separately from the analog

supply pins. AV must be connected to 0V and AV must be

SS

CC

connected to a supply voltage between 4.5V and 5.5V. A/D

measurements may be made in the range of 4.5V to 5.5V.

Increasing the voltage on the A/D ground reference above 0V or

reducing the voltage on the positive A/D reference below 4.5V is not

permitted.

10

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

Sm

Rm

N+1

I

N+1

N

To Comparator

I

N

+

Multiplexer

R

S

C

S

V

ANALOG

INPUT

Rm = 0.5 - 3 kΩ

CS + CC = 15pF maximum

RS = Recommended < 9.6 kΩ for 1 LSB @ 12MHz

NOTE:

Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion

is initiated, switch Sm closes for 8tcy (8µs @ 12MHz crystal frequency) during which time capacitance Cs + Cc is charged. It should

be noted that the sampling causes the analog input to present a varying load to an analog source.

SU00199

Figure 2. A/D Input: Equivalent Circuit

A/D CONVERTER PARAMETER DEFINITIONS

The following definitions are included to clarify some specifications

given and do not represent a complete set of A/D parameter

definitions.

Gain Error

Gain error is the deviation between the ideal and actual analog input

voltage required to cause the final code transition to a full-scale

output code after the offset error has been removed. This may

sometimes be referred to as full scale error.

Absolute Accuracy Error

Offset Error

Absolute accuracy error of a given output is the difference between

the theoretical analog input voltage to produce a given output and

the actual analog input voltage required to produce the same code.

Since the same output code is produced by a band of input voltages,

the “required input voltage” is defined as the midpoint of the band of

input voltage that will produce that code. Absolute accuracy error

not specified with a code is the maximum over all codes.

Offset error is the difference between the actual input voltage that

causes the first code transition and the ideal value to cause the first

code transition. This ideal value is 1/2 LSB above V

.

ref–

Channel to Channel Matching

Channel to channel matching is the maximum difference between

the corresponding code transitions of the actual characteristics

taken from different channels under the same temperature, voltage

and frequency conditions.

Nonlinearity

If a straight line is drawn between the end points of the actual

converter characteristics such that zero offset and full scale errors

are removed, then non-linearity is the maximum deviation of the

code transitions of the actual characteristics from that of the straight

line so constructed. This is also referred to as relative accuracy and

also integral non-linearity.

Crosstalk

Crosstalk is the measured level of a signal at the output of the

converter resulting from a signal applied to one deselected channel.

Total Error

Maximum deviation of any step point from a line connecting the ideal

first transition point to the ideal last transition point.

Differential Non-Linearity

Differential non-linearity is the maximum difference between the

actual and ideal code widths of the converter. The code widths are

the differences expressed in LSB between the code transition

points, as the input voltage is varied through the range for the

complete set of codes.

Relative Accuracy

Relative accuracy error is the deviation of the ADC’s actual code

transition points from the ideal code transition points on a straight

line which connects the ideal first code transition point and the final

code transition point, after nullifying offset error and gain error. It is

generally expressed in LSBs or in percent of FSR.

11

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

These flags are functionally identical to the corresponding 80C51

flags except that there is only one of the 80C51 style timers, and the

flags are combined into one register.

COUNTER/TIMER

The 8XC752 counter/timer is designated Timer 0 and is separate

2

from Timer I of the I C serial port and from the PWM. Its operation is

similar to mode 2 of the 80C51 counter/timer, extended to 16 bits.

When Timer 0 is used in the external counter mode, the T0 input

(P1.7) is sampled every S4P1. The counter/timer function is

controlled using the timer control register (TCON).

Note that the positions of the IE0/IT0 and IE1/IT1 bits are

transposed from the positions used in the standard 80C51 TCON

register.

2

A communications watchdog timer, Timer I, is described in the I C

2

TCON Register

section. In I C applications, this timer is dedicated to time generation

2

and bus monitoring for the I C. In non-I C applications, it is available

for use as a fixed time base.

MSB

LSB

IT1

GATE

C/T

TF

TR

IE0

IT0

IE1

The 16-bit timer/counter’s operation is similar to mode 2 operation

on the 80C51, but is extended to 16 bits. The timer/counter is

clocked by either 1/12 the oscillator frequency or by transitions on

the T0 pin. The C/T pin in special function register TCON selects

between these two modes. When the TCON TR bit is set, the

timer/counter is enabled. Register pair TH and TL are incremented

by the clock source. When the register pair overflows, the register

pair is reloaded with the values in registers RTH and RTL. The value

in the reload registers is left unchanged. The TF bit in special

function register TCON is set on counter overflow and, if the

interrupt is enabled, will generate an interrupt (see Figure 3).

Position Symbol

TCON.7 GATE 1 – Timer 0 is enabled only when INT0 pin is

high and TR is 1.

Function

0 – Timer 0 is enabled only when TR is 1.

TCON.6 C/T

TCON.5 TF

1 – Counter operation from T0 pin.

0 – Timer operation from internal clock.

1 – Set on overflow of T0.

0 – Cleared when processor vectors to interrupt

routine and by reset.

TCON.4 TR

1 – Enable timer 0

0 – Disable timer 0

TCON.3 IE0

TCON.2 IT0

1 – Edge detected on INT0

1 – INT0 is edge triggered.

0 – INT0 is level sensitive.

1 – Edge detected on INT1

1 – INT1 is edge triggered.

0 – INT1 is level sensitive.

TCON.1 IE1

TCON.0 IT1

OSC

÷ 12

C/T = 0

C/T = 1

TL

TH

TF

Int.

T0 Pin

TR

Reload

Gate

RTL

RTH

INT0 Pin

SU00300

Figure 3. 83C752 Counter/Timer Block Diagram

2

Table 3. I C Special Function Register Addresses

REGISTER ADDRESS

BIT ADDRESS

NAME

SYMBOL

I2CON

I2DAT

ADDRESS

MSB

9F

LSB

9A

–

2

I C control

98

99

D8

F8

9E

–

9D

–

9C

–

9B

–

99

–

98

–

2

I C data

–

2

I C configuration

I2CFG

I2STA

DF

FF

DE

FE

DD

FD

DC

FC

DB

FB

DA

FA

D9

F9

D8

F8

2

I C status

12

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

1, 3, 4

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Storage temperature range

Voltage from V to V

RATING

UNIT

°C

V

–65 to +150

–0.5 to +6.5

CC

SS

Voltage from any pin to V (except V

)

–0.5 to V + 0.5

V

SS

PP

CC

Power dissipation

1.0

W

Voltage from V pin to V

–0.5 to + 13.0

V

PP

SS

DC ELECTRICAL CHARACTERISTICS

4

T

= 0°C to +70°C or –40°C to +85°C, AV = 5V ±5, AV = 0V

amb

CC SS

V

CC

= 5V ± 10%, V = 0V

SS

4

TEST

LIMITS

1

SYMBOL

PARAMETER

CONDITIONS

MIN

Typical

MAX

UNIT

I

Supply current (see Figure 6)

CC

Inputs

V

Input low voltage, except SDA, SCL

Input high voltage, except X1, RST

Input high voltage, X1, RST

(0 to 70°C)

(–40 to +85°C)

(0 to 70°C)

(–40 to +85°C)

(0 to 70°C)

(–40 to +85°C)

–0.5

0.2V –0.1

V

IL

CC

0.2V –0.15

CC

0.2V +0.9

V

CC

V

CC

+0.5

IH

CC

(0.2V +1)

CC

0.7V

V

CC

V

CC

+0.5

IH1

CC

0.7V to 0.1

CC

SDA, SCL, P0.2

Input low voltage

V

(0 to 70°C)

(–40 to +85°C)

(0 to 70°C)

(–40 to –85°C)

–0.5

0.3V

V

IL1

CC

0.3V –0.1

CC

Input high voltage

0.7V

V

CC

V

CC

+0.5

IH2

CC

0.7V +0.1

CC

Outputs

Output low voltage, ports 1, 3, 0.3, and 0.4

(PWM disabled)

Output low voltage, port 0.2

2

V

I

= 1.6mA

= 3.2mA

0.45

V

OL

2

V

OL1

OL

Output high voltage, ports 1, 3, 0.3, and 0.4

(PWM disabled)

V

I

= –60µA,

= –25µA

= –10µA

= –400µA

= –40µA

2.4

0.75V

V

OH

CC

0.9V

OH

CC

I

2.4

0.9V

OH

V

Output high voltage, P0.4 (PWM enabled)

I

OH

OH2

CC

2

I

= 3mA

Port 0.0 and 0.1 (I C) – Drivers

OL

(over V range)

Output low voltage

Driver, receiver combined:

Capacitance

CC

0.4

10

V

OL2

C

pF

I

Logical 0 input current,

ports 1, 3, 0.3, and 0.4 (PWM disabled)

V

= 0.45V (0 to 70°C)

= 0.45V (0 to +85°C)

–50

–75

–650

–750

±10

175

10

µA

kΩ

pF

IL

IN

V

11

Logical 1 to 0 transition current,

= 2V (0 to 70°C)

TL

LI

IN

11

ports 1, 3, 0.3 and 0.4

V

IN

= 2V (–40 to +85°C)

Input leakage current, port 0.0, 0.1 and 0.2

0.45 < V < V

IN

CC

R

C

Reset pull-down resistor

25

RST

IO

Pin capacitance

Test freq = 1MHz,

T

amb

= 25°C

5

I

Power-down current

V

= 2 to 5.5V

= 2 to 6.0V

(83C752)

50

13.0

50

µA

V

PD

CC

V

PP

program voltage (87C752 only)

V

CC

= 0V

12.5

PP

SS

V

amb

= 5V±10%

= 21°C to 27°C

T

I

PP

Program current (87C752 only)

V

= 13.0V

mA

PP

13

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

DC ELECTRICAL CHARACTERISTICS (Continued)

4

T

amb

= 0°C to +70°C or –40°C to +85°C, AV = 5V ±5, AV = 0V

CC SS

V

CC

= 5V ± 10%, V = 0V

SS

4

TEST

LIMITS

1

SYMBOL

PARAMETER

CONDITIONS

MIN

Typical

MAX

UNIT

Analog Inputs (A/D guaranteed only with quartz window covered.)

10

AV

Analog supply voltage

AV = V ±0.2V

4.5

5.5

V

mA

V

CC

9

AI

CC

Analog operating supply current

AV = 5.12V

3

CC

12

AV

Analog input voltage

AV –0.2

AV +0.2

IN

SS

CC

C

Analog input capacitance

Sampling time

15

pF

s

IA

t

8t

CY

ADS

ADC

t

Conversion time

Resolution

40t

s

CY

R

8

bits

LSB

%

E

RA

Relative accuracy

Zero scale offset

Full scale gain error

Channel to channel matching

Crosstalk

±1

OS

e

G

0.4

±1

e

M

LSB

dB

CTC

C

0–100kHz

–60

t

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

10mA

26mA

67mA

(NOTE: This is 85°C spec.)

OL

Maximum I per 8-bit port:

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

4. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

5. Power-down I is measured with all output pins disconnected; port 0 = V ; X2, X1 n.c.; RST = V .

CC

SS

6. I is measured with all output pins disconnected; X1 driven with t

, t

= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;

CC

CLCH CHCL IL SS IH CC

RST = port 0 = V . I will be slightly higher if a crystal oscillator is used.

CC CC

7. Idle I is measured with all output pins disconnected; X1 driven with t

, t

= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;

CC

CLCH CHCL IL SS IH CC

port 0 = V

RST = V

.

CC;

SS

8. Load capacitance for ports = 80pF.

9. The resistor ladder network is not disconnected in the power down or idle modes. Thus, to conserve power, the user may remove AV

.

CC

10.If the A/D function is not required, or if the A/D function is only needed periodically, AV may be removed without affecting the operation of

CC

the digital circuitry. Contents of ADCON and ADAT are not guaranteed to be valid. If AV is removed, the A/D inputs must be lowered to

CC

less than 0.5V. Digital inputs on P1.0–P1.4 will not function normally.

11. These parameters do not apply to P1.0–P1.4 if the A/D function is enabled.

12.The input voltage slew rate should be <10V/ms. The maximum slew rate depends on the clock frequency of the microcontroller. Designers

should use low pass filters before the A/D inputs as a precaution to noise edges causing false readings.

14

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

AC ELECTRICAL CHARACTERISTICS

4, 8

T

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

amb

CC SS

12MHz CLOCK

VARIABLE CLOCK

SYMBOL

1/t

PARAMETER

MIN

MAX

MIN

MAX

UNIT

Oscillator frequency:

3.5

12

16

MHz

CLCL

External Clock (Figure 4)

t

High time

Low time

Rise time

Fall time

20

ns

CHCX

CLCX

CLCH

CHCL

20

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal.

The designations are:

C – Clock

D – Input data

H – Logic level high

L – Logic level low

Q – Output data

T – Time

V – Valid

X – No longer a valid logic level

Z – Float

t

V

–0.5

CLCX

CC

0.2 V + 0.9

CC

0.2 V – 0.1

CC

t

0.45V

CHCX

t

CLCH

CHCL

t

CLCL

SU00297

Figure 4. External Clock Drive

V

–0.5

CC

0.2 V + 0.9

CC

0.2 V – 0.1

CC

0.45V

SU00307

Figure 5. AC Testing Input/Output

15

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

6

MAX ACTIVE I

CC

22

20

18

16

14

6

12

10

8

I

mA

TYP ACTIVE I

CC

6

7

MAX IDLE I

CC

4

2

7

TYP IDLE I

CC

4MHz

8MHz

FREQ

12MHz

16MHz

SU00308

Figure 6. I vs. FREQ

CC

Maximum I values taken at V = 5.5V and worst case temperature.

CC

Typical I values taken at V = 5.0V and 25°C.

CC

Notes 6 and 7 refer to AC Electrical Characteristics.

EPROM location specified by the address which has been supplied

to Port 3.

PROGRAMMING CONSIDERATIONS

EPROM Characteristics

The XTAL1 pin is the oscillator input and receives the master system

clock. This clock should be between 1.2 and 6MHz.

The 87C752 is programmed by using a modified Quick-Pulse

Programming algorithm similar to that used for devices such as the

87C451 and 87C51. It differs from these devices in that a serial data

stream is used to place the 87C752 in the programming mode.

The RESET pin is used to accept the serial data stream that places

the 87C752 into various programming modes. This pattern consists

of a 10-bit code with the LSB sent first. Each bit is synchronized to

the clock input, X1.

Figure 7 shows a block diagram of the programming configuration

for the 87C752. Port pin P0.2 is used as the programming voltage

supply input (V signal). Port pin P0.1 is used as the program

(PGM/) signal. This pin is used for the 25 programming pulses.

PP

Programming Operation

Figures 8 and 9 show the timing diagrams for the program/verify

cycle. RESET should initially be held high for at least two machine

Port 3 is used as the address input for the byte to be programmed

and accepts both the high and low components of the eleven bit

address. Multiplexing of these address components is performed

using the ASEL input. The user should drive the ASEL input high

and then drive port 3 with the high order bits of the address. ASEL

should remain high for at least 13 clock cycles. ASEL may then be

driven low which latches the high order bits of the address internally.

The high address should remain on port 3 for at least two clock

cycles after ASEL is driven low. Port 3 may then be driven with the

low byte of the address. The low address will be internally stable 13

clock cycles later. The address will remain stable provided that the

low byte placed on port 3 is held stable and ASEL is kept low. Note:

ASEL needs to be pulsed high only to change the high byte of the

address.

cycles. P0.1 (PGM/) and P0.2 (V ) will be at V as a result of the

PP

OH

RESET operation. At this point, these pins function as normal

quasi-bidirectional I/O ports and the programming equipment may

pull these lines low. However, prior to sending the 10-bit code on the

RESET pin, the programming equipment should drive these pins

high (V ). The RESET pin may now be used as the serial data input

IH

for the data stream which places the 87C752 in the programming

mode. Data bits are sampled during the clock high time and thus

should only change during the time that the clock is low. Following

transmission of the last data bit, the RESET pin should be held low.

Next the address information for the location to be programmed is

placed on port 3 and ASEL is used to perform the address

multiplexing, as previously described. At this time, port 1 functions

as an output.

Port 1 is used as a bidirectional data bus during programming and

verify operations. During programming mode, it accepts the byte to

be programmed. During verify mode, it provides the contents of the

16

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

A high voltage V level is then applied to the V input (P0.2).

memory will be encrypted with the second byte in the encryption

table and so forth up to and including the 16the byte. The encryption

repeats in 16-byte groups; the 17th byte in the code memory will be

encrypted with the first byte in the encryption table, and so forth.

PP

(This sets Port 1 as an input port). The data to be programmed into

the EPROM array is then placed on Port 1. This is followed by a

series of programming pulses applied to the PGM/ pin (P0.1). These

pulses are created by driving P0.1 low and then high. This pulse is

repeated until a total of 25 programming pulses have occurred. At

the conclusion of the last pulse, the PGM/ signal should remain high.

Security Bits

Two security bits, security bit 1 and security bit 2, are provided to

limit access to the USER EPROM and encryption key arrays.

Security bit 1 is the program inhibit bit, and once programmed

performs the following functions:

The V signal may now be driven to the V level, placing the

PP

OH

87C752 in the verify mode. (Port 1 is now used as an output port).

After four machine cycles (48 clock periods), the contents of the

addressed location in the EPROM array will appear on Port 1.

1. Additional programming of the USER EPROM is inhibited.

2. Additional programming of the encryption key is inhibited.

3. Verification of the encryption key is inhibited.

The next programming cycle may now be initiated by placing the

address information at the inputs of the multiplexed buffers, driving

the V pin to the V voltage level, providing the byte to be

PP

4. Verification of the USER EPROM and the security bit levels may

still be performed.

programmed to Port1 and issuing the 26 programming pulses on the

PGM/ pin, bringing V back down to the V level and verifying the

PP

C

byte.

(If the encryption key array is being used, this security bit should be

programmed by the user to prevent unauthorized parties from

reprogramming the encryption key to all logical zero bits. Such

programming would provide data during a verify cycle that is the

logical complement of the USER EPROM contents).

Programming Modes

The 87C752 has four programming features incorporated within its

EPROM array. These include the USER EPROM for storage of the

application’s code, a 16-byte encryption key array and two security

bits. Programming and verification of these four elements are

selected by a combination of the serial data stream applied to the

RESET pin and the voltage levels applied to port pins P0.1 and

P0.2. The various combinations are shown in Table 4.

Security bit 2, the verify inhibit bit, prevents verification of both the

USER EPROM array and the encryption key arrays. The security bit

levels may still be verified.

Programming and Verifying Security Bits

Security bits are programmed employing the same techniques used

to program the USER EPROM and KEY arrays using serial data

streams and logic levels on port pins indicated in Table 4. When

programming either security bit, it is not necessary to provide

address or data information to the 87C752 on ports 1 and 3.

Encryption Key Table

The 87C752 includes a 16-byte EPROM array that is programmable

by the end user. The contents of this array can then be used to

encrypt the program memory contents during a program memory

verify operation. When a program memory verify operation is

performed, the contents of the program memory location is

XNOR’ed with one of the bytes in the 16-byte encryption table. The

resulting data pattern is then provided to port 1 as the verify data.

The encryption mechanism can be disable, in essence, by leaving

the bytes in the encryption table in their erased state (FFH) since

the XNOR product of a bit with a logical one will result in the original

bit. The encryption bytes are mapped with the code memory in

16-byte groups. the first byte in code memory will be encrypted with

the first byte in the encryption table; the second byte in code

Verification occurs in a similar manner using the RESET serial

stream shown in Table 4. Port 3 is not required to be driven and the

results of the verify operation will appear on ports 1.6 and 1.7.

Ports 1.7 contains the security bit 1 data and is a logical one if

programmed and a logical zero if not programmed. Likewise, P1.6

contains the security bit 2 data and is a logical one if programmed

and a logical zero if not programmed.

Table 4. Implementing Program/Verify Modes

OPERATION

SERIAL CODE

P0.1 (PGM/)

P0.2 (V

)

PP

Program user EPROM

Verify user EPROM

Program key EPROM

Verify key EPROM

Program security bit 1

Program security bit 2

Verify security bits

296H

292H

29AH

298H

29AH

–*

V

PP

V

IH

V

IH

–*

V

PP

V

IH

V

IH

PP

–*

V

IH

V

IH

NOTE:

*

Pulsed from V to V and returned to V .

IH IL IH

17

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

EPROM PROGRAMMING AND VERIFICATION

T

amb

= 21°C to +27°C, V = 5V ±10%, V = 0V

CC SS

SYMBOL

PARAMETER

MIN

1.2

MAX

UNIT

1/t

Oscillator/clock frequency

6

MHz

CLCL

1

t

Address setup to P0.1 (PROG–) low

Address hold after P0.1 (PROG–) high

Data setup to P0.1 (PROG–) low

Data hold after P0.1 (PROG–) high

10µs + 24t

AVGL

CLCL

48t

38t

36t

GHAX

DVGL

GHDX

SHGL

GHSL

GLGH

CLCL

V

setup to P0.1 (PROG–) low

hold after P0.1 (PROG–)

10

90

µs

PP

V

P0.1 (PROG–) width

low (V ) to data valid

110

2

V

PP

48t

CLCL

AVQV

CC

P0.1 (PROG–) high to P0.1 (PROG–) low

P0.0 (sync pulse) low

10

µs

GHGL

SYNL

4t

CLCL

8t

CLCL

P0.0 (sync pulse) high

SYNH

MASEL

MAHLD

HASET

ADSTA

ASEL high time

13t

CLCL

Address hold time

2t

Address setup to ASEL

Low address to address stable

13t

CLCL

NOTES:

1. Address should be valid at least 24t

before the rising edge of P0.2 (V ).

CLCL

PP

2. For a pure verify mode, i.e., no program mode in between, t

is 14t

maximum.

AVQV

CLCL

87C752

A0–A10

P3.0–P3.7

V

+5V

CC

ADDRESS STROBE

P0.0/ASEL

SS

PROGRAMMING

PULSES

P0.1

V

/V VOLTAGE

P0.2

PP IH

P1.0–P1.7

DATA BUS

SOURCE

CLK SOURCE

XTAL1

RESET

CONTROL

LOGIC

RESET

SU00320

Figure 7. Programming Configuration

XTAL1

MIN 2 MACHINE

CYCLES

TEN BIT SERIAL CODE

RESET

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

UNDEFINED

P0.2

P0.1

UNDEFINED

SU00302

Figure 8. Entry into Program/Verify Modes

18

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

12.75V

P0.2 (V

)

5V

t

PP

t

SHGL

GHSL

25 PULSES

P0.1 (PGM)

P0.0 (ASEL)

t

GLGH

MASEL

t

GHGL

98µs MIN

10µs MIN

t

HASET

t

HAHLD

HIGH ADDRESS

LOW ADDRESS

PORT 3

PORT 1

t

AVQV

ADSTA

DVGL

GHDX

INVALID DATA

VERIFY MODE

VALID DATA

DATA TO BE PROGRAMMED

PROGRAM MODE

INVALID DATA

VALID DATA

VERIFY MODE

SU00310

Figure 9. Program/Verify Cycle

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

19

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm

SOT341-1

20

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

DIP28: plastic dual in-line package; 28 leads (600 mil); long body

SOT117-2

21

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

PLCC28: plastic leaded chip carrer; 28 leads; pedestal

SOT261-3

22

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

NOTES

23

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

83C752/87C752

2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1998

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 05-98

Document order number:

9397 750 03843

24

1998 May 01


型号：	83C751
厂家：	NXP
描述：	80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count 80C51的8位单片机系列2K / 64 OTP / ROM ， I2C ，低引脚数
文件：	总24页 (文件大小：228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

83C751 [NXP]

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