933372810653 [NXP]
IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, PLASTIC, SOT-109-1, SO-16, Counter;
| 型号： | 933372810653 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, PLASTIC, SOT-109-1, SO-16, Counter CD 输入元件 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4029B
MSI
Synchronous up/down counter,
binary/decade counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Information on P0 to P3 is asynchronously loaded into the
counter while PL is HIGH, independent of CP.
DESCRIPTION
The HEF4029B is a synchronous edge-triggered up/down
4-bit binary/BCD decade counter with a clock input (CP),
an active LOW count enable input (CE), an up/down
control input (UP/DN), a binary/decade control input
(BIN/DEC), an overriding asynchronous active HIGH
parallel load input (PL), four parallel data inputs (P0 to P3),
four parallel buffered outputs (O0 to O3) and an active
LOW terminal count output (TC).
The counter is advanced one count on the LOW to HIGH
transition of CP when CE and PL are LOW. The TC signal
is normally HIGH and goes LOW when the counter
reaches its maximum count in the UP mode, or the
minimum count in the DOWN mode provided CE is LOW.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
HEF4029BP(N):
HEF4029BD(F):
HEF4029BT(D):
16-lead DIL; plastic
(SOT38-1)
PL
parallel load input
P0 to P3
BIN/DEC
UP/DN
CE
parallel data inputs
16-lead DIL; ceramic (cerdip)
(SOT74)
binary/decade control input
up/down control input
16-lead SO; plastic
(SOT109-1)
count enable input (active LOW)
clock input (LOW to HIGH, edge triggered)
buffered parallel outputs
CP
( ): Package Designator North America
O0 to O3
TC
terminal count output (active LOW)
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.3 Logic diagram (continued in Fig.4).
January 1995
3
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.4 Logic diagram (continued from Fig.3).
January 1995
4
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
FUNCTION TABLE
PL
BIN/DEC
UP/DN
CE
CP
MODE
H
L
L
X
X
L
X
X
L
X
H
L
X
X
parallel load (Pn → On)
no change
count-down, decade
L
L
L
L
H
H
H
L
L
L
L
count-up, decade
count-down, binary
count-up, binary
H
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going clock pulse edge
Fig.5 State diagram; BIN/DEC = LOW.
January 1995
5
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.6 State diagram; BIN/DEC = HIGH.
Logic equation for terminal count:
TC = CE (BIN ⁄ DEC • UP ⁄ DN • O0 • O1 • O2 • O3 + BIN ⁄ DEC • UP ⁄ DN • O0 • O1 • O2 • O3 +
BIN ⁄ DEC • UP ⁄ DN • O0 • O3 + BIN ⁄ DEC • UP ⁄ DN • O0 • O1 • O2 • O3 )
January 1995
6
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
2
Dynamic power
5
1000 fi + ∑(foCL) × VDD
4500 fi + ∑(foCL) × VDD
where
dissipation per
package (P)
10
15
fi = input freq. (MHz)
11 500 fi + ∑(foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → On
5
145
55
290
110
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
118 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
133 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
253 ns + (0,55 ns/pF) CL
94 ns + (0,23 ns/pF) CL
62 ns + (0,16 ns/pF) CL
168 ns + (0,55 ns/pF) CL
64 ns + (0,23 ns/pF) CL
47 ns + (0,16 ns/pF) CL
93 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
153 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
HIGH to LOW
10
15
5
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
40
160
60
315
120
80
LOW to HIGH
10
15
5
40
CP → TC
280
105
70
560
205
140
385
150
105
240
100
70
HIGH to LOW
10
15
5
195
75
LOW to HIGH
10
15
5
55
PL → On
120
50
HIGH to LOW
10
15
5
35
170
65
335
130
90
LOW to HIGH
10
15
5
45
CE → TC
180
70
360
140
100
335
135
100
HIGH to LOW
10
15
5
50
170
65
LOW to HIGH
10
15
50
January 1995
7
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
60
MAX.
Output transition times
HIGH to LOW
5
120
60
ns
ns
ns
ns
ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tTHL
30
20
60
30
20
40
120
60
LOW to HIGH
10
15
tTLH
40
January 1995
8
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN
TYP
MAX
Minimum clock
pulse width; LOW
5
110
35
25
160
55
35
150
50
35
270
90
60
300
105
75
240
90
70
70
20
10
45
15
10
15
0
55
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
10
15
5
tWCPL
15
Minimum PL
pulse width; HIGH
80
10
15
5
tWPLH
tRPL
tsu
25
15
Recovery time
for PL
75
10
15
5
25
20
Set-up times
135
45
BIN/DEC → CP
10
15
5
30
150
55
UP/DN → CP
CE → CP
Pn → PL
10
15
5
tsu
35
120
50
10
15
5
tsu
40
see also waveforms
Figs 7 and 8
35
10
15
5
tsu
10
5
Hold times
−90
−30
−20
−135
−50
−35
−30
−10
−10
−20
−10
−5
BIN/DEC → CP
UP/DN → CP
CE → CP
10
15
5
thold
thold
thold
thold
fmax
10
15
5
−5
30
10
5
10
15
5
15
0
Pn → PL
10
15
5
0
Maximum clock
pulse frequency
2
4
10
15
5
10
8
15
January 1995
9
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.7 Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP, BIN/DEC to CP
and UP/DN to CP. Set-up and hold times are shown as positive values but may be specified as negative
values.
Fig.8 Waveforms showing minimum pulse width for PL, recovery time for PL, and set-up and hold times for Pn
to PL. Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995
10
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Fig.9 Timing diagram; decade mode; P0 = LOW; P3 = LOW; BIN/DEC = LOW.
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Fig.10 Timing diagram; binary mode; P0 = HIGH; P1 = LOW; BIN/DEC = HIGH.
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
APPLICATION INFORMATION
Some examples of applications for the HEF4029B are:
• Programmable binary and decade counting/frequency synthesizers - BCD output.
• Analogue-to-digital and digital-to-analogue conversion.
• Up/down binary counting.
• Magnitude and sign generation.
• Up/down decade counting.
• Difference counting.
January 1995
13
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Fig.11 Example of parallel clocking when cascading HEF4029B ICs.
Note
TC lines at all stages after the first may have a negative-going glitch pulse resulting from differential delays of different HEF4029B ICs. These
negative-going glitches do not affect proper HEF4029B operation; however if the TC signals are used to trigger other edge-sensitive logic devices,
such as flip-flops or counters, the TC signals should be gated with the clock signal using a 2-input OR gate such as HEF4071B.
Fig.12 Example of ripple clocking when cascading HEF4029B ICs. Ripple clocking mode: the up/down control can be changed at any count;
the only restriction on changing the up/down control is that the clock input to the first counting stage must be HIGH.
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