933450870112 [NXP]
IC 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED 17-BIT UP DECADE COUNTER, PDIP18, PLASTIC, SOT-102-1, DIP-18, Counter;
| 型号： | 933450870112 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED 17-BIT UP DECADE COUNTER, PDIP18, PLASTIC, SOT-102-1, DIP-18, Counter 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4737B
HEF4737V
LSI
Quadruple static decade counters
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4737B
HEF4737V
Quadruple static decade counters
The complementary MOS structure gives the devices very
low stand-by and operating dissipation. Operating from a
single supply voltage all outputs can drive one standard
TTL input without interface circuitry under all specified
operating conditions.
DESCRIPTION
The HEF4737B and HEF4737V are static quadruple
decade counters for frequencies from 0 to 10 MHz. The
counters are supplied with an extra overload flip-flop giving
a total count capability of 19 999. The counter has the
following inputs and outputs: a count input (CP), an
asynchronous reset input (MR), an asynchronous preset
input (PL), a transfer input (T), an output enable input (EO)
(which controls the BCD outputs), the digit select inputs
(SA, SB, SC) (which perform selection of the contents of the
latches to the 3-state BCD outputs (O0 to O3)), and the
carry outputs (CO2 to CO5) (which give the carry signals of
the decades except from the first decade).
The BCD digit outputs are LOCMOS 3-state outputs. The
high impedance off-state feature allows common busing of
the outputs. The counters are supplied with asynchronous
reset and preset to 19 999 facilities making them suitable
for counter and time base applications. All carry signals
are available except from the first decade.
Schmitt-trigger action in the inputs makes the circuit highly
tolerant to slower input rise and fall times.
Recommended supply voltage range for HEF4737B is 3 to
15 V and for HEF4737V is 4,5 to 12,5 V.
HEF4737BP; HEF4737VP(N); 18-lead DIL
plastic (SOT102-1)
HEF4737BD; HEF4737VD(F); 18-lead DIL
ceramic (SOT133B)
( ): Package Designator North America
SUPPLY VOLTAGE
RATING
RECOMMENDED
OPERATING
HEF4737B
HEF4737V
−0,5 to 18
−0,5 to 18
3,0 to 15,0
4,5 to 12,5
V
V
Fig.1 Pinning diagram.
FAMILY DATA, IDD LIMITS category LSI
PINNING
See Family Specifications
CP
count input
MR
asynchronous reset input
asynchronous preset input
transfer input
PL
T
SA, SB, SC
EO
digit select inputs
output enable input
BCD outputs
O0 to O3
CO2 to CO5
carry outputs
January 1995
2
Philips Semiconductors
Product specification
HEF4737B
HEF4737V
Quadruple static decade counters
Fig.2 Block diagram.
FUNCTIONAL DESCRIPTION
Input signals
Preset input (PL)
This is an asynchronous preset. When MR is LOW a HIGH
at the PL input will preset the counter to 19 999
independent of the level at the count input.
Count input (CP)
The signal to be counted is applied to this input. When PL
and MR are LOW the contents of the counter increments
by one at a LOW to HIGH transition of CP.
Transfer input (T)
A HIGH level applied to this input allows the information
held by the counter to pass to the latches.
Reset input (MR)
Output enable input (EO)
This is an asynchronous reset. A HIGH level applied to this
input will reset the counter to zero independent of the level
at the count input and preset input.
A HIGH level at this input enables the BCD outputs and
information can be read out of the latches using the
January 1995
3
Philips Semiconductors
Product specification
HEF4737B
HEF4737V
Quadruple static decade counters
multiplexer. A LOW level at this input disables the BCD
outputs making them floating (high impedance off-state).
Output signals
The carry outputs are active LOW outputs.
Carry output CO2
Digit select inputs (SA, SB, SC)
When the contents of the first two decades of the counter
are both 9 then the CO2 output becomes LOW. It remains
LOW until the next LOW to HIGH transition of the count
input, i.e. until the contents of the first two decades are
zero. CO2 is LOW when the contents of the counter are: 00
099, 00 199, 00 299 etc.
SA
L
SB
SC
L
L
L
L
L
L
H
selects D1 (LSD)
selects D2
H
L
H
H
X
selects D3
H
X
selects D4
Carry output CO3
selects D5 (MSD)
When the contents of the first three decades of the counter
are all 9 then the CO3 output becomes LOW. It remains
LOW until the next LOW to HIGH transition of the count
input, i.e. until the contents of the first three decades are
zero. CO3 is LOW when the contents of the counter are
00 999, 01 999, 02 999 etc.
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. When D5 is selected, the contents of D5 is available at
O0 and O1, O2 and O3 are LOW.
Carry output CO4
5. LSD = least significant divider
6. MSD = most significant divider
When the contents of the first four decades of the counter
are all 9 then the CO4 output becomes LOW. It remains
LOW until the next LOW to HIGH transition of the count
input, i.e. until the contents of the first four decades are
zero. CO4 is LOW when the contents of the counter are
09 999 and 19 999.
The carry signals CO2 , CO3 and CO4 are suppressed
while the preset is active. A HIGH to the preset input sets
the counter to 19 999 but the carry signals remain HIGH
until preset input returns to LOW, then the carry outputs
will also become LOW.
Carry output CO5
When the content of the counter is 10 000 the CO5 output
becomes LOW. It returns to HIGH when the content of the
counter is zero.
Digit outputs (O0 to O3)
The digit outputs give the contents of the selected latch.
The output is in the form of BCD, positive logic.
January 1995
4
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Fig.3 Timing diagram.
Philips Semiconductors
Product specification
HEF4737B
HEF4737V
Quadruple static decade counters
The values given at VDD = 15 V in the following d.c. and a.c. characteristics, are not applicable to the HEF4737V,
because of its reduced supply voltage range.
DC CHARACTERISTICS
VSS = 0 V
Tamb (°C)
VDD
V
VOH
V
VOL
V
SYMBOL
−40
+ 25
MIN.
+ 85
MIN. MAX.
MAX. MIN. MAX.
Input leakage
current at
10
15
4,75
10
15
5
−
−
−
−
−
−
−
−
−
−
−
−
0,3
0,3
−
−
−
1
1
−
−
−
−
−
−
µA
µA
± IIN
VI = 0 or VDD
Output (sink)
current LOW
0,4
0,5
1,5
1,6
2,5
7,0
0,96
2,4
7,0
1,6
2,3
6,0
0,80
2,0
6,0
1,4
1,7
4,0
0,65
1,6
4,5
mA
mA
mA
mA
mA
mA
IOL
−
−
Output (source)
current HIGH
4,6
−
10
15
9,5
−IOH
−
13,5
−
Output (source)
current HIGH
3-state output
leakage current
VO = 0 or VDD
5
2,5
−IOH
3,0
−
2,5
−
2,0
−
mA
10
15
−
−
1,6
1,6
−
−
1,6
1,6
−
−
12
12
µA
µA
± IOZ
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 15 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN.
TYP. MAX.
Propagation delays
CP → On
5
320
120
90
640
240
180
640
240
180
ns
308 ns + (0,24 ns/pF) CL
125 ns + (0,10 ns/pF) CL
86 ns + (0,07 ns/pF) CL
296 ns + (0,48 ns/pF) CL
110 ns + (0,20 ns/pF) CL
82 ns + (0,15 ns/pF) CL
608 ns + (0,24 ns/pF) CL
325 ns + (0,10 ns/pF) CL
246 ns + (0,07 ns/pF) CL
596 ns + (0,48 ns/pF) CL
320 ns + (0,20 ns/pF) CL
242 ns + (0,15 ns/pF) CL
(D1 selected)
HIGH to LOW
10
15
5
tPHL
tPLH
tPHL
tPLH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
320
120
90
LOW to HIGH
10
15
5
CP → On
620 1240
(D5 selected)
HIGH to LOW
10
15
5
330
250
660
500
620 1240
LOW to HIGH
10
15
330
250
660
500
January 1995
6
Philips Semiconductors
Product specification
HEF4737B
HEF4737V
Quadruple static decade counters
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
V
MIN.
TYP. MAX.
CP → CO2
HIGH to LOW
5
10
15
5
220
110
85
440
220
170
400
220
170
ns
ns
ns
ns
ns
ns
208 ns + (0,24 ns/pF) CL
105 ns + (0,10 ns/pF) CL
81 ns + (0,07 ns/pF) CL
196 ns + (0,48 ns/pF) CL
100 ns + (0,20 ns/pF) CL
77 ns + (0,15 ns/pF) CL
tPHL
220
110
85
LOW to HIGH
10
15
tPLH
Propagation delays
CP → CO5
5
10
15
5
350
160
120
350
160
120
200
80
700
320
240
700
320
240
400
160
110
400
160
110
440
180
120
440
180
120
980
400
120
520
220
170
700
320
240
700
320
240
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
338 ns + (0,24 ns/pF) CL
155 ns + (0,10 ns/pF) CL
116 ns + (0,07 ns/pF) CL
326 ns + (0,48 ns/pF) CL
150 ns + (0,20 ns/pF) CL
112 ns + (0,15 ns/pF) CL
188 ns + (0,24 ns/pF) CL
75 ns + (0,10 ns/pF) CL
51 ns + (0,07 ns/pF) CL
176 ns + (0,48 ns/pF) CL
70 ns + (0,20 ns/pF) CL
47 ns + (0,15 ns/pF) CL
208 ns + (0,24 ns/pF) CL
85 ns + (0,10 ns/pF) CL
56 ns + (0,07 ns/pF) CL
196 ns + (0,48 ns/pF) CL
80 ns + (0,20 ns/pF) CL
52 ns + (0,15 ns/pF) CL
478 ns + (0,24 ns/pF) CL
195 ns + (0,10 ns/pF) CL
56 ns + (0,07 ns/pF) CL
236 ns + (0,48 ns/pF) CL
100 ns + (0,20 ns/pF) CL
77 ns + (0,15 ns/pF) CL
326 ns + (0,48 ns/pF) CL
150 ns + (0,20 ns/pF) CL
112 ns + (0,15 ns/pF) CL
338 ns + (0,24 ns/pF) CL
155 ns + (0,10 ns/pF) CL
116 ns + (0,07 ns/pF) CL
HIGH to LOW
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
tPHL
LOW to HIGH
10
15
5
Sn → On
HIGH to LOW
10
15
5
55
200
80
LOW to HIGH
10
15
5
55
T→ On
220
90
HIGH to LOW
10
15
5
60
220
90
LOW to HIGH
10
15
5
60
MR → On
490
200
60
HIGH to LOW
10
15
5
PL → On
260
110
85
LOW to HIGH
10
15
5
MR → COn
350
160
120
350
160
120
LOW to HIGH
10
15
5
PL → COn
HIGH to LOW
10
15
January 1995
7
Philips Semiconductors
Product specification
HEF4737B
HEF4737V
Quadruple static decade counters
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
V
MIN.
TYP. MAX.
Output transition
times; any output
HIGH to LOW
5
10
15
5
35
18
15
50
30
25
70
36
ns
ns
ns
ns
ns
ns
15 ns + (0,40 ns/pF) CL
9 ns + (0,18 ns/pF) CL
8 ns + (0,13 ns/pF) CL
15 ns + (0,70 ns/pF) CL
13 ns + (0,33 ns/pF) CL
13 ns + (0,23 ns/pF) CL
tTHL
30
100
60
LOW to HIGH
10
15
tTLH
50
3-state propagation delays
Output disable times
EO → On
5
10
15
5
60
35
25
60
35
25
120
70
ns
ns
ns
ns
ns
ns
HIGH
tPHZ
50
120
70
LOW
10
15
tPLZ
50
Output enable times
EO → On
5
10
15
5
90
40
30
90
40
30
80
30
25
50
25
20
60
30
25
50
20
18
6
180
80
ns
ns
HIGH
tPZH
60
ns
180
80
ns
LOW
10
15
5
tPZL
ns
60
ns
Maximum CP pulse
width; LOW
160
ns
10
15
5
tWCPL
tWMRH
tWPLH
tWTH
fmax
60
50
100
50
40
120
60
50
100
40
36
3
ns
ns
Minimum MR pulse
width; HIGH
ns
10
15
5
ns
ns
Minimum PL pulse
width; HIGH
ns
10
15
5
ns
ns
Minimum T pulse
width; HIGH
ns
10
15
5
ns
ns
Maximum clock
pulse frequency
MHz
MHz
MHz
10
15
8
16
20
10
January 1995
8
Philips Semiconductors
Product specification
HEF4737B
HEF4737V
Quadruple static decade counters
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
Dynamic power
dissipation per
package (P)
5
950 fi + ∑ (foCL) × VDD
4 200 fi + ∑ (foCL) × VDD
where
10
15
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
2
11 200 fi + ∑ (foCL) × VDD
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
9
Philips Semiconductors - hef4737b_v_cnv_3 (discontinued/ withdrawn)
Discontinued and withdrawn products, packages,
availability and ordering
North
American
Type
marking/packing
Order code
device
buy
Discretes
Type number number (12nc)
package status
online
packing info
Standard Marking
* Bulk Pack
SOT102
SOT133
SOT102
SOT102
Withdrawn
Withdrawn
Withdrawn
Withdrawn
HEF4737BP
HEF4737VD
HEF4737VP
HEF4737VPB
9334 070 10112
-
-
-
-
Standard Marking
* Bulk Pack
9334 934 70112
9334 508 70112
9336 376 10112
Standard Marking
* Bulk Pack
Standard Marking
* Bulk Pack
Detailed discontinuation information
Please note, devices listed in the "Products, packages, availability and ordering" table marked with "Withdrawn" are not in production
anymore. Devices marked with "Discontinued" will not be in production in the near future.
Contact your nearest sales or distributor office for the latest information on product status and availability.
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hef4737b_v_cnv_3
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