933668770652 [NXP]
HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDIP14, DIP-14;
| 型号： | 933668770652 |
| 厂家： | 
NXP |
| 描述： | HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDIP14, DIP-14 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总5页 (文件大小：33K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT04
Hex inverter
September 1993
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Hex inverter
74HC/HCT04
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT04 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT04 provide six inverting buffers.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CI
propagation delay nA to nY
input capacitance
CL = 15 pF; VCC = 5 V
7
8
ns
pF
pF
3.5
21
3.5
24
CPD
power dissipation capacitance per gate notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
Σ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2
Philips Semiconductors
Product specification
Hex inverter
74HC/HCT04
PIN DESCRIPTION
PIN NO.
SYMBOL
1A to 6A
1Y to 6Y
GND
NAME AND FUNCTION
data inputs
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
data outputs
7
ground (0 V)
14
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUT
nA
OUTPUT
nY
L
H
H
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
Fig.5 Logic diagram
(one inverter).
Fig.4 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
Hex inverter
74HC/HCT04
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85
−40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA to nY
25
9
7
85
17
14
105
21
18
130
26
22
2.0
4.5
6.0
ns
Fig.6
Fig.6
t
THL/ tTLH output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
ns
September 1993
4
Philips Semiconductors
Product specification
Hex inverter
74HC/HCT04
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per unit, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nA
1.20
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85
−40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA to nY
10
7
19
15
24
19
29
22
ns
ns
4.5
4.5
Fig.6
Fig.6
t
THL/ tTLH output transition
time
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V
Fig.6 Waveforms showing the data input (nA) to data output (nY) propagation delays and the output transition
times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
5
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