933669780652 [NXP]
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, SOT-38-1, DIP-16;
| 型号： | 933669780652 |
| 厂家： | 
NXP |
| 描述： | HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, SOT-38-1, DIP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4094
8-stage shift-and-store bus register
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
The data in each shift register stage is transferred to the
storage register when the strobe input (STR) is HIGH.
Data in the storage register appears at the outputs
whenever the output enable input (OE) signal is HIGH.
FEATURES
• Output capability: standard
• ICC category: MSI
Two serial outputs (QS1 and QS2) are available for
cascading a number of “4094” devices. Data is available at
QS1 on the positive-going clock edges to allow high-speed
operation in cascaded systems in which the clock rise time
is fast. The same serial information is available at QS2 on
the next negative-going clock edge and is for cascading
“4094” devices when the clock rise time is slow.
GENERAL DESCRIPTION
The 74HC/HCT4094 are high-speed Si-gate CMOS
devices and are pin compatible with the “4094” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4094 are 8-stage serial shift registers
having a storage latch associated with each stage for
strobing data from the serial input (D) to the parallel
buffered 3-state outputs (QP0 to QP7). The parallel outputs
may be connected directly to common bus lines.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register
Data is shifted on the positive-going clock (CP) transitions.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
CP to QS1
15
13
20
18
95
3.5
83
19
18
21
19
86
ns
CP to QS2
ns
CP to QPn
ns
STR to QPn
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
pF
3.5
92
CPD
power dissipation capacitance per package notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
PIN DESCRIPTION
PIN NO.
SYMBOL
STR
NAME AND FUNCTION
strobe input
1
2
D
serial input
3
CP
clock input
4, 5, 6, 7,14, 13, 12, 11
QP0 to QP7
GND
parallel outputs
ground (0 V)
8
9, 10
15
QS1, QS2
OE
serial outputs
output enable input
positive supply voltage
16
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
FUNCTION TABLE
INPUTS
SERIAL
OUTPUTS
PARALLEL OUTPUTS
CP
OE
STR
D
QP0
QPn
QS1
QS2
↑
↓
↑
↑
↑
↓
L
L
H
H
H
H
X
X
L
H
H
H
X
X
X
L
H
H
Z
Z
NC
L
H
NC
Z
Z
NC
QPn - 1
QPn - 1
NC
Q’6
NC
Q’6
Q’6
Q’6
NC
NC
QP7
NC
NC
NC
QP7
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
NC= no change
↑ = LOW-to-HIGH CP transition
↓
= HIGH-to-LOW CP transition
Q’6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the
positive clock edge
Fig.6 Timing diagram.
December 1990
5
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
50
18
14
150
30
26
190
38
33
225
45
38
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
CP to QS1
tPHL/ tPLH propagation delay
CP to QS2
44
16
13
135
27
23
170
34
29
205
41
35
2.0 Fig.7
4.5
6.0
t
t
t
t
t
PHL/ tPLH propagation delay
63
23
18
195
39
33
245
49
42
295
59
50
2.0 Fig.7
4.5
6.0
CP to QPn
PHL/ tPLH propagation delay
STR to QPn
58
21
17
180
36
31
225
45
38
270
54
46
2.0 Fig.8
4.5
6.0
PZH/ tPZL 3-state output enable time
OE to QPn
55
20
16
175
35
30
220
44
37
265
53
45
2.0 Fig.9
4.5
6.0
PHZ/ tPLZ 3-state output disable
time OE to QPn
41
15
12
125
25
21
155
31
26
190
38
32
2.0 Fig.9
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.7
4.5
tW
tW
tsu
tsu
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
strobe pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
set-up time
D to CP
50
10
9
14
5
4
65
13
11
75
15
13
2.0 Fig.10
4.5
6.0
set-up time
CP to STR
100 28
125
25
21
150
30
26
2.0 Fig.8
4.5
6.0
20
17
10
8
December 1990
6
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
th
hold time
D to CP
3
3
3
−6
−2
−2
3
3
3
3
3
3
ns
ns
2.0 Fig.10
4.5
6.0
th
hold time
CP to STR
0
0
0
−14
−5
−4
0
0
0
0
0
0
2.0 Fig.8
4.5
6.0
fmax
maximum clock pulse
frequency
6.0 28
4.8
24
28
4.0
20
24
MHz 2.0 Fig.7
30
35
87
103
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
OE, CP
D
STR
1.50
0.40
1.00
December 1990
8
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to QS1
23
21
25
22
20
21
7
39
36
43
39
35
35
15
49
45
54
49
44
44
19
59
54
65
59
53
53
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.8
4.5 Fig.9
4.5 Fig.9
4.5 Fig.7
4.5 Fig.7
4.5 Fig.8
4.5 Fig.10
4.5 Fig.8
4.5 Fig.10
4.5 Fig.8
t
PHL/ tPLH propagation delay
CP to QS2
t
PHL/ tPLH propagation delay
CP to QPn
tPHL/ tPLH propagation delay
STR to QPn
t
t
t
PZH/ tPZL 3-state output enable time
OE to QPn
PHZ/ tPLZ 3-state output disable time
OE to QPn
THL/ tTLH output transition time
tW
tW
tsu
tsu
th
clock pulse width
HIGH or LOW
16
16
10
20
4
7
20
20
13
25
4
24
24
15
30
4
strobe pulse width
HIGH
5
set-up time
D to CP
4
set-up time
CP to STR
9
hold time
D to CP
0
th
hold time
0
−4
80
0
0
CP to STR
fmax
maximum clock pulse
frequency
30
24
20
MHz 4.5 Fig.7
December 1990
9
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the strobe (STR) to
output (QPn) propagation delays and the
strobe pulse width and the clock set-up and
hold times for the strobe input.
Fig.7 Waveforms showing the clock (CP) to
output (QPn, QS1, QS2) propagation
delays, the clock pulse width and the
maximum clock frequency.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the data set-up and
hold times for the data input (D).
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the 3-state enable and
disable times for input OE.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
10
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