933795010602 [NXP]
IC F/FAST SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24, Bus Driver/Transceiver;
| 型号： | 933795010602 |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24, Bus Driver/Transceiver 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F543
Octal registered transceiver,
non-inverting (3-State)
74F544
Octal registered transceiver,
inverting (3-State)
Product specification
IC15 Data Handbook
1994 Dec 5
Philip s Se m ic ond uc tors
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
74F543
74F544
Octal registered transceiver, non-inverting (3-State)
Octal registered transceiver, inverting 93-State)
FEATURES
FUNCTIONAL DESCRIPTION
The 74F543 and 74F544 contain two sets of eight D-type latches,
with separate input and controls for each set. For data flow from A to
B, for example, the A-to-B Enable (EAB) input must be Low in order
to enter data from A0 - A7 or take data from B0 - B7, as indicated in
the Function Table. With EAB Low, a Low signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent; a
subsequent Low-to-High transition for the LEAB signal puts the
A latches in the storage mode and their outputs no longer change
with the A inputs. With EAB and OEAB both Low, the 3-State
B output buffers are active and display the data present at the
outputs of the A latches. Control of data flow from B to A is similar,
but using the EBA, LEBA, and OEBA inputs.
• Combines74F245 and 74F373 type functions in one chip
• 8-bit octal transceiver with D-type latch
• 74F543 Non-inverting
74F544 Inverting
• Back-to-back registers for storage
• Separate controls for data flow in each direction
• A outputs sink 20mA and source 3mA
• B outputs sink 64mA and source 15mA
• 3-State outputs for bus-oriented applications
• 74F543 available in SSOP Type II package
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
DESCRIPTION
The 74F543 and 74F544 Octal Registered Transceivers contain two
sets of D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB, LEBA) and Output Enable
(OEAB, OEBA) inputs are provided for each register to permit
independent control of inputting and outputting in either direction of
data flow. While the 74F543 has non-inverting data path, the 74F544
inverts data in both directions. The A outputs are guaranteed to sink
24mA, while the B outputs are rated for 64mA.
74F543
74F544
6.0ns
6.5ns
80mA
95mA
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
DRAWING
NUMBER
V
DESCRIPTION
CC
T
= 0°C to +70°C
A
N74F543N,
N74F544N
24-pin plastic skinny DIP (300mil)
SOT222–1
N74F543D,
N74F544D
24-pin plastic SOL
SOT137-1
SOT340-1
24-pin plastic SSOP Type II
74F543DB
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
A0 - A7
DESCRIPTION
Port A, 3-State inputs
3.5/1.0
3.5/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/2.0
1.0/1.0
1.0/1.0
150/40
750/106.7
150/40
750/106.7
70µA/0.6mA
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
15mA/64mA
3.0mA/24mA
15mA/64mA
B0 - B7
OEAB
OEBA
EAB
Port B, 3-State inputs
A-to-B Output Enable input (Active Low)
B-to-A Output Enable input (Active Low)
A-to-B Enable input (Active Low)
B-to-A Enable input (Active Low)
A-to-B Latch Enable input (Active Low)
B-to-A Latch Enable input (Active Low)
Port A, 3-State outputs
74F543
74F544
EBA
LEAB
LEBA
A0 - A7
B0 - B7
A0 - A7
B0 - B7
74F543
74F544
Port B, 3-State outputs
Port A, 3-State outputs
Port B, 3-State outputs
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High State and 0.6mA in the Low state.
2
1994 Dec 5
853-0874 14379
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
PIN CONFIGURATION – 74F543
LOGIC SYMBOL – 74F543
3
4
5
6
7
8
9
10
LEBA
OEBA
1
2
3
4
5
24
V
CC
23 EBA
22
21
20
A0
A1
A2
B0
B1
B2
A0 A1 A2 A3 A4 A5 A6 A7
EAB
11
23
14
1
13
2
OEAB
OEBA
EBA
6
7
19
18
17
16
15
A3
A4
A5
A6
A7
B3
B4
B5
B6
B7
LEAB
LEBA
8
B0 B1 B2 B3 B4 B5 B6 B7
9
10
EAB 11
GND 12
14 LEAB
13 OEAB
22 21 20 19 18 17 16 15
V
= Pin 24
CC
GND = Pin 12
SF00237
SF00238
LOGIC SYMBOL (IEEE/IEC) – 74F543
2
IEN3
23
1
G1
1C5
2EN4
G2
13
11
14
2C6
3
4
22
21
3
5D
6D
4
20
19
5
6
7
8
18
17
16
15
9
10
SF00239
3
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
PIN CONFIGURATION – 74F544
LOGIC SYMBOL – 74F544
3
4
5
6
7
8
9
10
LEBA
OEBA
1
2
3
4
5
24
V
CC
23 EBA
22
21
20
A0
A1
A2
B0
B1
B2
A0 A1 A2 A3 A4 A5 A6 A7
EAB
11
23
14
1
13
2
OEAB
OEBA
EBA
6
7
19
18
17
16
15
A3
A4
A5
A6
A7
B3
B4
B5
B6
B7
LEAB
LEBA
8
B0 B1 B2 B3 B4 B5 B6 B7
9
10
EAB 11
GND 12
14 LEAB
13 OEAB
22 21 20 19 18 17 16 15
V
= Pin 24
CC
GND = Pin 12
SF00240
SF00242
LOGIC SYMBOL (IEEE/IEC) – 74F544
FUNCTION TABLE for 74F543 and 74F544
INPUTS
OUTPUTS
STATUS
2
IEN3
OEXX EXX LEXX DATA 74F543 74F544
23
1
G1
1C5
2EN4
G2
H
X
L
L
L
L
L
L
L
X
H
↑
X
X
L
L
↑
X
X
h
l
Z
Z
Z
Z
Disabled
Disabled
13
11
Z
Z
14
2C6
Disable +
Latch
↑
Z
Z
3
22
21
L
L
L
L
L
h
l
H
L
L
3
5D
Latch +
Display
6D
4
↑
H
L
4
5
L
L
H
H
L
X
H
L
20
19
Transparent
Hold
H
NC
6
NC
18
17
16
15
H
L
h
= High voltage level
= Low voltage level
7
8
= High state must be present one setup time before the
Low-to-High transition of LEXX or EXX (XX=AB or BA)
= Low state must be present one setup time before the
Low-to-High transition of LEXX or EXX (XX=AB or BA)
= Low-to-High transition of LEXX or EXX XX = AB or BA
= Don’t care
9
l
10
↑
X
NC = No change
= High impedance “off” state
SF00241
Z
4
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
LOGIC DIAGRAM FOR 74F543
DETAIL A
22
D
Q
B0
LE
3
Q
D
A0
LE
4
21
20
A1
B1
B2
B3
B4
B5
B6
B7
5
A2
6
19
18
A3
7
DETAIL A X 7
A4
8
17
16
15
A5
9
A6
10
A7
2
OEBA
13
OEAB
23
EBA
11
14
EAB
1
LEBA
V
= Pin 24
CC
LEAB
GND = Pin 12
SF00243
LOGIC DIAGRAM FOR 74F544
DETAIL A
22
D
Q
B0
LE
3
Q
D
A0
LE
4
5
21
20
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
6
7
19
18
DETAIL A X 7
8
17
16
15
9
10
2
OEBA
13
OEAB
23
1
EBA
11
14
EAB
V
= Pin 24
LEBA
CC
GND = Pin 12
LEAB
SF00244
5
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
Input voltage
Input current
-0.5 to +7.0
-0.5 to +7.0
-30 to +5
-0.5 to +5.5
48
V
V
CC
IN
I
IN
mA
V
V
OUT
Voltage applied to output in High output state
A0 - A7, A0 - A7
B0 - B7, B0 - B7
mA
mA
I
Current applied to output in Low output state
OUT
128
°
T
Operating free-air temperature range
Storage temperature
0 to +70
-65 to +150
C
amb
°
T
STG
C
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
CC
V
IH
V
IL
Supply voltage
5.0
5.5
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
0.8
-18
-3
V
I
IK
mA
mA
mA
mA
mA
A0 - A7, A0 - A7
B0 - B7, B0 - B7
A0 - A7, A0 - A7
B0 - B7, B0 - B7
I
High-level output current
OH
OL
-15
24
I
Low-level output current
64
°
T
amb
Operating free-air temperature range
-0
+70
C
6
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN TYP
MAX
"10%V
2.4
V
V
CC
A0 - A7,
A0 - A7
I
= -3mA
= -15mA
= 24mA
= 64mA
V
V
V
= MIN
OH
CC
"5%V
2.7
2.0
2.0
3.4
CC
= MAX
= MIN
V
High-level output voltage
IL
OH
"10%V
V
CC
CC
B0 - B7,
B0 - B7
IH
I
OH
"5%V
V
"10%V
0.35
0.35
0.50
0.50
0.55
0.55
V
CC
CC
A0 - A7,
A0 - A7
I
I
V
V
V
= MIN
OL
CC
"5%V
V
= MAX
V
Low-level output voltage
Input clamp voltage
IL
OL
"10%V
V
CC
CC
B0 - B7,
B0 - B7
= MIN
IH
OL
"5%V
0.42
V
V
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73 –1.2
V
IK
I
OEAB, OEBA, EAB
Others
= MAX, V = 7.0 V
100
1
µA
mA
µA
mA
mA
I
Input current at maximum
input voltage
I
I
= 5.5, V = 5.5V
I
I
High-level input current
= MAX, V = 2.7V
20
IH
I
Others
–0.6
–1.2
I
Low-level input current
V
= MAX, V = 0.5V
CC I
IL
EAB,
EBA
I
+ I
Off-state output current, high-level voltage applied
Off-state output current, Low-level voltage applied
V
V
= MAX, V = 2.7V
70
µA
µA
OZH
IH
CC
O
I
+ I
= MAX, V = 0. 5V
–600
–150
OZH
IL
CC
O
A0 - A7,
A0 - A7
–60
mA
3
I
Short-circuit output current
V
CC
V
CC
V
CC
= MAX
= MAX
= MAX
OS
B0 - B7,
B0 - B7
–100
–225
mA
I
70
95
105
135
135
110
140
135
mA
mA
mA
mA
mA
mA
CCH
74F543
74F544
I
CCL
CCZ
CCH
I
95
I
Supply current (total)
CC
I
I
80
I
105
100
CCL
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under the recommended operating conditions for the applicable
type.
°
2. All typical values are at V = 5V, T
= 25 C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
7
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
AC ELECTRICAL CHARACTERISTICS FOR 74F543
74F543 LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
V
= 5.0V
V
CC
= 5.0V ± 10%
C = 50pF
L
CC
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
3.5
3.0
5.5
5.0
8.5
8.0
3.0
2.5
9.0
8.5
PLH
PHL
Waveform 2
Waveform 2
ns
ns
ns
ns
ns
ns
ns
ns
A to B
n
n
t
t
Propagation delay
B to A
2.5
2.5
4.0
4.5
7.0
7.5
2.5
2.5
7.5
8.0
PLH
PHL
n
n
t
t
Propagation delay
LEBA to A
5.0
4.0
7.0
6.0
10.0
9.0
4.5
4.0
11.0
9.5
PLH
PHL
Waveform NO TAG, 2
Waveform NO TAG, 2
n
t
t
Propagation delay
LEAB to B
6.0
4.5
8.5
6.5
11.5
9.5
5.5
4.0
12.5
10.0
PLH
PHL
n
t
t
Output Enable time
Waveform 4
Waveform 5
2.0
3.5
4.0
5.0
7.5
8.5
1.5
3.0
8.0
9.0
PZH
PZL
OEBA to A or OEAB to B
n
n
n
t
t
Output Disable time
Waveform 4
Waveform 5
1.0
1.5
3.0
4.0
6.5
7.5
1.0
1.0
7.5
8.5
PHZ
PLZ
OEBA to A or OEAB to B
n
t
t
Output Enable time
Waveform 4
Waveform 5
4.5
5.0
7.0
7.0
10.5
10.5
4.0
4.5
11.5
11.0
PZH
PZL
EBA to A or EAB to B
n
n
t
t
Output Disable time
Waveform 4
Waveform 5
2.5
4.5
5.0
7.0
8.5
11.0
2.0
3.0
9.5
12.0
PHZ
PLZ
EBA to A or EAB to B
n
n
AC SETUP REQUIREMENTS FOR 74F543
74F543 LIMITS
T
V
= +25°C
= 5.0V
T
V
CC
= 0°C to +70°C
= 5.0V ± 10%
amb
amb
CC
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
C = 50pF
L
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
A to LEAB or B to LEBA
n n
0.0
2.5
0.0
3.0
s
Waveform 3
ns
ns
ns
t (H)
Hold time, High or Low
A to LEAB or B to LEBA
0.0
1.5
0.0
2.0
h
Waveform 3
Waveform 3
t (L)
h
n
n
t (H)
Setup time, High or Low
A to EAB or B to EBA
1.0
2.5
1.5
3.0
s
t (L)
s
n
n
t (H)
t (L)
h
Hold time, High or Low
A to EAB or B to EBA
Waveform 3
Waveform 3
0.0
1.5
0.0
2.0
h
ns
ns
n
n
t (L)
w
Latch enable pulse width, Low
4.0
4.5
8
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
AC ELECTRICAL CHARACTERISTICS FOR 74F544
74F544 LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
V
= 5.0V
V
CC
= 5.0V ± 10%
C = 50pF
L
CC
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
3.0
3.0
6.5
5.0
9.5
8.0
3.0
3.0
10.5
8.5
PLH
PHL
Waveform NO TAG
Waveform NO TAG, 2
Waveform NO TAG, 2
ns
ns
ns
ns
ns
ns
ns
A to B or B to A
n
n
n
n
t
t
Propagation delay
LEBA to A
4.0
4.0
7.0
7.0
9.5
9.5
4.0
4.0
10.5
10.5
PLH
PHL
n
t
t
Propagation delay
LEAB to B
5.0
4.0
8.0
7.5
11.5
9.5
4.0
4.0
12.5
10.5
PLH
PHL
n
t
t
Output Enable time
Waveform 4
Waveform 5
2.0
3.5
4.0
5.5
7.0
8.5
1.5
3.0
7.5
9.0
PZH
PZL
OEBA to A or OEAB to B
n
n
n
t
t
Output Disable time
Waveform 4
Waveform 5
1.0
1.5
4.0
4.0
6.5
6.5
1.0
1.5
7.0
7.5
PHZ
PLZ
OEBA to A or OEAB to B
n
t
t
Output Enable time
Waveform 4
Waveform 5
4.0
4.5
7.0
8.0
9.5
11.0
3.5
4.5
10.0
12.0
PZH
PZL
EBA to A or EAB to B
n
n
n
t
t
Output Disable time
Waveform 4
Waveform 5
2.5
4.5
5.0
8.5
8.0
11.5
2.5
4.0
9.0
11.5
PHZ
PLZ
EBA to A or EAB to B
n
AC SETUP REQUIREMENTS FOR 74F544
74F544 LIMITS
T
V
= +25°C
= 5.0V
T
V
CC
= 0°C to +70°C
= 5.0V ± 10%
amb
amb
CC
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
C = 50pF
L
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
A to LEAB or B to LEBA
n n
1.5
1.5
2.0
2.5
s
Waveform 3
Waveform 3
Waveform 3
ns
ns
ns
t (H)
Hold time, High or Low
A to LEAB or B to LEBA
1.5
2.0
2.5
2.5
h
t (L)
h
n
n
t (H)
Setup time, High or Low
A to EAB or B to EBA
1.5
1.5
2.5
2.5
s
t (L)
s
n
n
t (H)
t (L)
h
Hold time, High or Low
A to EAB or B to EBA
1.5
2.0
2.0
2.0
h
Waveform 3
Waveform 3
ns
ns
n
n
t (L)
w
Latch enable pulse width, Low
4.0
4.5
9
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
AC WAVEFORMS
V
M
= 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
OEAB, OEBA
EAB, EBA
V
V
M
M
V
V
M
V
M
IN
V
-0.3V
0V
OH
t
t
PHZ
PZH
t
t
PLH
PHL
V
M
B
B
A
A
V
V
M
n
n
V
n,
n,
M
OUT
SF00248
SF00245
Waveform 1. Propagation Delay for Inverting Outputs
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
V
V
M
IN
M
OEAB, OEBA
EAB, EBA
t
t
PHL
V
t
V
M
PLH
M
V
V
V
OUT
M
M
t
PZL
PLZ
B
B
A
A
n
n
n,
n,
V
M
V
+0.3V
OL
SF00246
Waveform 2. Propagation Delay for Non-Inverting Outputs
SF00249
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
A
n
n
n
B
A
B
V
V
V
V
M
M
M
M
n
t (H)
s
t (H)
h
t (L)
s
t (L)
h
V
V
M
M
LEAB, LEBA
EAB, EBA
t
(L)
w
SF00247
Waveform 3. Data Setup Time and Hold Times, and Latch
Enable Pulse Width
10
1994 Dec 5
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
TEST CIRCUIT AND WAVEFORMS
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
R
L
M
M
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
11
1994 Dec 5
Philips Semiconductors
Product specification
Bus transceivers
74F543, 74F544
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
12
1994 Dec 05
Philips Semiconductors
Product specification
Bus transceivers
74F543, 74F544
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
13
1994 Dec 05
Philips Semiconductors
Product specification
Bus transceivers
74F543, 74F544
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
14
1994 Dec 05
Philips Semiconductors
Product specification
Bus transceivers
74F543, 74F544
NOTES
15
1994 Dec 05
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1994
All rights reserved. Printed in U.S.A.
(print code)
Date of release: July 1994
9397-750-05135
Document order number:
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