933824010005 [NXP]

IC HCT SERIES, QUAD 2-INPUT OR GATE, UUC, CHIP ON WAFER, Gate;
933824010005
型号: 933824010005
厂家: NXP    NXP
描述:

IC HCT SERIES, QUAD 2-INPUT OR GATE, UUC, CHIP ON WAFER, Gate

栅 输入元件
文件: 总6页 (文件大小:35K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines  
74HC/HCT32  
Quad 2-input OR gate  
December 1990  
Product specification  
File under Integrated Circuits, IC06  
Philips Semiconductors  
Product specification  
Quad 2-input OR gate  
74HC/HCT32  
FEATURES  
GENERAL DESCRIPTION  
Output capability: standard  
ICC category: SSI  
The 74HC/HCT32 are high-speed Si-gate CMOS devices  
and are pin compatible with low power Schottky TTL  
(LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC/HCT32 provide the 2-input OR function.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
tPHL/ tPLH  
PARAMETER  
CONDITIONS  
UNIT  
HC HCT  
propagation delay nA, nB to nY  
input capacitance  
CL = 15 pF; VCC = 5 V  
6
9
ns  
pF  
pF  
CI  
3.5 3.5  
CPD  
power dissipation capacitance per gate  
notes 1 and 2  
16  
28  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
2
2
PD = CPD × VCC × fi + ∑ (CL × VCC × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
(CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
V
CC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
Philips Semiconductors  
Product specification  
Quad 2-input OR gate  
74HC/HCT32  
PIN DESCRIPTION  
PIN NO.  
1, 4, 9, 12  
SYMBOL  
NAME AND FUNCTION  
1A to 4A  
1B to 4B  
1Y to 4Y  
GND  
data inputs  
2, 5, 10, 13  
data inputs  
3, 6, 8, 11  
data outputs  
7
ground (0 V)  
14  
VCC  
positive supply voltage  
Fig.1 Pin configuration.  
Fig.2 Logic symbol.  
Fig.3 IEC logic symbol.  
December 1990  
3
Philips Semiconductors  
Product specification  
Quad 2-input OR gate  
74HC/HCT32  
FUNCTION TABLE  
INPUTS  
nA  
OUTPUT  
nY  
nB  
L
L
H
H
L
H
L
L
H
H
H
H
Notes  
1. H = HIGH voltage level  
L = LOW voltage level  
Fig.4 Functional diagram.  
Fig.5 Logic diagram 74HC (one gate).  
Fig.6 Logic diagram 74HCT (one gate).  
December 1990  
4
Philips Semiconductors  
Product specification  
Quad 2-input OR gate  
74HC/HCT32  
DC CHARACTERISTICS FOR 74HC  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
AC CHARACTERISTICS FOR 74HC  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
T
amb (°C)  
TEST CONDITIONS  
74HC  
SYMBOL  
PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
40 to +85 40 to +125  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nA, nB to nY  
22  
8
6
90  
18  
15  
115  
23  
20  
135  
27  
23  
ns  
ns  
2.0 Fig.7  
4.5  
6.0  
t
THL/ tTLH output transition time  
19  
7
6
75  
15  
13  
95  
19  
16  
110  
22  
19  
2.0 Fig.7  
4.5  
6.0  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
Note to HCT types  
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.  
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
nA, nB  
1.20  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
T
amb (°C)  
TEST CONDITIONS  
VCC  
74HCT  
SYMBOL  
PARAMETER  
UNIT  
WAVEFORMS  
(V)  
+25  
40 to +85 40 to +125  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nA, nB to nY  
11  
24  
30  
36  
ns  
ns  
4.5 Fig.7  
4.5 Fig.7  
t
THL/ tTLH output transition time  
7
15  
19  
22  
December 1990  
5
Philips Semiconductors  
Product specification  
Quad 2-input OR gate  
74HC/HCT32  
AC WAVEFORMS  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.7 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
December 1990  
6

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