933835860005 [NXP]
IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC, DIE, FF/Latch;
| 型号： | 933835860005 |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC, DIE, FF/Latch 输出元件 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT377
Octal D-type flip-flop with data
enable; positive-edge trigger
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74HC/HCT377
FEATURES
GENERAL DESCRIPTION
• Ideal for addressable register applications
The 74HC/HCT377 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
• Data enable for address and data synchronization
applications
• Eight positive-edge triggered D-type flip-flops
• See “273” for master reset version
• See “373” for transparent latch version
• See “374” for 3-state version
The 74HC/HCT377 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. A common
clock (CP) input loads all flip-flops simultaneously when
the data enable (E) is LOW. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop.
• Output capability: standard
• ICC category: MSI
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
tPHL/ tPLH
PARAMETER
CONDITIONS
UNIT
ns
HC HCT
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V
13
14
53
3.5
20
fmax
CI
77
3.5
20
MHz
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74HC/HCT377
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
E
data enable input (active LOW)
flip-flop outputs
2, 5, 6, 9, 12, 15, 16, 19
Q0 to Q7
D0 to D7
GND
CP
3, 4, 7, 8, 13, 14, 17, 18
data inputs
10
11
20
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74HC/HCT377
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODES
CP
↑
E
l
Dn
h
Qn
H
load “1”
load “0”
↑
l
l
L
hold (do nothing)
↑
X
h
H
X
X
no change
no change
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time
prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I
= LOW voltage level one set-up time
prior to the LOW-to-HIGH CP transition
↑ = LOW-to-HIGH CP transition
X = don’t care
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74HC/HCT377
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
44
16
13
160
32
27
200
40
34
240
48
41
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.6
4.5
6.0
tW
tsu
tsu
th
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
set-up time
Dn to CP
60
12
10
14
5
4
75
15
13
90
18
15
2.0 Fig.7
4.5
6.0
set-up time
E to CP
60
12
10
6
2
2
75
15
13
90
18
15
2.0 Fig.7
4.5
6.0
hold time
Dn to CP
3
3
3
−8
−3
−2
3
3
3
3
3
3
2.0 Fig.7
4.5
6.0
th
hold time
E to CP
4
4
4
−3
−1
−1
4
4
4
4
4
4
2.0 Fig.7
4.5
6.0
fmax
maximum clock pulse
frequency
6
30
35
23
70
83
5
24
28
4
20
24
MHz 2.0 Fig.6
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74HC/HCT377
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
E
CP
Dn
1.50
0.50
0.20
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
17
32
40
48
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
tTHL/ tTLH output transition time
7
15
19
22
tW
tsu
tsu
th
clock pulse width
HIGH or LOW
20
12
22
2
8
25
15
28
2
30
18
33
2
set-up time
Dn to CP
4
set-up time
E to CP
12
−4
−2
48
hold time
Dn to CP
th
hold time
E to CP
3
3
3
fmax
maximum clock pulse
frequency
27
22
18
MHz 4.5 Fig.6
December 1990
6
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74HC/HCT377
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output
transition times and the maximum clock pulse frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the data set-up and hold times from the data input (Dn) and from the data enable input
(E) to the clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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