933981790126 [NXP]

TRANSISTOR 200 mA, 250 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-92, PLASTIC, SPT, SOT-54 VARIANT, 3 PIN, FET General Purpose Small Signal;
933981790126
型号: 933981790126
厂家: NXP    NXP
描述:

TRANSISTOR 200 mA, 250 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-92, PLASTIC, SPT, SOT-54 VARIANT, 3 PIN, FET General Purpose Small Signal

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DISCRETE SEMICONDUCTORS  
DATA SHEET  
BSP254; BSP254A  
P-channel enhancement mode  
vertical D-MOS transistor  
April 1995  
Product specification  
File under Discrete Semiconductors, SC13b  
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
FEATURES  
QUICK REFERENCE DATA  
Direct interface to C-MOS, TTL,  
etc.  
SYMBOL  
PARAMETER  
CONDITIONS MIN. TYP. MAX. UNIT  
VDS  
drain-source  
voltage  
250  
±20  
V
High-speed switching  
No secondary breakdown.  
VGSO  
Yfs  
gate-source  
voltage  
open drain  
V
forward transfer  
admittance  
ID = 200 mA; 100 200  
VDS = 25V  
mS  
DESCRIPTION  
P-channel vertical D-MOS transistor  
in a TO-92 variant envelope and  
intended for use as a line current  
interruptor in relay, high-speed and  
line transformer drivers.  
ID  
drain current (DC)  
drain-source  
on-state resistance ID = 200 mA  
0.2  
A
RDS(on)  
VGS = 10 V;  
10  
15  
Ptot  
total power  
dissipation  
Tamb = 25 °C  
1
W
PINNING - TO-92 variant BSP254  
PIN  
DESCRIPTION  
1
2
3
gate  
d
s
handbook, halfpage  
drain  
1
2
3
source  
g
PINNING - TO-92 variant BSP254A  
MAM147  
PIN  
DESCRIPTION  
source  
1
2
3
gate  
Fig.1 Simplified outline and symbol.  
drain  
April 1995  
2
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
LIMITING VALUES  
In accordance with the Absolute Maximum System (IEC 134)  
SYMBOL  
VDS  
PARAMETER  
drain-source voltage  
CONDITIONS  
MIN.  
MAX.  
250  
UNIT  
V
V
A
A
V GSO  
ID  
gate-source voltage  
drain current  
open drain  
20  
DC  
0.2  
0.6  
1
IDM  
Ptot  
drain current  
peak value  
Tamb = 25 °C (note 1)  
total power dissipation  
storage temperature range  
junction temperature  
W
Tstg  
Tj  
65  
+150  
150  
°C  
°C  
THERMAL RESISTANCE  
SYMBOL  
PARAMETER  
MAX.  
125  
UNIT  
K/W  
Rth j-a  
from junction to ambient (note 1)  
Note  
1. Transistor mounted on printed circuit board, maximum lead length 4 mm,  
mounting pad for drain lead minimum 10 mm x 10 mm.  
MRC238  
1.2  
handbook, halfpage  
P
tot  
(W)  
0.8  
0.4  
0
0
50  
100  
150  
200  
(°C)  
T
amb  
Fig.2 Power derating curve.  
April 1995  
3
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
CHARACTERISTICS  
Tj = 25 °C unless otherwise specified.  
SYMBOL  
V(BR)DSS  
PARAMETER  
CONDITIONS  
VGS = 0  
MIN.  
250  
TYP. MAX. UNIT  
drain-source breakdown voltage  
V
ID = 10 µA  
IDSS  
±IGSS  
VGS(th)  
RDS(on)  
Yfs  
drain-source leakage current  
gate-source leakage current  
gate-source threshold voltage  
drain-source on-resistance  
transfer admittance  
VDS = 200 V  
VGS = 0  
1
µA  
nA  
V
±VGS = 20 V  
VDS = 0  
100  
2.8  
15  
VGS = VDS  
ID = 1 mA  
0.8  
VGS = 10 V  
ID = 200 mA;  
10  
200  
VDS = 25 V  
ID = 200 mA  
100  
mS  
Ciss  
Coss  
Crss  
ton  
input capacitance  
output capacitance  
feedback capacitance  
turn-on time  
note 1  
note 1  
note 1  
note 2  
note 2  
65  
20  
6
90  
30  
15  
10  
30  
pF  
pF  
pF  
ns  
ns  
5
toff  
turn-off time  
20  
Notes  
1. Measured at f = 1 MHz; VDS = 25 V; VGS = 0.  
2. VGS = 0 to 10 V; ID = 250 mA; VDD = 50 V.  
handbook, halfpage  
V
= 50 V  
DD  
handbook, halfpage  
INPUT  
10 %  
90 %  
10 %  
0 V  
I
D
OUTPUT  
10 V  
50 Ω  
90 %  
MBB689  
t
t
off  
on  
MBB690  
Fig.3 Switching times test circuit.  
Fig.4 Input and output waveforms.  
April 1995  
4
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
MDA706  
MDA707  
1  
1  
handbook, halfpage  
handbook, halfpage  
V
= 10 V  
6 V  
GS  
I
I
D
(A)  
D
(A)  
0.8  
0.8  
0.6  
0.4  
0.6  
0.4  
5 V  
4 V  
0.2  
0.2  
3 V  
15  
0
0
0
0
5  
10  
20  
V
25  
(V)  
2  
4  
6  
8  
V
10  
(V)  
DS  
GS  
Fig.5 Typical output characteristics; Tj = 25 °C.  
Fig.6 Typical transfer characteristic; VDS = 10 V;  
Tj = 25 °C.  
MDA734  
MDA708  
3
10  
160  
handbook, halfpage  
handbook, halfpage  
V
= 10 V  
5 V  
GS  
C
(pF)  
I
D
120  
(mA)  
4 V  
2
10  
80  
40  
0
C
iss  
C
C
oss  
rss  
10  
8
12  
16  
20  
24  
R
28  
()  
0
5  
10  
15  
20  
V
25  
(V)  
DS  
DSon  
Fig.7 Typical on-resistance as a function of drain  
Fig.8 Typical capacitances as a function of  
drain-source voltage; VGS = 0; f = 1 MHz;  
Tj = 25 °C.  
current, Tj = 25 °C.  
April 1995  
5
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
MDA710  
MDA711  
2.5  
1.1  
handbook, halfpage  
handbook, halfpage  
k
k
2
1
1.5  
1
0.9  
0.8  
0.5  
0
0.7  
50  
50  
0
50  
100  
150  
0
50  
100  
150  
T (°C)  
T (°C)  
j
j
Fig.9  
Fig.10  
VGS (th ) at Tj  
RDS (on ) at Tj  
k = -----------------------------------------------  
RDS (on ) at 25 °C  
k = -------------------------------------------------  
VGS (th ) at 25 °C  
typical VGS(th) at 1 mA.  
typical RDS(on) at 200 mA/10 V.  
April 1995  
6
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
PACKAGE OUTLINES  
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)  
SOT54 variant  
c
L
2
E
d
A
L
b
1
2
e
1
e
D
3
b
1
L
1
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
L
L
2
1
UNIT  
mm  
A
b
b
c
D
d
E
e
e
L
1
1
max  
max  
5.2  
5.0  
0.48  
0.40  
0.66  
0.56  
0.45  
0.40  
4.8  
4.4  
1.7  
1.4  
4.2  
3.6  
14.5  
12.7  
2.54  
1.27  
2.5  
2.5  
Notes  
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.  
REFERENCES  
OUTLINE  
EUROPEAN  
ISSUE DATE  
PROJECTION  
VERSION  
IEC  
JEDEC  
EIAJ  
97-04-14  
SOT54 variant  
TO-92  
SC-43  
April 1995  
7
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
April 1995  
8
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
NOTES  
April 1995  
9
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
NOTES  
April 1995  
10  
Philips Semiconductors  
Product specification  
P-channel enhancement mode vertical  
D-MOS transistor  
BSP254; BSP254A  
NOTES  
April 1995  
11  
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Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1997  
SCA54  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
137107/00/01/pp12  
Date of release: April 1995  
Document order number: 9397 750 02484  

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