934055815127 [NXP]
TRANSISTOR 100 A, 55 V, 0.005 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247, PLASTIC PACKAGE-3, FET General Purpose Power;
| 型号： | 934055815127 |
| 厂家： | 
NXP |
| 描述： | TRANSISTOR 100 A, 55 V, 0.005 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247, PLASTIC PACKAGE-3, FET General Purpose Power 局域网 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
VDSS = 55 V
ID = 100 A
• Low thermal resistance
• Logic level compatible
RDS(ON) ≤ 4.2 mΩ (VGS = 10 V)
g
RDS(ON) ≤ 4.5 mΩ (VGS = 5 V)
s
RDS(ON) ≤ 5 mΩ (VGS = 4.5 V)
GENERAL DESCRIPTION
PINNING
SOT429 (TO247)
SiliconMAXproductsusethelatest
Philips Trench technology to
achieve the lowest possible
on-state resistance in each
package at each voltage rating.
PIN
DESCRIPTION
1
2
gate
drain
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
3
source
drain
tab
2
1
3
The PSMN004-55W is supplied in
the SOT429 (TO247) conventional
leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
Drain-source voltage
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
55
55
± 15
V
V
V
Drain-gate voltage
Continuous gate-source
voltage
VGSM
ID
Peak pulsed gate-source
voltage
Continuous drain current
Tj ≤ 150 ˚C
-
± 20
V
Tmb = 25 ˚C; VGS = 5 V
Tmb = 100 ˚C; VGS = 5 V
Tmb = 25 ˚C
-
-
-
-
1001
1001
300
300
175
A
A
A
W
˚C
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tmb = 25 ˚C
- 55
1 Maximum continuous current limited by package.
October 1999
1
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS Non-repetitive avalanche
CONDITIONS
MIN.
MAX.
UNIT
Unclamped inductive load, IAS = 100 A;
tp = 100 µs; Tj prior to avalanche = 25˚C;
-
357
mJ
energy
VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to
fig:15
IAS
Non-repetitive avalanche
current
-
100
A
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
-
0.5
K/W
Rth j-a
Thermal resistance junction in free air
to ambient
-
45
-
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
55
-
-
-
-
V
V
voltage
Tj = -55˚C
42
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
1
0.5
1.5
-
-
3.2
3.6
3.8
6.2
0.02 100
0.05
-
2
-
2.3
4.2
4.5
5
V
V
V
mΩ
mΩ
mΩ
mΩ
nA
µA
µA
Tj = 175˚C
Tj = -55˚C
-
-
-
-
-
-
-
-
RDS(ON)
Drain-source on-state
resistance
VGS = 10 V; ID = 25 A
VGS = 5 V; ID = 25 A
VGS = 4.5 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
9.5
IGSS
IDSS
Gate-source leakage current VGS = ±10 V; VDS = 0 V;
Zero gate voltage drain
current
VDS = 55 V; VGS = 0 V;
10
500
Tj = 175˚C
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 100 A; VDD = 44 V; VGS = 5 V
-
-
-
226
36
106
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; RD = 1.2 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
-
-
-
26
-
-
-
-
ns
ns
ns
ns
118
848
336
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
-
-
3.5
4.5
7.5
-
-
-
nH
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
13
1900
1250
-
-
-
nF
pF
pF
October 1999
2
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
100
A
A
V
ISM
VSD
-
-
300
IF = 25 A; VGS = 0 V
IF = 75 A; VGS = 0 V
-
-
0.78
0.92
1.2
-
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 20 V
-
-
150
0.7
-
-
ns
µC
October 1999
3
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
Transient thermal impedance, Zth j-mb (K/W)
Normalised Power Derating, PD (%)
100
1
0.1
D = 0.5
0.2
90
80
70
60
50
40
30
20
10
0.1
0.05
0.02
P
D = tp/T
D
tp
0.01
single pulse
T
0.001
0
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
0
25
50
75
100
125
150
175
Pulse width, tp (s)
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A)
100
90
80
70
60
50
40
30
20
10
0
Normalised Current Derating, ID (%)
10 V
VGS = 10V
Tj = 25 C
100
90
80
70
60
50
40
30
20
10
0
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2 V
0
25
50
75
100
125
150
175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Mounting Base temperature, Tmb (C)
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Peak Pulsed Drain Current, IDM (A)
1000
Drain-Source On Resistance, RDS(on) (Ohms)
0.02
RDS(on) = VDS/ ID
tp = 10 us
2.5 V
2.2 V 2.3 V
2.4 V
2 V
Tj = 25 C
0.018
0.016
0.014
0.012
0.01
2.1 V
100 us
100
1 ms
10 ms
D.C.
0.008
0.006
0.004
0.002
0
10
1
100 ms
5 V
VGS = 10V
1
10
Drain-Source Voltage, VDS (V)
100
0
10
20
30
40
50
60
70
80
90 100
Drain Current, ID (A)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
October 1999
4
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
2.25
100
90
80
70
60
50
40
30
20
10
0
VDS > ID X RDS(ON)
2
1.75
1.5
1.25
1
maximum
typical
minimum
0.75
0.5
0.25
0
175 C
Tj = 25 C
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Drain current, ID (A)
220
200
180
160
140
120
100
80
1.0E-01
Tj = 25 C
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
175 C
minimum
typical
maximum
60
40
20
0
0
0.5
1
1.5
2
2.5
3
0
10
20
30
40
50
60
70
80
90
100
Gate-source voltage, VGS (V)
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
2.4
2.2
2
Capacitances, Ciss, Coss, Crss (pF)
100000
1.8
1.6
1.4
1.2
1
Ciss
10000
1000
100
Coss
Crss
0.8
0.6
0.4
0.2
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
0.1
1
10
100
Junction temperature, Tj (C)
Drain-Source Voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
October 1999
5
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
Gate-source voltage, VGS (V)
15
Maximum Avalanche Current, IAS (A)
1000
ID = 100 A
14
13
12
11
10
9
Tj = 25 C
25 C
100
10
1
VDD = 11 V
8
7
6
5
4
3
2
1
0
VDD = 44 V
Tj prior to avalanche = 150 C
0
40
80 120 160 200 240 280 320 360 400 440
Gate charge, QG (nC)
0.001
0.01
0.1
Avalanche time, tAV (ms)
1
10
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Source-Drain Diode Current, IF (A)
100
VGS = 0 V
90
80
70
60
50
40
175 C
30
Tj = 25 C
20
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Source-Drain Voltage, VSDS (V)
1
1.1 1.2
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
October 1999
6
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
MECHANICAL DATA
Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247
SOT429
α
E
P
A
A
1
β
q
S
R
D
Y
(1)
L
1
Q
b
2
L
1
2
3
c
b
1
w
M
b
e
e
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
β
A
A
b
b
b
2
c
D
E
e
L
L
1
P
Q
q
R
S
w
Y
α
UNIT
mm
1
1
1.9
1.7
1.2
0.9
3.7
3.3
2.6
2.4
7.5
7.1
15.7
15.3
6°
4°
17°
13°
5.3
4.7
2.2
1.8
3.2
2.8
0.9
0.6
21
20
16
15
16
15
4.0
3.6
3.5
3.3
5.45
5.3
0.4
Note
1. Tinning of terminals are uncontrolled within zone L
.
1
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
98-04-07
99-08-04
SOT429
TO-247
Fig.16. SOT429; pin 2 connected to mounting base
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT429 envelope.
3. Epoxy meets UL94 V0 at 1/8".
October 1999
7
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-55W
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
October 1999
8
Rev 1.100
it Q
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PSMN004-55W; N-
channel logic level
TrenchMOS(tm)
transistor
download datasheet
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SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state
resistance in each package at each voltage rating.
Cross-reference
Packages
•
•
End of Life
information
Distributors Go
Here!
The PSMN004-55W is supplied in the SOT429 (TO247) conventional leaded package.
•
•
Features
Models
•
•
SoC solutions
●
●
●
●
●
’Trench’ technology
Very low on-state resistance
Fast switching
Low thermal resistance
Logic level compatible
Applications
●
●
d.c. to d.c. converters
switched mode power supplies
Datasheet
Type number Title
Publication
release date
Datasheet status Page
File Datasheet
count size
(kB)
PSMN004-
55W
N-channel logic level 10/1/1999
TrenchMOS(tm)
Product
specification
8
97
Download
transistor
Parametrics
Type number Package
V
(V) Configuration
I DC(A) R
(mOhm) Q
DS
D
DS(on) gd
(typ)(nC)
4.2@10V
4.5@5V
5@4.5V
SOT429 (TO-247)
PSMN004-55W
55
Single N-channel 100
106
Products, packages, availability and ordering
Type
North
Ordering code Marking/Packing Package Device status Buy online
Discretes
number
American (12NC)
type
packing info
number
Standard Marking
9340 558 15127 * Horizontal, Rail
Pack
SOT429
PSMN004- PSMN004-
55W 55W
Full production
(TO-247)
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