935007620602 [NXP]

IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, 0.300 INCH, PLASTIC, SOT-38-4, DIP-16, FF/Latch;
935007620602
型号: 935007620602
厂家: NXP    NXP
描述:

IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, 0.300 INCH, PLASTIC, SOT-38-4, DIP-16, FF/Latch

光电二极管 输出元件 逻辑集成电路 触发器
文件: 总12页 (文件大小:97K)
中文:  中文翻译
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INTEGRATED CIRCUITS  
74F50109  
Synchronizing dual J-K positive  
edge-triggered flip-flop with metastable  
immune characteristics  
Product specification  
IC15 Data Handbook  
1990 Sep 14  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
Synchronizing dual J–K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
FEATURE  
PIN CONFIGURATION  
Metastable immune characteristics  
1
2
3
4
5
16  
15  
14  
V
RD0  
J0  
CC  
Output skew guaranteed less than 1.5ns  
RD1  
J1  
High source current (I = 15mA) ideal for clock driver  
OH  
K0  
applications  
CP0  
13 K1  
Pinout compatible with 74F109  
12  
11  
SD0  
Q0  
CP1  
SD1  
See 74F5074 for synchronizing dual D-type flip-flop  
See 74F50728 for synchronizing cascaded D-type flip-flop  
6
7
8
10 Q1  
Q0  
See 74F50729 for synchronizing dual D-type flip-flop with  
9
GND  
Q1  
edge-triggered set and reset  
SF00598  
TYPE  
TYPICAL f  
TYPICAL SUPPLY  
CURRENT( TOTAL)  
max  
74F50109  
150MHz  
22mA  
LOGIC SYMBOL  
2
14  
3 13  
ORDERING INFORMATION  
ORDER CODE  
COMMERCIAL RANGE  
= 5V ±10%,  
4
5
CP0  
J1  
K1  
K0  
J0  
SD0  
RD0  
CP1  
SD1  
RD1  
DESCRIPTION  
PKG DWG #  
V
CC  
1
T
amb  
= 0°C to +70°C  
12  
11  
15  
16–pin plastic DIP  
16–pin plastic SO  
N74F50109N  
N74F50109D  
SOT38-4  
Q0 Q0 Q1 Q1  
SOT109-1  
INPUT AND OUTPUT LOADING  
AND FAN OUT TABLE  
6
7
10  
9
V
= Pin 16  
CC  
GND = Pin 8  
SF00599  
74F (U.L.)  
HIGH/  
LOW  
LOAD  
VALUE  
HIGH/LOW  
PINS  
DESCRIPTION  
IEC/IEEE SYMBOL  
J0, J1  
J inputs  
K inputs  
1.0/0.417 20µA/250µA  
1.0/0.417 20µA/250µA  
K0, K1  
2
4
3
1
5
Clock inputs  
(active rising edge)  
1J  
6
7
CP0, CP1  
SD0, SD1  
RD0, RD1  
1.0/0.033  
1.0/0.033  
20µA/20µA  
20µA/20µA  
C1  
Set inputs  
(active low)  
1K  
R
Reset inputs  
(active low)  
S
1.0/0.033  
750/33  
20µA/20µA  
14  
12  
13  
15  
11  
2J  
Q0, Q1, Q0, Q1 Data outputs  
15mA/20mA  
10  
9
C2  
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high  
state and 0.6mA in the low state.  
2K  
R
S
SF00600  
2
September 14, 1990  
853-1388 00422  
Philips Semiconductors  
Product specification  
Synchronizing dual J–K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
device–under–test can be often be driven into a metastable state. If  
the Q output is then used to trigger a digital scope set to infinite  
persistence the Q output will build a waveform.0 An experiment was  
run by continuously operating the devices in the region where  
metastability will occur.  
LOGIC DIAGRAM  
7, 9  
Q
6, 10  
Q
When the device–under–test is a 74F74 (which was not designed  
with metastable immune characteristics) the waveform will appear  
as in Fig. 2.  
Fig. 2 shows clearly that the Q output can vary in time with respect  
to the Q trigger point. This also implies that the Q or Q output  
waveshapes may be distorted. This can be verified on an analog  
scope with a charge plate CRT. Perhaps of even greater interest are  
the dots running along the 3.5V volt line in the upper right hand  
quadrant. These show that the Q output did not change state even  
though the Q output glitched to at least 1.5 volts, the trigger point of  
the scope.  
3, 13  
K
2, 14  
J
4, 12  
CP  
5, 11  
SD  
1, 15  
RD  
When the device–under–test is a metastable immune part, such as  
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q  
output will appear as in Fig. 3. The 74F5074 Q output will not vary  
with respect to the Q trigger point even when the a part is driven into  
a metastable state. Any tendency towards internal metastability is  
resolved by Philips Semiconductors patented circuitry. If a  
V
= Pin 16  
CC  
GND = Pin 8  
SF00601  
metastable event occurs within the flop the only outward  
manifestation of the event will be an increased clock–to–Q/Q  
propagation delay. This propagation delay is, of course, a function of  
DESCRIPTION  
The 74F50109 is a dual positive edge-triggered JK-type flip-flop  
featuring individual J, K, clock, set, and reset inputs; also true and  
complementary outputs.  
the metastability characteristics of the part defined by τ and T  
0.  
The metastability characteristics of the 74F5074 and related part  
types represent state–of–the–art TTL technology.  
Set (SD) and reset (RD) are asynchronous active low inputs and  
operate independently of the clock (CP) input.  
After determining the T and t of the flop, calculating the mean time  
0
The J and K are edge–triggered inputs which control the state  
changes of the flip–flops as described in the function table.  
The J and K inputs must be stable just one setup time prior to the  
between failures (MTBF) is simple. Suppose a designer wants to  
use the 74F50729 for synchronizing asynchronous data that is  
arriving at 10MHz (as measured by a frequency counter), has a  
clock frequency of 50MHz, and has decided that he would like to  
sample the output of the 74F50109 10 nanoseconds after the clock  
edge. He simply plugs his number into the equation below:  
low–to–high transition of the clock for guaranteed propagation  
delays. The JK design allows operation as a D flip–flop by tying J  
and K inputs together.  
The 74F50109 is designed so that the outputs can never display a  
metastable state due to setup and hold time violations. If setup time  
and hold time are violated the propagation delays may be extended  
beyond the specifications but the outputs will not glitch or display a  
metastable state. Typical metastability parameters for the 74F50109  
(t’/t)  
MTBF = e / T f f  
o C I  
In this formula, f is the frequency of the clock, f is the average  
input event frequency, and t’ is the time after the clock pulse that the  
output is sampled (t’ < h, h being the normal propagation delay). In  
C
I
6
this situation the f will be twice the data frequency of 20 MHz  
are: τ 135ps and τ 9.8 X 10 sec where τ represents a function  
I
because input events consist of both of low and high transitions.  
of the rate at which a latch in a metastable state resolves that  
15  
2
Multiplying f by f gives an answer of 10 Hz . From Fig. 4 it is  
condition and T represents a function of the measurement of the  
I
C
0
10  
clear that the MTBF is greater than 10 seconds. Using the above  
formula MTBF is 1.51 X 10 seconds or about 480 years.  
propensity of a latch to enter a metastable state.  
10  
METASTABLE IMMUNE CHARACTERISTICS  
Philips Semiconductors uses the term ’metastable immune’ to  
describe characteristics of some of the products in its FAST family.  
Specifically the 74F50XXX family presently consist of 4 products  
which displays metastable immune characteristics. This term means  
that the outputs will not glitch or display an output anomaly under  
any circumstances including setup and hold time violations.  
TRIGGER  
DIGITAL  
SIGNAL GENERATOR  
SIGNAL GENERATOR  
D
Q
Q
SCOPE  
CP  
INPUT  
SF00586  
This claim is easily verified on the 74F5074. By running two  
independent signal generators (see Fig. 1) at nearly the same  
frequency (in this case 10MHz clock and 10.02 MHz data) the  
Figure 1. Test setup  
3
September 14, 1990  
Philips Semiconductors  
Product specification  
Synchronizing dual J–K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
COMPARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS  
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive  
SF00602  
Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated  
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive  
SF00588  
Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated  
4
September 14, 1990  
Philips Semiconductors  
Product specification  
Synchronizing dual J–K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’  
6
8
10  
12  
10  
10  
10  
10  
14  
15  
10  
12  
11  
10  
9
10  
10  
10  
10  
10  
10  
10  
10 = f f  
C I  
10,000 years  
100 years  
MTBF in seconds  
8
one year  
7
6
one week  
7
8
9
10  
t’ in nanoseconds  
SF00589  
8
NOTE: V = 5V, T  
= 25°C, τ =135ps, To = 9.8 X 10 sec  
CC  
amb  
Figure 4.  
TYPICAL VALUES FOR τ AND T AT VARIOUS V S AND TEMPERATURES  
0
CC  
T
amb  
= 0°C  
T
amb  
= 25°C  
T = 70°C  
amb  
V
CC  
τ
T
0
τ
T
0
τ
T
0
9
6
5
5.5V  
5.0V  
4.5V  
125ps  
115ps  
115ps  
1.0 X 10 sec  
138ps  
135ps  
132ps  
5.4 X 10 sec  
160ps  
167ps  
175ps  
1.7 X 10 sec  
10  
6
4
1.3 X 10 sec  
9.8 X 10 sec  
3.9 X 10 sec  
13  
8
4
3.4 X 10 sec  
5.1 X 10 sec  
7.3 X 10 sec  
FUNCTION TABLE  
NOTES:  
H = High–voltage level  
INPUTS  
OUTPUTS  
OPERATING  
SD RD CP  
J
X
X
X
X
h
h
l
K
X
X
X
X
l
Q
H
L
Q
L
MODE  
h
=
High–voltage level one setup time prior to  
low–to–high clock transition  
Low–voltage level  
Low–voltage level one setup time prior to  
low–to–high clock  
L
H
L
H
L
X
X
X
Asynchronous set  
L
l
=
=
H
H
q
Asynchronous reset  
Undetermined*  
Hold  
L
H
q
transition  
q
=
Lower case indicate the state of the referenced  
output prior to the low–to–high clock transition  
Don’t care  
H
H
H
H
H
H
H
H
H
H
q
q
Toggle  
X
*
=
=
=
=
Low–to–high clock transition  
h
l
H
L
L
Load ”1” (set)  
Load ”0” (reset)  
Hold ’no change”  
Not low–to–high clock transition  
Both outputs will be high if both SD and RD go low  
simultaneously  
H
q
l
h
q
5
September 14, 1990  
Philips Semiconductors  
Product specification  
Synchronizing dual J–K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
ABSOLUTE MAXIMUM RATINGS  
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the  
operating free air temperature range.)  
SYMBOL  
PARAMETER  
RATING  
–0.5 to +7.0  
–0.5 to +7.0  
–30 to +5  
UNIT  
V
V
CC  
V
IN  
Supply voltage  
Input voltage  
Input current  
V
I
IN  
mA  
V
I
Voltage applied to output in high output state  
Current applied to output in low output state  
–0.5 to V  
V
OUT  
CC  
40  
mA  
°C  
°C  
OUT  
T
amb  
Operating free air temperature range  
Storage temperature range  
0 to +70  
T
stg  
–65 to +150  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
LIMITS  
UNIT  
MIN  
4.5  
NOM  
MAX  
V
Supply voltage  
5.0  
5.5  
V
V
CC  
IH  
IL  
V
V
High–level input voltage  
Low–level input voltage  
Input clamp current  
2.0  
0.8  
–18  
–1  
V
I
I
I
mA  
mA  
mA  
Ik  
High–level output current  
Low–level output current  
OH  
OL  
20  
T
amb  
Operating free air temperature range  
0
+70  
°C  
DC ELECTRICAL CHARACTERISTICS  
(Over recommended operating free-air temperature range unless otherwise noted.)  
SYMBOL  
PARAMETER  
TEST  
LIMITS  
UNIT  
1
2
CONDITIONS  
MIN TYP  
MAX  
V
High–level output voltage  
V
= MIN, V  
=
I
OH  
= MAX  
2.5  
2.7  
V
V
±10%V  
±5%V  
OH  
CC  
IL  
IL  
CC  
MAX,  
V
IH  
= MIN  
3.4  
CC  
V
CC  
= MIN, V  
=
V
OL  
Low–level output voltage  
I
OL  
= MAX  
0.30  
0.30  
0.50  
0.50  
V
±10%V  
CC  
CC  
MAX,  
V
V
V
V
V
V
V
V
= MIN  
V
±5%V  
IH  
V
IK  
Input clamp voltage  
= MIN, I = I  
IK  
-0.73 -1.2  
100  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
I
I
I
I
Input current at maximum input voltage  
High–level input current  
= MAX, V = 7.0V  
µA  
µA  
µA  
µA  
mA  
mA  
I
I
= MAX, V = 2.7V  
20  
IH  
IL  
I
Low–level input current  
Jn, Kn  
= MAX, V = 0.5V  
-250  
I
CPn, SDn, RDn  
= MAX, V = 0.5V  
-20  
I
3
I
I
Short circuit output current  
= MAX  
= MAX  
-60  
-150  
OS  
4
Supply current (total)  
22  
32  
CC  
NOTES:  
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.  
2. All typical values are at V = 5V, T  
= 25°C.  
amb  
CC  
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold  
OS  
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting  
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any  
sequence of parameter tests, I tests should be performed last.  
OS  
4. Measure I with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.  
CC  
6
September 14, 1990  
Philips Semiconductors  
Product specification  
Synchronizing dual J–K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
AC ELECTRICAL CHARACTERISTICS  
LIMITS  
T
amb  
= +25°C  
T
amb  
= 0°C to +70°C  
V
CC  
= +5.0V ± 10%  
SYMBOL  
PARAMETER  
TEST  
V
CC  
= +5.0V  
UNIT  
CONDITION  
C = 50pF,  
L
C = 50pF,  
L
R = 500Ω  
L
R = 500Ω  
L
MIN  
TYP  
MAX  
MIN  
MAX  
f
Maximum clock frequency  
Waveform 1  
Waveform 1  
130  
150  
90  
ns  
ns  
max  
t
t
Propagation delay  
CPn to Qn or Qn  
2.0  
2.0  
3.8  
3.8  
6.0  
6.0  
2.0  
2.0  
6.5  
6.5  
PLH  
PHL  
t
t
Propagation delay  
SDn, RDn to Qn or Qn  
3.5  
3.5  
5.5  
5.5  
8.0  
8.0  
3.0  
3.0  
8.5  
8.5  
PLH  
PHL  
Waveform 2  
Waveform 4  
ns  
ns  
1, 2  
t
Output skew  
1.5  
1.5  
sk(o)  
NOTES:  
1. | t actual – t actual| for any output compared to any other output where N and M are either LH or HL.  
PN  
PM  
2. Skew times are valid only under same test conditions (temperature, V , loading, etc.,).  
CC  
AC SETUP REQUIREMENTS  
LIMITS  
T
= +25°C  
= +5.0V  
T
= 0°C to +70°C  
= +5.0V ± 10%  
amb  
amb  
V
SYMBOL  
PARAMETER  
TEST  
V
UNIT  
CC  
CC  
CONDITION  
C = 50pF,  
L
C = 50pF,  
L
R = 500Ω  
L
R = 500Ω  
L
MIN  
TYP  
MAX  
MIN  
MAX  
t
t
(H)  
(L)  
Setup time, high or low  
Jn, Kn to CPn  
1.5  
1.5  
2.0  
2.0  
su  
su  
Waveform 1  
Waveform 1  
ns  
ns  
t (H)  
Hold time, high or low  
Jn, Kn to CPn  
1.0  
1.0  
1.5  
1.5  
h
t (L)  
h
t
t
(H)  
(L)  
CPn pulse width,  
high or low  
3.0  
4.0  
3.5  
5.0  
w
w
Waveform 1  
Waveform 2  
Waveform 3  
ns  
ns  
ns  
t
t
(L)  
SDn or RDn pulse width, low  
3.5  
3.0  
4.0  
3.5  
w
Recovery time  
SDn or RDn to CP  
rec  
7
September 14, 1990  
Philips Semiconductors  
Product specification  
Synchronizing dual J–K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
AC WAVEFORMS  
t
(L)  
Jn, Kn  
w
V
t
V
V
V
M
M
M
M
SDn  
RDn  
V
V
M
M
t
(H)  
t (H)  
h
(L)  
t (L)  
h
su  
su  
1/f  
M
max  
t
(L)  
w
V
V
M
M
CPn  
Qn  
V
V
M
V
M
t
(H)  
w
t
t
PHL  
PLH  
t
(L)  
t
PHL  
w
t
PLH  
Qn  
Qn  
V
V
V
M
M
M
V
V
M
M
M
t
t
PLH  
PHL  
t
t
PHL  
PLH  
V
M
V
M
V
Qn  
SF00050  
SF00139  
Waveform 2. Propagation delay for set and reset to output,  
set and reset pulse width  
Waveform 1. Propagation delay for data to output, data  
setup time and hold times, and clock  
width, and maximum clock frequency  
V
Qn, Qn  
M
t
sk(o)  
SDn or RDn  
V
M
t
Qn, Qn  
rec  
V
M
V
CPn  
M
SF00590  
Waveform 4. Output skew  
SF00603  
Waveform 3. Recovery time for set or reset to output  
NOTES:  
For all waveforms, V = 1.5V.  
M
The shaded areas indicate when the input is permitted to change for  
predictable output performance.  
TEST CIRCUIT AND WAVEFORM  
t
AMP (V)  
0V  
V
w
CC  
90%  
90%  
NEGATIVE  
PULSE  
V
V
M
M
10%  
10%  
V
V
OUT  
IN  
PULSE  
GENERATOR  
D.U.T.  
t
t )  
t
t )  
THL ( f  
TLH ( r  
R
C
R
L
t
t )  
T
L
t
t )  
TLH ( r  
THL ( f  
AMP (V)  
0V  
90%  
M
90%  
POSITIVE  
PULSE  
V
V
M
10%  
10%  
Test Circuit for Totem-Pole Outputs  
DEFINITIONS:  
t
w
Input Pulse Definition  
INPUT PULSE REQUIREMENTS  
R
L
C
L
R
T
=
=
=
Load resistor;  
see AC ELECTRICAL CHARACTERISTICS for value.  
Load capacitance includes jig and probe capacitance;  
see AC ELECTRICAL CHARACTERISTICS for value.  
family  
V
rep. rate  
t
w
t
t
THL  
amplitude  
3.0V  
M
TLH  
Termination resistance should be equal to Z  
pulse generators.  
of  
OUT  
2.5ns 2.5ns  
74F  
1.5V  
1MHz  
500ns  
SF00006  
8
September 14, 1990  
Philips Semiconductors  
Product specification  
Synchronizing dual J-K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
DIP16: plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
9
1990 Sep 14  
Philips Semiconductors  
Product specification  
Synchronizing dual J-K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
10  
1990 Sep 14  
Philips Semiconductors  
Product specification  
Synchronizing dual J-K positive edge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
NOTES  
11  
1990 Sep 14  
Philips Semiconductors  
Product specification  
Synchronizing dual J-K positiveedge-triggered  
flip-flop with metastable immune characteristics  
74F50109  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
print code  
Date of release: 10-98  
9397-750-05214  
Document order number:  
Philips  
Semiconductors  

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