935069190112 [NXP]
IC ABT SERIES, 10 1-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24, Bus Driver/Transceiver;
| 型号： | 935069190112 |
| 厂家： | 
NXP |
| 描述： | IC ABT SERIES, 10 1-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24, Bus Driver/Transceiver 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总6页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT821
extra data width for wider data/address paths of buses carrying
parity.
FEATURES
• High speed parallel registers with positive edge-triggered D-type
flip-flops
The 74ABT821 is a buffered 10-bit wide version of the
74ABT374/74ABT534 functions.
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
The 74ABT821 is a 10-bit, edge triggered register coupled to ten
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
and 200 V per Machine Model
• Power-up 3-State
• Power-up Reset
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
DESCRIPTION
The active Low Output Enable (OE) controls all ten 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in high impedance ”off” state, which means they will neither drive
nor load the bus.
The 74ABT821 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT821 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
CP to Qn
PLH
PHL
C = 50pF; V = 5V
4.6
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
4
7
pF
pF
nA
IN
I
C
Outputs disabled; V = 0V or V
O CC
OUT
CCZ
I
Outputs disabled; V =5.5V
500
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT821 N
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT821 N
74ABT821 D
74ABT821 DB
74ABT821 PW
24-Pin plastic SO
74ABT821 D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT821 DB
74ABT821PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
24
Output enable input
(active-Low)
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
V
CC
1
OE
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
D0-D9
Q0-Q9
Data inputs
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
Data outputs
Clock pulse input (active
rising edge)
TOP VIEW
13
CP
10
20
GND
Ground (0V)
V
CC
Positive supply voltage
D8 10
D9 11
15
14
13
Q8
Q9
CP
GND 12
SA00223
1
1995 Sep 06
853-1616 15703
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT821
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
EN
C2
13
2
3
4
5
6
7
8
9
10 11
2
3
4
5
6
7
8
9
23
2D
1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
22
21
20
19
18
17
16
15
14
13
1
CP
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
10
11
SA00224
SA00225
FUNCTION TABLE
INPUTS
INTERNAL
REGISTER
OUTPUTS
Q0 – Q9
OPERATING MODE
OE
CP
Dn
L
L
↑
↑
l
h
L
H
L
H
Load and read register
Hold
L
↑
X
NC
NC
H
H
↑
↑
X
Dn
NC
Dn
Z
Z
Disable outputs
H
h
=
=
High voltage level
NC= No change
High voltage level one set-up time
prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time
prior to the Low-to-High clock transition
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
Low to High clock transition
L
l
=
=
↑
Not a Low-to-High clock transition
LOGIC DIAGRAM
D0
2
D1
D2
D3
5
D4
D5
D6
D7
D8
10
D9
11
3
4
6
7
8
9
D
D
D
D
D
D
D
D
D
D
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP Q
13
1
CP
OE
23
Q0
22
Q1
21
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q2
Q9
SA00226
2
1995 Sep 06
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT821
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
3
1995 Sep 06
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT821
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low-level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = GND or V
CC
0.13
V
O
I
3
voltage
I
Input leakage current
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
±1.0
±1.0
µA
µA
I
CC
I
I
Power-off leakage current
= 0.0V; V or V 4.5V
±100
±100
≤
I
OFF
CC
O
Power-up/down 3-State
output current
V
CC
V
OE
= 2.0V; V = 0.5V; V = GND or V
;
O
I
CC
I
/I
±5.0
±50
±50
µA
PU PD
4
= V
CC
I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
OZL
IH
I
= 5.5V; V = 5.5V; V = GND or V
O I
CEX
CC
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–100
0.5
–180
250
38
–50
–180
250
38
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
25
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
mA
CC
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. For V = 2.1V to V = 5V " 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Typ
Max
f
Maximum clock frequency
1
1
125
185
125
ns
ns
MAX
t
t
Propagation delay
CP to Qn
2.1
2.8
4.1
4.6
5.6
6.2
2.1
2.8
6.2
6.7
PLH
PHL
t
t
Output enable time
to High and Low level
3
4
1.0
2.2
3.0
4.1
4.5
5.6
1.0
2.2
5.3
6.3
PZH
PZL
ns
ns
t
t
Output disable time
from High and Low level
3
4
2.7
2.8
4.7
4.6
6.2
6.1
2.7
2.8
6.7
6.5
PHZ
PLZ
4
1995 Sep 06
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT821
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
Dn to CP
2.1
2.1
0.5
0.3
2.1
2.1
s
2
2
1
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
1.3
1.3
0.0
–0.3
1.3
1.3
h
t (L)
h
t (H)
CP pulse width
High or Low
2.9
3.8
1.8
2.8
2.9
3.8
w
t (L)
w
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
V
V
V
V
M
Dn
CP
1/f
M
M
M
MAX
t (H)
s
t (H)
h
t (L)
s
t (L)
h
CP
V
V
M
M
t
(H)
t
(L)
W
W
V
V
M
M
t
t
PLH
PHL
V
Q
n
V
M
M
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00107
Waveform 2. Data Setup and Hold Times
SA00159
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
OE
V
V
M
M
t
t
PLZ
PZL
V
V
M
OE
Qn
M
t
V
M
Qn
t
V
+0.3V
OL
PZH
PHZ
0V
V
–0.3V
0V
OH
V
M
SA00067
Waveform 4. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
SA00066
Waveform 3. 3–State Output Enable Time to High Level and
Output Disable Time from High Level
5
1995 Sep 06
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT821
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
)
(t )
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
6
1995 Sep 06
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