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935069850112 [NXP]

IC SPECIALTY CONSUMER CIRCUIT, PDIP52, 0.600 INCH, PLASTIC, SOT-247-1, SDIP-52, Consumer IC:Other;
935069850112
型号： 935069850112
厂家： NXP    NXP
描述：

IC SPECIALTY CONSUMER CIRCUIT, PDIP52, 0.600 INCH, PLASTIC, SOT-247-1, SDIP-52, Consumer IC:Other

光电二极管
文件： 总47页 (文件大小：250K)
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INTEGRATED CIRCUITS  
DATA SHEET  
TDA8376; TDA8376A  
I2C-bus controlled PAL/NTSC TV  
processors  
1996 Jan 26  
Objective specification  
File under Integrated Circuits, IC02  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
CONTENTS  
1
2
3
4
5
6
7
FEATURES  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
ORDERING INFORMATION  
BLOCK DIAGRAM  
PINNING  
FUNCTIONAL DESCRIPTION  
7.1  
7.2  
Video switches  
Integrated video filters, peaking and black  
stretcher  
7.3  
7.4  
7.5  
Synchronization circuit  
Colour decoder  
RGB output circuit and black-current  
stabilization  
8
I2C-BUS SPECIFICATION  
8.1  
8.2  
Start-up procedure  
Inputs  
8.2.1  
8.2.2  
Input control bits  
Output control bits  
9
LIMITING VALUES  
10  
11  
11.1  
12  
13  
THERMAL CHARACTERISTICS  
QUALITY SPECIFICATION  
Latch-up  
CHARACTERISTICS  
TEST AND APPLICATION INFORMATION  
13.1  
13.2  
East-West output stage  
Adjustment of geometry control parameters  
14  
15  
PACKAGE OUTLINES  
SOLDERING  
15.1  
Introduction  
15.2  
SDIP  
15.2.1  
15.2.2  
15.3  
Soldering by dipping or by wave  
Repairing soldered joints  
QFP  
15.3.1  
15.3.2  
15.3.3  
Reflow soldering  
Wave soldering  
Repairing soldered joints  
16  
17  
18  
DEFINITIONS  
LIFE SUPPORT APPLICATIONS  
PURCHASE OF PHILIPS I2C COMPONENTS  
1996 Jan 26  
2
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
1
FEATURES  
2
GENERAL DESCRIPTION  
• Source selection with 2 CVBS inputs and a Y/C (or extra  
CVBS) input  
The TDA8376 and TDA8376A are alignment-free I2C-bus  
controlled video processors which contain a PAL/NTSC  
colour decoder, luminance processor, sync processor,  
RGB-control and deflection processor. The circuits have  
been designed for use with the baseband chrominance  
delay line TDA4665 and for DC-coupled vertical and  
East-West (E-W) output stages. Both ICs are pin  
compatible. The TDA8376A has a flexible horizontal and  
vertical zoom possibility for 16 : 9 applications.  
• Output signals of the video switch circuit for the teletext  
decoder and a Picture-In-Picture (PIP) processor  
• Video identification circuit which is independent of the  
synchronization for stable On Screen Display (OSD)  
under ‘no-signal’ conditions  
• Integrated chrominance trap with pre-shoot  
compensation and bandpass filters (automatically  
calibrated)  
The supply voltage for the ICs is 8 V. The ICs are available  
in an SDIP package with 52 pins and in a QFP package  
with 64 pins (see Chapter 4).  
• Integrated luminance delay line  
• Asymmetrical peaking in the luminance channel with a  
(defeatable) noise coring function  
The pin numbers indicated in this document are  
referenced to the SDIP52; SOT247-1 package; unless  
otherwise indicated.  
• Black stretcher circuit in the luminance channel  
• PAL/NTSC colour decoder with automatic search  
system  
• Easy interfacing with the TDA8395 (SECAM decoder)  
for multistandard applications  
• RGB control circuit with black-current stabilization and  
white point adjustment; to obtain a good grey scale  
tracking the black-current ratio of the 3 guns depends on  
the white point adjustment  
• Two linear RGB inputs and fast blanking  
• Horizontal synchronization with two control loops and  
alignment-free horizontal oscillator  
• Vertical count-down circuit  
• Geometry correction by modulation of the vertical and  
E-W drive  
• Vertical and horizontal zoom possibility for 16 : 9  
applications (TDA8376A only)  
• I2C-bus control of various functions  
• Low dissipation (700 mW)  
• Small amount of peripheral components compared with  
competition ICs  
• Y, U and V inputs and outputs.  
1996 Jan 26  
3
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
3
QUICK REFERENCE DATA  
SYMBOL  
PARAMETER  
MIN.  
TYP. MAX. UNIT  
Supply  
VP  
supply voltage  
supply current  
−
8.0  
75  
−
−
V
IP  
−
mA  
Input voltages  
V9,13(p-p)  
V27(p-p)  
CVBS input voltage (peak-to-peak value)  
−
−
−
1.0  
1.0  
0.3  
−
−
−
V
V
V
S-VHS luminance input voltage (peak-to-peak value)  
V6(p-p)  
S-VHS chrominance input voltage (burst amplitude) (peak-to-peak  
value)  
Vi(p-p)  
RGB input voltage (peak-to-peak value)  
−
0.7  
−
V
Output voltages  
V38(p-p)  
TXT output voltage (peak-to-peak value)  
−
−
−
−
−
1.0  
1.0  
525  
675  
2.0  
−
−
−
−
−
V
V11(p-p)  
PIP output voltage (peak-to-peak value)  
V
V30(p-p)  
−(R−Y) output voltage (peak-to-peak value)  
−(B−Y) output voltage (peak-to-peak value)  
RGB output signal voltage amplitudes (peak-to-peak value)  
mV  
mV  
V
V29(p-p)  
V19,20,21(p-p)  
Output currents  
I40  
horizontal output current  
10  
1
−
−
−
−
−
−
mA  
mA  
mA  
I47,48  
I46  
vertical output current  
E-W drive output current  
0.5  
4
ORDERING INFORMATION  
PACKAGE  
TYPE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
TDA8376  
SDIP52  
QFP64  
plastic shrink dual in-line package; 52 leads (600 mil)  
SOT247-1  
SOT319-2  
TDA8376AH  
plastic quad flat package; 64 leads (lead length 1.95 mm);  
body 14 × 20 × 2.8 mm  
1996 Jan 26  
4
  g
FBI  
PH2LF  
V
(+8 V)  
SCO  
P2  
V
(+8 V)  
SCL  
3
SDA  
4
HOUT  
40  
P1  
DEC  
BG  
DEC  
DIG  
PH1LF  
8
37  
44  
5
1
43 41 39  
VCO  
AND  
CONTROL  
2nd LOOP AND  
HORIZONTAL  
OUTPUT  
2
46  
49  
EW  
GEOMETRY  
I C-BUS  
EWD  
TRANSCEIVER  
EHTO  
VDR  
ref  
47  
48  
SYNC  
SEPARATOR  
AND 1st LOOP  
HORIZONTAL/  
VERTICAL  
DIVIDER  
CONTROL DACs  
16 x 6 bits  
VERTICAL  
GEOMETRY  
(p)  
VDR  
(n)  
2 x 4 bits  
50  
51  
VSC  
I
ref  
2
C
VERTICAL  
SYNC  
SEPARATOR  
BLK  
BLACK  
STRETCHER  
VIDEO  
IDENTIFICATION  
BLACK  
CURRENT  
STABILIZER  
18  
TDA8376(A)  
BLKIN  
BCLIN  
WHITE  
POINT  
ref  
BRI CONTR  
22  
21  
20  
19  
DELAY,  
PEAKING AND  
CORING  
RO  
GO  
BO  
RGB MATRIX  
AND  
OUTPUT  
FILTER  
TUNING  
TRAP  
BAND PASS  
SW  
SAT  
SW  
14  
15  
16  
17  
HUE  
RGBIN2  
RI2  
G-Y MATRIX  
AND  
SAT CONTROL  
RGB INPUT  
AND  
SWITCH  
CVBS  
SWITCH  
PAL/NTSC  
DECODER  
S-VHS SWITCH  
GI2  
BI2  
10  
42  
45  
9
13  
6
7
11 38  
12 36  
35  
34  
33 30  
29  
32  
31 28 27  
23 24 25 26  
DET  
GND3  
GND1 GND2  
DEC  
FT  
RYO BYO RYI  
BYI  
RI1 GI1 BI1  
CVBS  
PIPO  
CVBS/TXT  
EXT  
4.4  
MHz  
3.6  
MHz  
LUMIN  
CVBS  
MGE078  
RGBIN1  
INT  
CHROMA  
TDA4665  
CVBS/Y  
SEC  
ref  
XTAL2 XTAL1  
LUMOUT  
Fig.1 Block diagram (SDIP52; SOT247-1).  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
6
PINNING  
SYMBOL  
PIN  
DESCRIPTION  
SDIP52  
QFP64  
DECDIG  
1
11  
12  
13  
14  
16  
17  
18  
20  
22  
23  
25  
26  
27  
28  
29  
30  
31  
32  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
49  
51  
53  
54  
55  
56  
decoupling digital supply  
black peak hold capacitor  
I2C-bus serial clock input  
CBLK  
2
SCL  
3
SDA  
4
I2C-bus serial data input/output  
band gap decoupling  
chrominance input (S-VHS)  
external CVBS/Y input  
main supply voltage (+8 V)  
internal CVBS input  
ground 1  
DECBG  
CHROMA  
CVBS/Y  
VP1  
5
6
7
8
CVBSINT  
GND1  
PIPO  
DECFT  
CVBSEXT  
RGBIN2  
RI2  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
picture-in-picture output  
decoupling filter tuning  
external CVBS input  
RGB insertion input 2  
red input 2  
GI2  
green input 2  
BI2  
blue input 2  
BLKIN  
BO  
black-current input  
blue output  
GO  
green output  
RO  
red output  
BCLIN  
RI1  
beam current limiter input  
red input 1  
GI1  
green input 1  
BI1  
blue input 1  
RGBIN1  
LUMIN  
LUMOUT  
BYO  
RGB insertion input 1  
luminance input  
luminance output  
−(B−Y) signal output  
−(R−Y) signal output  
−(B−Y) signal input  
−(R−Y) signal input  
3.58 MHz crystal connection  
4.43/3.58 MHz crystal connection  
loop filter phase detector  
SECAM reference output  
RYO  
BYI  
RYI  
XTAL1  
XTAL2  
DET  
SECref  
VP2  
horizontal oscillator supply voltage (+8 V)  
CVBS/TXT output  
CVBS/TXT  
1996 Jan 26  
6
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
PIN  
SYMBOL  
DESCRIPTION  
SDIP52  
QFP64  
SCO  
HOUT  
FBI  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
−
57  
58  
59  
24  
62  
63  
60  
1
sandcastle output  
horizontal output  
flyback input  
GND2  
PH2LF  
PH1LF  
GND3  
EWD  
VDR(p)  
VDR(n)  
EHTO  
VSC  
Iref  
ground 2  
phase-2 filter  
phase-1 filter  
ground 3  
east-west drive output  
3
vertical drive 1 positive output  
vertical drive 2 negative output  
EHT/overvoltage protection input  
vertical sawtooth capacitor  
reference current input  
not connected  
4
5
7
8
n.c.  
2
n.c.  
6
not connected  
n.c.  
−
9
not connected  
n.c.  
−
10  
15  
19  
33  
48  
50  
52  
21  
61  
64  
not connected  
n.c.  
−
not connected  
n.c.  
−
not connected  
n.c.  
−
not connected  
n.c.  
−
not connected  
n.c.  
−
not connected  
n.c.  
−
not connected  
VP3  
−
supply voltage 3 (+8 V)  
ground 4  
GND4  
GND5  
−
−
ground 5  
1996 Jan 26  
7
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
handbook, halfpage  
DEC  
1
2
3
4
5
6
7
8
9
52 n.c.  
51  
DIG  
C
I
BLK  
SCL  
ref  
50 VSC  
49 EHTO  
48 VDR  
SDA  
DEC  
BG  
(n)  
CHROMA  
47 VDR  
(p)  
CVBS/Y  
46 EWD  
V
45 GND3  
44 PH1LF  
43 PH2LF  
42 GND2  
41 FBI  
P1  
CVBS  
INT  
GND1 10  
PIPO 11  
DEC  
12  
13  
FT  
CVBS  
40 HOUT  
39 SCO  
EXT  
TDA8376(A)  
RGBIN2 14  
RI2 15  
38 CVBS/TXT  
GI2 16  
37  
V
P2  
BI2 17  
36 SEC  
ref  
BLKIN 18  
BO 19  
35 DET  
34 XTAL2  
33 XTAL1  
32 RYI  
GO 20  
RO 21  
BCLIN 22  
RI1 23  
31 BYI  
30 RYO  
GI1 24  
29 BYO  
BI1 25  
28 LUMOUT  
27 LUMIN  
RGBIN1 26  
MGE076  
Fig.2 Pin configuration (SDIP52).  
1996 Jan 26  
8
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
EWD  
n.c.  
1
2
3
4
5
6
7
8
9
51 XTAL2  
50 n.c.  
VDR  
49 XTAL1  
48 n.c.  
(p)  
VDR  
(n)  
EHTO  
n.c.  
47 RYI  
46 BYI  
VSC  
45 RYO  
44 BYO  
I
ref  
n.c.  
LUMOUT  
42 LUMIN  
RGBIN1  
43  
n.c. 10  
TDA8376(A)  
DEC  
C
11  
41  
DIG  
12  
40 BI1  
39 GI1  
38 RI1  
37 BCLIN  
36 RO  
35 GO  
34 BO  
33 n.c.  
BLK  
SCL 13  
SDA 14  
n.c. 15  
DEC  
BG  
16  
CHROMA 17  
CVBS/Y 18  
n.c. 19  
MGE077  
Fig.3 Pin configuration (QFP64).  
9
1996 Jan 26  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
This provides a better picture impression than a  
7
FUNCTIONAL DESCRIPTION  
Video switches  
symmetrical peaking. The circuit contains a coring circuit  
to prevent the noise content of the video signal being  
amplified by the peaking circuit. This coring circuit can be  
switched-off when required.  
7.1  
The circuit has two CVBS inputs and a Super-Video Home  
System (S-VHS) input. The input can be chosen by the  
I2C-bus. The input selector also has a position in which  
CVBSEXT is processed, unless there is a signal on the  
S-VHS input. When the input selector is in this position it  
switches to the S-VHS input if the S-VHS detector detects  
sync pulses on the S-VHS luminance input. The S-VHS  
detector output can be read by the I2C-bus. When the  
S-VHS option is not used the luminance input can be used  
as a second input for external CVBS signals. The choice is  
made via the CVS bit (see Table 1).  
It is possible to connect a Colour Transient Improvement  
(CTI) or Picture Signal Improvement (PSI) IC to the  
TDA8376. The luminance signal which has passed the  
filter and delay line circuit is available externally. The  
output signal of the transient improvement circuit must be  
applied to the luminance input circuit. When the CTI  
function is not required the two pins must be AC-coupled.  
The luminance signal below 50 IRE can be stretched in  
accordance with the difference between the peak black  
level and the blanking level of the back-porch of the video  
signal. The black level stretcher can be switched-off by  
connecting pin 2 to the positive supply line.  
The video switch circuit has two outputs which can be  
programmed in a different way. The input signal for the  
decoder is also available on the TXT output. Therefore this  
signal can be used to drive the teletext decoder and the  
SECAM add-on decoder. The signal on the PIP output can  
be chosen independent of the TXT output. If S-VHS is  
selected for one of the outputs the luminance and  
chrominance signals are added so that a CVBS signal is  
obtained again.  
7.3  
Synchronization circuit  
The sync separator is preceded by a controlled amplifier  
which adjusts the sync pulse amplitude to a fixed level.  
These pulses are fed to the slicing stage which is operating  
at 50% of the amplitude.  
The circuit contains a video identification circuit which  
checks whether a video signal is available at the selected  
video input. This circuit is independent of the  
synchronization circuit. The information of this  
identification circuit can also be used to switch the  
phase-1 (ϕ1) loop to a low gain when no signal is received  
so that a stable OSD display is obtained. The video  
identification circuit can be switched on and off via the  
I2C-bus.  
The separated sync pulses are fed to the first phase  
detector and to the coincidence detector. This coincidence  
detector is only used to detect whether the line oscillator is  
synchronized and not for transmitter identification. The first  
Phase-Locked Loop (PLL) has a very high-statical  
steepness so that the phase of the picture is independent  
of the line frequency. To prevent the horizontal  
synchronization being disturbed by anti-copy signals such  
as Macrovision the phase detector is gated during the  
vertical retrace period so that pulses during scan have no  
effect on the output voltage. The position of this pulse is  
asymmetrical and the width is approximately 22 µs.  
7.2  
Integrated video filters, peaking and black  
stretcher  
The circuit contains a chrominance bandpass and trap  
circuit. The chrominance trap filter in the luminance path is  
designed for a symmetrical step response behaviour. The  
filters are realized by gyrator circuits and they are  
automatically tuned by comparing the tuning frequency  
with the crystal frequency of the decoder. The luminance  
delay line and the delay for the peaking circuit are also  
realized by gyrator circuits. During SECAM reception the  
centre frequency of the chrominance trap is set to a value  
of approximately 4.2 MHz to obtain a better suppression of  
the SECAM carrier frequencies.  
The horizontal output signal is generated by an oscillator  
which operates at twice the line frequency. Its frequency is  
divided-by-two to lock the first control loop to the incoming  
signal. The time-constant of the loop can be forced by the  
I2C-bus (fast or slow). If required the IC can select the  
time-constant depending on the noise content of the  
incoming video signal. The free-running frequency of the  
oscillator is determined by a digital control circuit which is  
locked to the reference signal of the colour decoder. When  
the IC is switched on the horizontal output signal is  
suppressed and the oscillator is calibrated as soon as all  
subaddress bytes have been sent. When the frequency of  
the oscillator is correct the horizontal drive signal is  
switched on.  
The peaking function is achieved by two luminance delay  
cells each with a delay of 165 ns. The resulting peaking  
frequency is 3 MHz. The peaking is asymmetrical so that  
the overshoots in the direction of ‘black’ are approximately  
two times higher than those in the direction of ‘white’.  
1996 Jan 26  
10  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
To obtain a smooth switching-on and switching-off  
behaviour of the horizontal output stage the horizontal  
output frequency is doubled during switch-on and  
switch-off (slow start/stop). During that time the duty factor  
of the output pulse has such a value that maximum safety  
is obtained for the output stage  
7.4  
Colour decoder  
The colour decoder contains an alignment-free crystal  
oscillator, a killer circuit and the colour difference  
demodulators. The 90° phase shift for the reference signal  
is made internally. The demodulation angle and gain ratio  
for the colour difference signals for PAL and NTSC are  
adapted to the standard.  
To protect the horizontal output transistor the horizontal  
drive is switched off when a power-on reset is detected.  
The drive signal is switched on again when the normal  
switch-on procedure is followed, i.e. all sub-address bytes  
must be sent and, after calibration, the horizontal drive  
signal will be released again via the slow start procedure.  
The colour decoder is very flexible. Together with the  
SECAM decoder TDA8395 an automatic multistandard  
decoder can be designed. In the automatic mode the  
SECAM identification is accepted only when the vertical  
frequency is 50 Hz. In the forced mode the system can  
also identify signals with a vertical frequency of 60 Hz.  
When the coincidence detector indicates an out-of-lock  
situation the calibration procedure is repeated.  
Which standard the IC can decode depends on the  
external crystals. If a 4.4 MHz and a 3.5 MHz crystal are  
used PAL 4.4, NTSC 4.4, NTSC 3.5 and PAL 3.5 can be  
decoded. If two 3.5 MHz crystals are used PAL N and M  
can be decoded. If one crystal is connected only  
PAL/NTSC 4.4 or PAL/NTSC 3.5 can be decoded. The  
crystal frequency of the decoder is used to tune the line  
oscillator. Therefore the value of the crystal frequency  
must be given to the IC via the I2C-bus. For a reliable  
calibration of the horizontal oscillator it is very important  
that the crystal indication bits (XA and XB) are not  
corrupted (see Table 6). For this reason the crystal bits  
(SXA and SXB) can be read in the output bytes so that the  
software can check the I2C-bus transmissions  
The circuit has a second control loop to generate the drive  
pulses for the horizontal driver stage. To prevent the  
horizontal output transistor being switched on during  
flyback the horizontal drive output is gated with the flyback  
pulse.  
The vertical sawtooth generator drives the vertical output  
and E-W correction drive circuits. The geometry  
processing circuits provide control of horizontal shift, E-W  
width, E-W parabola/width ratio, E-W corner/parabola  
ratio, trapezium correction, vertical shift, vertical slope,  
vertical amplitude, and the S-correction. All these controls  
can be set via the I2C-bus. The geometry processor has a  
differential current output for the vertical drive signal and a  
single-ended output for the E-W drive. Both the vertical  
drive and the E-W drive outputs can be modulated for EHT  
compensation. The EHT compensation pin is also used for  
overvoltage protection.  
(see Table 38).  
7.5  
RGB output circuit and black-current  
stabilization  
The colour-difference signals are matrixed with the  
luminance signal to obtain the RGB-signals. For the  
RGB-inputs linear amplifiers have been chosen so that the  
circuit is suited for signals coming from the SCART  
connector. The RGB2 inputs (pins 14 to 17) have priority  
over the RGB1 inputs (pins 23 to 26). Both fast blanking  
inputs can be blocked by I2C-bus controls. The contrast  
and brightness controls operate on internal and external  
signals.  
The TDA8376A geometry processor also offers the  
possibility for a flexible vertical and horizontal zoom mode  
for 16 : 9 applications. Because of this feature an  
additional control can be added on the remote control so  
that the viewer can adjust the picture.  
In addition the de-interlace of the vertical output can be set  
via the I2C-bus.  
To avoid damage of the picture tube when the vertical  
deflection fails, the guard output current of the TDA8350  
can be supplied to the sandcastle output. When a failure is  
detected the RGB-outputs are blanked and a bit is set  
(NDF) in the status byte of the I2C-bus. When no vertical  
deflection output stage is connected this guard circuit will  
also blank the output signals. This can be overruled by the  
EVG bit of subaddress 0A (see Table 1).  
1996 Jan 26  
11  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
I2C-BUS SPECIFICATION  
The output signal has an amplitude of approximately 2 V  
black-to-white at nominal input signals and nominal  
settings of the controls.  
8
handbook, halfpage  
The black current stabilization is realized by feedback from  
the video output amplifiers to the RGB control circuit. The  
‘black current’ of the 3 guns of the picture tube is internally  
measured and stabilized. The black level control is active  
during 4 lines at the end of the vertical blanking. During the  
first line the leakage current is measured and the following  
3 lines the 3 guns are adjusted to the required level. The  
maximum acceptable leakage current is ±100 µA.  
A6  
A5  
0
A4  
0
A3  
0
A2  
1
A1  
0
A0 R/W  
1
1
1/0  
MLA743  
Fig.4 Slave address (8A).  
The nominal value of the ‘black current’ is 10 µA. The ratio  
of the currents for the various guns automatically tracks  
with the white point adjustment so that the background  
colour is the same as the adjusted white point.  
Valid subaddresses: 00 to 13 (TDA8376) or 00 to 16  
(TDA8376A); subaddress FE is reserved for test  
purposes. Auto-increment mode is available for  
subaddresses.  
The input impedance of the ‘black-current’ measuring pin  
is 15 kΩ. Therefore the beam current during scan will  
cause the input voltage to exceed the supply voltage. The  
internal protection will start conducting so that the  
excessive current is bypassed.  
8.1  
Start-up procedure  
Read the status bytes until POR = 0 and send all  
subaddress bytes. The horizontal output signal is switched  
on when the oscillator is calibrated.  
When the TV receiver is switched on the black current  
stabilization circuit is not active, the RGB outputs are  
blanked and beam current limiting input pin is  
Each time before the data in the IC is refreshed, the status  
bytes must be read. If POR = 1, the procedure previously  
mentioned must be carried out to restart the IC.  
short-circuited. Only during the measuring lines will the  
outputs supply a voltage of 5 V to the video output stage  
so that it can be detected if the picture tube is warming up.  
These pulses are switched on after a waiting time of  
approximately 0.5 s. This ensures that the vertical  
deflection is activated so that the measuring pulses are not  
visible on the screen. As soon as the current supplied to  
the measuring input exceeds a value of 190 µA the  
stabilization circuit is activated. After a waiting time of  
approximately 0.8 s the blanking and the beam current  
limiting input pin are released. The remaining switch-on  
behaviour of the picture is determined by the external time  
constant of the beam current limiting network.  
When this procedure is not followed the horizontal  
frequency may be incorrect after power-up or after a  
power dip.  
1996 Jan 26  
12  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
8.2  
Inputs  
Table 1 Input status bits  
DATA BYTE  
SUBADDRESS  
(HEX)  
FUNCTION  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Source select  
Decoder mode  
Hue  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
INA  
INB  
INC  
DL  
A5  
A5  
A5  
A5  
A5  
A5  
A5  
A5  
A5  
A5  
A5  
A5  
A5  
YD1  
A5  
A5  
A5  
0
IND  
STB  
A4  
A4  
A4  
A4  
A4  
A4  
A4  
A4  
A4  
A4  
A4  
A4  
A4  
YD0  
A4  
A4  
A4  
0
FOA  
POC  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
0
FOB  
CM2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
0
XA  
CM1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
0
XB  
CM0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
0
FORF FORS  
0
0
0
0
Horizontal shift (HS)  
E-W width (E-W)  
E-W parabola/width (PW)  
E-W corner parabola (CP)  
E-W trapezium (TC)  
Vertical slope (VS)  
Vertical amplitude (VA)  
S-correction (SC)  
Vertical shift (VSH)  
White point R  
White point G  
White point B  
Peaking  
0
0
0
0
0
0
0
0
NCIN  
VID  
HCO  
SBL  
0
LBM  
EVG  
PRD  
EXP(1) CL(1)  
0
MAT  
YD3  
RBL  
IE1  
0
CVS  
0
YD2  
COR  
IE2  
0
Brightness  
Saturation  
Contrast  
12  
13  
14  
15  
16  
Spare  
0
0
Spare  
0
0
0
0
0
0
0
0
Spare  
0
0
0
0
0
0
0
0
Vertical zoom (VX, 76A)  
0
0
A5  
A4  
A3  
A2  
A1  
A0  
Note  
1. The bits EXP and CL in subaddress 0C are only valid for the TDA8376. For the TDA8376A these two bits must be  
set to logic 0.  
Table 2 Output status bits  
DATA BYTE  
SUBADDRESS  
FUNCTION  
(HEX)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Output status bytes  
00  
01  
POR  
NDF  
FSI  
IN1  
STS  
IN2  
SL  
IFI  
XPR  
AFA  
CD2  
X(1)  
CD1  
SXA  
CD0  
SXB  
Note  
1. X = don’t care.  
1996 Jan 26  
13  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
8.2.1  
INPUT CONTROL BITS  
Table 7 Forced field frequency  
Table 3 Source select 1  
FORF  
FORS  
FIELD FREQUENCY  
0
0
auto (60 Hz when line not  
synchronized)  
INA  
0
INB  
0
DECODER AND TXT  
CVBSINT  
0
1
1
1
0
1
60 Hz; note 1  
50 Hz; note 1  
0
1
CVBSEXT  
1
0
S-VHS  
auto  
1
1
S-VHS (CVBSEXT  
)
(50 Hz when line not synchronized)  
Table 4 Source select 2  
Note  
1. When the forced mode is selected the divider will only  
switch to that position when the horizontal oscillator is  
not synchronized.  
INC  
IND  
PIP  
0
0
1
1
0
1
0
1
CVBSINT  
CVBSEXT  
S-VHS  
Table 8 Interlace  
S-VHS (CVBSEXT  
)
DL  
STATUS  
MODE  
0
1
interlace  
Table 5 Phase 1 (ϕ1) time constant  
de-interlace  
FOA  
FOB  
MODE  
Table 9 Standby  
0
0
1
0
1
X(1)  
normal  
slow  
STB  
fast  
0
1
standby  
normal  
Note  
1. X = don’t care.  
Table 10 Synchronization mode  
Table 6 Crystal indication XA and XB  
POC  
MODE  
XA  
XB  
CRYSTAL  
0
1
active  
not active  
0
0
1
1
0
1
0
1
two 3.6 MHz  
one 3.6 MHz (pin 33)  
one 4.4 MHz (pin 34)  
Table 11 Colour decoder mode  
CM2 CM1 CM0  
DECODER MODE  
3.6 MHz (pin 33) and  
4.4 MHz (pin 34)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
not forced, own intelligence  
forced NTSC 3.6 MHz  
forced PAL 4.4 MHz  
forced SECAM  
forced NTSC 4.4 MHz  
forced PAL 3.6 MHz (pin 33)  
forced PAL 3.6 MHz (pin 34)  
no function  
1996 Jan 26  
14  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
Table 12 Vertical divider mode  
Table 20 Condition Y/C input  
NCIN  
VERTICAL DIVIDER MODE  
CVS  
Y-INPUT MODE  
0
1
normal operation  
0
1
switched to Y/C mode  
switched to CVBS mode  
switched to search window  
Table 13 Video identification mode  
Table 21 PAL/NTSC matrix  
VID  
VIDEO IDENTIFICATION MODE  
MAT  
MATRIX  
adapted to standard  
PAL  
0
1
ϕ1 loop switched on and off  
0
1
not active  
Table 14 Long blanking mode  
Table 22 Y-delay adjustment; note 1  
LBM  
BLANKING MODE  
YD0 to YD3  
Y-DELAY  
0
1
adapted to standard (50 or 60 Hz)  
YD3  
YD2  
YD1  
YD0  
YD3 × 160 ns +  
YD2 × 80 ns +  
YD1 × 40 ns +  
YD0 × 40 ns  
fixed in accordance with 50 Hz standard  
Table 15 EHT tracking mode  
HCO  
TRACKING MODE  
Note  
0
1
EHT tracking only on vertical  
1. For an equal delay of the luminance and chrominance  
signal the delay must be set at a value of 160 ns. This  
is only valid for a CVBS signal without group  
delay distortions.  
EHT tracking on vertical and E-W  
Table 16 Enable vertical guard (RGB blanking)  
EVG  
VERTICAL GUARD MODE  
not active  
active  
Table 23 RGB blanking  
0
1
RBL  
RGB BLANKING  
0
1
not active  
active  
Table 17 Service blanking  
SBL  
SERVICE BLANKING MODE  
Table 24 Noise coring (peaking)  
0
1
off  
on  
COR  
NOISE CORING  
0
1
off  
on  
Table 18 Overvoltage input mode  
PRD  
OVERVOLTAGE MODE  
Table 25 Enable fast blanking RGB1  
0
1
detection mode  
protection mode  
IE1  
0
FAST BLANKING  
not active  
active  
1
Table 19 Vertical deflection mode (TDA8376 only)  
EXP  
CL  
VERTICAL DEFLECTION MODE  
Table 26 Enable fast blanking RGB2  
0
0
1
1
0
1
0
1
normal  
IE2  
0
FAST BLANKING  
compress  
expand  
not active  
active  
1
expand and lift  
1996 Jan 26  
15  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
8.2.2  
OUTPUT CONTROL BITS  
Table 33 Output vertical guard  
Table 27 Power-on reset  
NDF  
VERTICAL OUTPUT STAGE  
0
1
OK  
POR  
MODE  
failure  
0
1
normal  
power-down  
Table 34 Indication RGB1 insertion  
Table 28 Field frequency indication  
IN1  
0
RGB INSERTION  
no (pin 26 LOW)  
yes (pin 26 HIGH)  
FSI  
0
FREQUENCY  
1
50 Hz  
60 Hz  
1
Table 35 Indication RGB2 insertion  
Table 29 S-VHS status  
IN2  
RGB INSERTION  
0
1
no (pin 14 LOW)  
yes (pin 14 HIGH)  
STS  
S-VHS INPUT  
0
1
no signal  
signal  
Table 36 Output video identification  
Table 30 Phase 1 (ϕ1) lock indication  
IFI  
VIDEO SIGNAL  
0
1
no video signal identified  
video signal identified  
SL  
INDICATION  
0
1
not locked  
locked  
Table 37 IC version indication  
AFA  
IC  
Table 31 X-ray protection  
0
1
TDA8376  
XPR  
OVERVOLTAGE  
TDA8376A  
0
1
no overvoltage detected  
overvoltage detected  
Table 38 Crystal indication SXA and SXB  
SXA  
SXB  
CRYSTAL  
Table 32 Colour decoder mode  
0
0
1
1
0
1
0
1
two 3.6 MHz  
one 3.6 MHz  
one 4.4 MHz  
CD2 CD1 CD0  
STANDARD  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no colour standard identified  
NTSC 3.6 MHz  
PAL 4.4 MHz  
3.6 and 4.4 MHz  
SECAM  
NTSC 4.4 MHz  
PAL 3.6 MHz (pin 33)  
PAL 3.6 MHz (pin 34)  
spare  
1996 Jan 26  
16  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
9
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL PARAMETER CONDITIONS  
VP supply voltage  
MIN.  
MAX.  
9.0  
UNIT  
−
V
Tstg  
Tamb  
Tsol  
Tj  
storage temperature  
−25  
0
+150  
70  
°C  
°C  
°C  
°C  
V
operating ambient temperature  
soldering temperature  
for 5 s  
−
260  
operating junction temperature  
electrostatic handling  
−
150  
Ves  
all pins; notes 1 and 2  
all pins; notes 1 and 3  
−2000  
−200  
+2000  
+200  
V
Notes  
1. All pins are protected against ESD by means of internal clamping diodes.  
2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.  
3. Machine Model (MM): R = 0 Ω; C = 200 pF.  
10 THERMAL CHARACTERISTICS  
SYMBOL  
Rth j-a  
PARAMETER  
VALUE  
UNIT  
thermal resistance from junction to ambient in free air  
SDIP52  
QFP64  
40  
50  
K/W  
K/W  
11 QUALITY SPECIFICATION  
In accordance with “SNW-FQ-611E”. The number of the quality specification can be found in the “Quality Reference  
Handbook”. The handbook can be ordered using the code 9398 510 63011.  
11.1 Latch-up  
At Tamb = 70 °C all pins meet the following specification.  
• Itrigger ≥ 100 mA or ≥1.5VDD(max)  
• Itrigger ≤ −100 mA or ≤−0.5VDD(max)  
.
1996 Jan 26  
17  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
12 CHARACTERISTICS  
VP = 8 V; Tamb = 25 °C; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
Supplies  
MAIN SUPPLY (PIN 8)  
VP1  
IP1  
supply voltage  
supply current  
total power dissipation  
7.2  
8.0  
8.8  
V
−
−
75  
−
−
mA  
W
Ptot  
650  
HORIZONTAL OSCILLATOR SUPPLY (PIN 37)  
VP2  
IP2  
supply voltage  
supply current  
7.2  
8.0  
6
8.8  
V
−
−
mA  
CVBS and S-VHS input switch  
INTERNAL AND EXTERNAL CVBS INPUTS (PINS 9 AND 13)  
V9(p-p)  
CVBS input voltage  
(peak-to-peak value)  
note 1  
−
1.0  
1.4  
V
I9  
CVBS input current  
−
4
−
−
µA  
SSCVBS  
suppression of non-selected CVBS notes 2 and 3  
input signal  
50  
−
dB  
S-VHS INPUT (PINS 6 AND 7)  
V7(p-p)  
luminance input voltage  
−
1.0  
1.4  
V
(peak-to-peak value)  
I7(p-p)  
luminance input current  
−
−
4
−
µA  
V6(p-p)  
chrominance input voltage  
(burst amplitude)  
note 4  
0.3  
0.45  
V
(peak-to-peak value)  
Zi  
chrominance input impedance  
−
−
50  
−
−
kΩ  
TXT AND PIP OUTPUT SIGNALS (PINS 38 AND 11)  
Vo(p-p)  
output signal voltage amplitude  
(peak-to-peak value)  
1.0  
V
Zo  
output impedance  
−
−
−
250  
Ω
VTS  
top sync voltage level  
tbf  
−
V
1996 Jan 26  
18  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
RGB inputs, colour difference inputs, luminance inputs and outputs  
RGB INPUTS (PINS 15 TO 17 AND 23 TO 25); note 5  
Vi(p-p)  
input signal voltage amplitude for an note 6  
output signal of 2 V (black-to-white)  
at nominal controls  
−
0.7  
0.8  
V
(peak-to-peak value)  
Vi(p-p)  
input signal voltage amplitude  
before clipping occurs  
(peak-to-peak value)  
note 2  
1.0  
−
−
−
V
∆Vo  
difference between black level of  
internal and external signals at the  
outputs  
−
20  
mV  
Ii  
input currents  
no clamping; note 7  
note 2  
−
−
0.1  
0
−
µA  
∆td  
delay difference for the three  
channels  
20  
ns  
FAST BLANKING (PINS 14 AND 26)  
Vi  
input voltage  
no data insertion  
data insertion  
−
−
0.4  
−
V
0.9  
−
−
V
V14,26(max)  
td  
maximum input pulse  
data insertion  
−
3.0  
−
V
delay time from RGB input to  
RGB output  
data insertion; note 5  
−
100  
ns  
∆td  
delay difference between data  
insertion to RGB output and  
RGB input to RGB output  
data insertion; note 5  
−
50  
−
ns  
I14,26  
SSint  
input current  
−
−
−
0.2  
mA  
dB  
suppression of internal RGB signals notes 1 and 2; data  
insertion; fi = 0 to 5 MHz  
55  
−
SSext  
V14  
suppression of external RGB signals notes 1 and 2; no data  
insertion; fi = 0 to 5 MHz  
55  
4
−
−
−
−
dB  
V
input voltage to insert black level at  
the RGB outputs to facilitate OSD  
signals being applied to the outputs  
COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32)  
V32(p-p)  
V31(p-p)  
I31,32  
input signal amplitude −(R−Y)  
(peak-to-peak value)  
note 7  
note 7  
note 7  
−
−
−
1.05  
1.35  
0.1  
−
V
input signal amplitude −(B−Y)  
(peak-to-peak value)  
−
V
input current for both inputs  
1.0  
µA  
1996 Jan 26  
19  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28)  
V28(p-p)  
output signal voltage amplitude  
(peak-to-peak value)  
top sync to white  
−
0.45  
0.63  
V
VTS  
top sync voltage level  
output impedance  
−
−
−
2.5  
−
−
−
V
Ω
V
Zo  
250  
0.45  
V27(p-p)  
input signal voltage amplitude  
(peak-to-peak value)  
Iclamp  
clamping current during burst key  
pulse  
−
−
200  
−
µA  
µA  
Ii  
input current  
no clamping  
−
0.5  
Chrominance filters  
CHROMINANCE TRAP CIRCUIT  
ftrap  
trap frequency  
−
−
−
fosc  
4.2  
2
−
−
−
−
MHz  
MHz  
during SECAM reception  
note 8  
QF  
SR  
trap quality factor  
colour subcarrier rejection  
20  
−
dB  
CHROMINANCE BAND-PASS CIRCUIT  
fc  
centre frequency  
−
−
fosc  
3
−
−
MHz  
QBP  
band-pass quality factor  
Delay line, peaking circuit and black stretcher  
Y DELAY LINE  
td  
delay time  
note 2  
8 steps  
note 2  
−
480  
−
−
ns  
td1  
B
tuning range delay time  
bandwidth of internal delay line  
−160  
+160  
ns  
5
−
−
MHz  
PEAKING CONTROL; note 9  
fc(p)  
tW  
peaking centre frequency  
−
−
−
−
3
−
−
−
−
MHz  
ns  
width of preshoot or overshoot  
overshoot  
at 50% of pulse; note 2  
positive  
160  
20  
OS  
%
negative  
36  
%
peaking control curve  
wave gain  
16 steps  
see Fig.5  
1.8  
GW  
−
−
−
−
negative half wave gain  
--------------------------------------------------------------  
positive half wave gain  
CORING STAGE  
S
coring range  
15  
IRE  
BLACK LEVEL STRETCHER (PIN 2); note 10  
BLSmax  
LSH  
maximum black level shift  
level shift  
15  
−1  
−1  
6
21  
0
27  
+1  
+3  
10  
IRE  
IRE  
IRE  
IRE  
100% of peak-white  
50% of peak-white  
15% of peak-white  
−
8
1996 Jan 26  
20  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
Horizontal synchronization circuits  
SYNC VIDEO INPUTS (PINS 7, 9 AND 13)  
V7,9,13  
SLHS  
SLVS  
sync pulse voltage amplitude  
slicing level for horizontal sync  
slicing level for vertical sync  
note 7  
50  
300  
−
mV  
%
note 11  
−
−
50  
30  
−
−
%
HORIZONTAL OSCILLATOR  
ffr  
free running frequency  
−
−
−
15625  
−
−
Hz  
%
∆ffr  
spread of free running frequency  
±2  
0.5  
∆f/∆VP  
frequency variation with respect to  
the supply voltage  
VP = 8 V ±10%; note 2  
0.2  
%
∆f(max)  
maximum frequency variation with  
temperature  
Tamb = 0 to 70 °C; note 2  
−
−
80  
Hz  
FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 44); note 12  
fHR  
fCR  
S/N  
frequency holding range PLL  
frequency catching range PLL  
−
±0.9  
±0.9  
20  
±1.2  
−
kHz  
kHz  
dB  
note 2  
±0.6  
−
signal-to-noise ratio of the video  
input signal at which the time  
constant is switched  
−
HYS  
hysteresis at the switching point  
−
1
−
dB  
SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 43)  
∆ϕi/∆ϕo  
control sensitivity  
−
150  
12  
−
−
µs/µs  
µs  
tcr  
control range from start of horizontal  
output to flyback at nominal shift  
position  
11  
tshift  
horizontal shift range  
63 steps  
note 13  
±2  
−
−
−
µs  
ϕdync  
control sensitivity for dynamic  
compensation  
−
5.3  
µs/V  
V43  
I43  
voltage to switch on the ‘flash’  
protection  
6
−
−
−
V
input current during protection  
−
1
mA  
HORIZONTAL OUTPUT (PIN 40); note 14  
VOL  
LOW level output voltage  
maximum allowed output current  
maximum allowed output voltage  
duty factor  
IOL = 10 mA  
note 2  
−
−
0.3  
−
V
IO(max)  
VO(max)  
δ
10  
−
−
mA  
V
−
VP  
−
−
50  
75  
%
%
note 2; VHOUT = high;  
−
−
during switch-on/switch-off  
fswitch  
frequency during switch-on and  
switch-off  
−
2fHOUT  
−
Hz  
tswitch(on)  
tswitch(off)  
switch-on time  
switch-off time  
−
−
−
50  
−
−
−
ms  
ms  
ms  
RGB drive maximum  
RGB drive minimum  
100  
50  
1996 Jan 26  
21  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
FLYBACK PULSE INPUT (PIN 41)  
VHSW  
switching voltage level for horizontal  
−
0.4  
−
V
blanking  
Vϕ2(SW)  
V41(max)  
Zi  
switching level for phase-2 loop  
maximum input voltage  
input impedance  
−
−
−
4.0  
8.0  
10  
−
−
−
V
note 7  
note 7  
V
MΩ  
SANDCASTLE PULSE OUTPUT (PIN 39)  
V39  
output voltage  
during burst key  
4.8  
1.8  
3.3  
−
5.3  
2.0  
3.5  
25  
5.8  
2.2  
3.7  
−
V
during blanking  
V
tW  
pulse width  
burst key pulse  
µs  
vertical blanking (50 Hz)  
vertical blanking (60 Hz)  
lines  
lines  
V
−
21  
−
Vclamp  
I39(min)  
clamping voltage level for vertical  
guard detection  
−
2.7  
−
minimum input current to activate  
guard detection  
−
−
0.5  
mA  
I39(max)  
td  
maximum allowable input current  
2.5  
−
−
−
mA  
delay of start of burst key to start of  
sync  
−
5.4  
µs  
Vertical synchronization and geometry correction  
VERTICAL OSCILLATOR; note 15  
ffr  
free running frequency  
locking frequency range  
divider value not locked  
locking range  
−
50/60  
−
Hz  
flock  
45  
−
−
64.5  
−
Hz  
625/525  
lines  
LR  
488  
−
722  
lines/  
frame  
VERTICAL RAMP GENERATOR (PIN 50)  
V50(p-p)  
sawtooth voltage amplitude  
(peak-to-peak value)  
VS = 1FH;  
C = 100 nF; R = 39 kΩ  
−
3.5  
−
V
Idis  
discharge current  
−
−
1
−
−
mA  
Icharge  
charge current set by external  
resistor  
note 16  
19  
µA  
VS  
vertical slope control range  
charge current increase  
LOW level voltage of ramp  
63 steps  
f = 60 Hz  
−20  
−
−
+20  
−
%
%
V
∆I50  
V50L  
20  
2.07  
−
−
VERTICAL DRIVE OUTPUTS (PINS 47 AND 48)  
Idiff(p-p)  
differential output current  
(peak-to-peak value)  
VA = 1FH  
−
0.95  
−
mA  
ICM  
Vo  
common mode output current  
output voltage  
−
400  
−
µA  
0
−
4.0  
V
1996 Jan 26  
22  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 49); note 13  
V49  
input voltage  
1.2  
−
−
2.8  
V
SMR  
ϕvert  
ϕEW  
Ieq  
scan modulation range  
vertical sensitivity  
−5  
−
+5  
−
%
6.3  
−6.3  
−
%/V  
%/V  
µA  
V
E-W sensitivity  
when switched-on  
−
−
E-W equivalent output current  
overvoltage detection level  
+100  
−
−100  
−
V49  
3.9  
DE-INTERLACE  
first field delay  
−
0.5H  
−
E-W WIDTH; note 17  
CR  
control range  
63 steps  
TDA8376  
100  
100  
−
−
80  
65  
%
%
TDA8376A  
Ieq  
equivalent output current  
TDA8376  
0
−
−
−
400  
700  
8.0  
µA  
µA  
V
TDA8376A  
0
Vo  
Io  
E-W output voltage range  
E-W output current range  
TDA8376  
1.0  
0
0
−
−
900  
µA  
µA  
TDA8376A  
1200  
E-W PARABOLA/WIDTH  
CR  
Ieq  
control range  
equivalent output current  
63 steps  
0
0
−
−
22  
%
E-W = 3FH; CP = 00H  
440  
µA  
E-W CORNER/PARABOLA  
CR  
Ieq  
control range  
equivalent output current  
63 steps  
−43  
−
−
0
0
%
PW = 3FH; E-W = 3FH  
−190  
µA  
E-W TRAPEZIUM  
CR  
Ieq  
control range  
equivalent output current  
63 steps  
−5  
−
−
+5  
%
−100  
+100  
µA  
VERTICAL AMPLITUDE  
CR  
control range  
63 steps  
80  
−
−
120  
%
Ieqdiff(p-p)  
equivalent differential vertical drive  
output current (peak-to-peak value)  
SC = 00H  
760  
1140  
µA  
VERTICAL SHIFT  
CR  
control range  
63 steps  
−5  
−
−
+5  
%
Ieqdiff(p-p)  
equivalent differential vertical drive  
output current (peak-to-peak value)  
−50  
+50  
µA  
S-CORRECTION  
CR  
control range  
63 steps  
23  
0
−
30  
%
1996 Jan 26  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
VERTICAL EXPANSION (ZOOM) MODE (TDA8376A ONLY); note 18  
Output current variation compared with nominal scan:  
VEF  
vertical expansion factor  
0.75  
−
1.38  
%
%
output current limiting and RGB  
blanking  
−
1.06  
−
Colour demodulation part  
CHROMINANCE AMPLIFIER  
ACCcr  
ACC control range  
note 19  
26  
−
−
−
dB  
dB  
∆V  
variation in amplitude of the output  
signals over the ACC range  
−
2
THRon  
HYSoff  
threshold colour killer ON  
hysteresis colour killer OFF  
−23  
−26  
−29  
dB  
dB  
strong signal conditions;  
−
+3  
−
S/N ≥ 40 dB; note 2  
noisy input signals; note 2  
−
+1  
−
dB  
REFERENCE PART  
Phase-locked loop; note 20  
fCR  
frequency catching range  
phase shift for a ±400 Hz deviation note 2  
±360  
±600  
−
Hz  
∆ϕ  
−
−
2
deg  
of the oscillator frequency  
Oscillator  
TCosc  
temperature coefficient of the  
oscillator frequency  
note 2  
−
−
−
−
tbf  
tbf  
Hz/K  
Hz  
∆fosc  
oscillator frequency deviation with  
respect to the supply  
note 2; VP = 8 V ±10%  
Ri(min)  
minimum negative input resistance  
maximum load capacitance  
−
−
−
−
1
kΩ  
CL(max)  
15  
pF  
HUE CONTROL  
HUEcr  
hue control range  
63 steps; see Fig.6  
note 2  
±35  
−
±40  
0
−
−
−
deg  
deg  
deg  
∆HUE  
hue variation for ±10% VP  
hue variation with temperature  
∆HUE/∆T  
Tamb = 0 to 70 °C; note 2  
−
0
1996 Jan 26  
24  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
DEMODULATORS (PINS 29 AND 30)  
V30(p-p)  
V29(p-p)  
G
−(R−Y) output voltage amplitude  
(peak-to-peak value)  
note 21  
−
−
0.525  
0.675  
1.78  
−
−
V
V
−(B−Y) output voltage amplitude  
(peak-to-peak value)  
note 21  
−
gain ratio between both  
demodulators G(B−Y) and G(R−Y)  
1.60  
−1  
−
1.96  
+1  
−
∆V  
spread of voltage amplitude ratio  
PAL/NTSC  
note 2  
note 2  
dB  
Zo  
output impedance −(R−Y)/−(B−Y)  
500  
Ω
output  
B
bandwidth of demodulators  
−3 dB; notes 7 and 21  
f = fosc; −(R−Y) output  
f = fosc; −(B−Y) output  
f = 2fosc; −(R−Y) output  
f = 2fosc; −(B−Y) output  
−
−
−
−
−
−
650  
−
−
kHz  
mV  
mV  
mV  
mV  
mV  
V29,30(p-p)  
residual carrier output  
(peak-to-peak value)  
5
−
5
−
5
−
5
V30(p-p)  
∆Vo/∆T  
∆Vo/∆VP  
ϕe  
H/2 ripple at −(R−Y) output  
(peak-to-peak value)  
−
25  
variation of output voltage amplitude note 2  
with temperature  
−
−
−
0.1  
−
−
%/K  
dB  
variation of output voltage amplitude note 2  
with supply voltage  
±0.1  
±5  
phase error in the demodulated  
signals  
−
deg  
COLOUR DIFFERENCE MATRICES IN CONTROL CIRCUIT  
PAL or (SECAM mode with TDA8395); −(R−Y) and −(B−Y) not affected  
(G−Y)/(R−Y) ratio of demodulated signals  
−
−
−0.51  
±10%  
−
−
(G−Y)/(B−Y) ratio of demodulated signals  
−0.19  
±25%  
NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting)  
−(B−Y)  
−(R−Y)  
−(G−Y)  
−(B−Y) signal  
−(R−Y) signal  
−(G−Y) signal  
−(B−Y)  
1.39(R−Y) − 0.07(B−Y)  
−0.46(R−Y) − 0.15(B−Y)  
1996 Jan 26  
25  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 36); note 22  
fref  
reference frequency  
−
4.43  
−
MHz  
V
V36(p-p)  
output voltage amplitude  
(peak-to-peak value)  
0.2  
0.25  
0.3  
Vo  
output voltage level  
PAL/NTSC identified  
−
−
1.5  
5.0  
−
−
V
V
no PAL/NTSC identified;  
SECAM (by TDA8395)  
identified  
I36  
required current to stop PAL/NTSC  
identification circuit during SECAM  
150  
−
−
−
−
µA  
Control part  
SATURATION CONTROL; note 6  
SATCR  
saturation control range  
63 steps; see Fig.7  
63 steps  
52  
dB  
CONTRAST CONTROL; note 6  
CONCR  
contrast control range  
−
−
20  
−
dB  
dB  
tracking between the three channels see Fig.8  
over a control range of 10 dB  
−
0.5  
BRIGHTNESS CONTROL  
BRICR  
brightness control range  
63 steps; see Fig.9  
−
±0.7  
−
V
V
RGB OUTPUT SIGNALS (PINS 19, 20 AND 21)  
V19,20,21(p-p) output voltage amplitude  
(peak-to-peak value)  
at nominal luminance input tbf  
signal, nominal contrast  
and white-point  
2.0  
tbf  
adjustment; note 6  
at maximum white point  
setting  
−
3.0  
−
V
VBWmax(p-p) maximum voltage amplitude  
(black-to-white)  
note 23  
−
−
2.6  
3.6  
−
−
V
V
at maximum white point  
setting  
VRED(p-p)  
output voltage amplitude for the ‘red’ at nominal settings for  
tbf  
2.1  
tbf  
V
channel (peak-to-peak value)  
contrast and saturation  
control and no luminance  
signal to the input (R−Y,  
PAL)  
Vblank  
Ibias  
blanking level at the RGB outputs  
0.7  
0.8  
1.5  
0.9  
V
internal bias current of NPN emitter  
follower output transistor  
−
−
mA  
Io  
available output current  
output impedance  
−
−
−
5
−
mA  
Ω
Zo  
150  
−
−
CRbl  
control range of the black-current  
stabilization  
nominal brightness and  
white-point adjustment (with  
respect to the measuring  
pulse); Vblk = 2.5 V  
±1  
V
1996 Jan 26  
26  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
Vbl  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
black level shift with picture content note 2  
−
−
−
20  
mV  
V
Vo  
output voltage of the 4-L pulse after  
switch-on  
4.2  
−
∆bl/∆T  
∆bl  
variation of black level with  
temperature  
note 2  
note 2  
−
1.0  
−
mV/K  
relative variation in black level  
between the three channels during  
variations of  
supply voltage (±10%)  
saturation (50 dB)  
nominal controls  
nominal contrast  
nominal saturation  
nominal controls  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
tbf  
tbf  
tbf  
tbf  
tbf  
−
mV  
mV  
mV  
mV  
mV  
dB  
contrast (20 dB)  
brightness (±0.5 V)  
temperature (range 40 °C)  
S/N  
signal-to-noise ratio of the output  
signals  
RGB input; note 24  
CVBS input; note 24  
60  
50  
−
−
dB  
Vres(p-p)  
residual voltage at the RGB outputs at fosc  
(peak-to-peak value)  
15  
15  
mV  
mV  
at 2fosc plus higher  
−
harmonics in RGB outputs  
B
bandwidth of output signals  
RGB input; at −3 dB  
8
−
−
−
MHz  
MHz  
CVBS input; at −3 dB;  
−
2.8  
f
osc = 3.58 MHz  
CVBS input; at −3 dB;  
osc = 4.43 MHz  
−
3.5  
−
−
MHz  
MHz  
f
S-VHS input; at −3 dB  
5
−
WHITE-POINT ADJUSTMENT  
I2C-bus setting for nominal gain  
HEX code  
−
20H  
50  
−
Ginc(max)  
Gdec(max)  
maximum increase of the gain  
maximum decrease of the gain  
HEX code 3FH  
HEX code 00H  
40  
40  
60  
60  
%
%
50  
BLACK-CURRENT STABILIZATION (PIN 18); note 25  
Ibias  
bias current for the picture tube  
cathode  
nominal white point setting  
−
10  
−
µA  
Ileak  
acceptable leakage current  
maximum current during scan  
−
−
100  
0.3  
−
−
µA  
Iscan(max)  
mA  
1996 Jan 26  
27  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
BEAM CURRENT LIMITING (PIN 22); note 23  
VCR  
contrast reduction starting voltage  
−
−
3.5  
−
V
V
VdiffCR  
voltage difference for full contrast  
reduction  
2.0  
−
VBR  
brightness reduction starting voltage  
−
−
2.5  
1.0  
−
−
V
V
VdiffBR  
voltage difference for full brightness  
reduction  
Vbias  
Ich(int)  
Idisch  
internal bias voltage  
−
−
−
4.5  
25  
−
−
−
V
internal charge current  
µA  
µA  
discharge current due to ‘peak-white  
limiting’  
200  
Notes  
1. Signal with negative-going sync. Amplitude includes sync pulse amplitude.  
2. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix  
batches which are made in the pilot production period.  
3. This parameter is measured at nominal settings of the various controls.  
4. Indicated is a signal for a colour bar with 75% saturation (chrominance : burst ratio = 2.2 : 1).  
5. The RGB1 inputs (pins 14 to 17) have priority over the RGB2 inputs (pins 23 to 25).  
6. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum −10 dB. In the nominal  
brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses.  
7. This parameter is not tested during production and is just given as application information for the designer of the  
television receiver.  
8. The −3 dB bandwidth of the circuit can be calculated by means of the following equation:  
1
2Q  
f–3 dB = fosc 1 –  
-------  
9. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns  
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the  
overshoots but by measuring the frequency response of the Y output.  
10. For video signals with a black level which deviates from the back-porch blanking level the signal is ‘stretched’ to the  
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.10). The black level is  
detected by the capacitor connected to pin 2. The black level stretcher can be made inoperative by connecting pin 2  
to the positive supply line. The values given are valid only when the luminance input signal (pins 7, 9 and 13) has a  
value of 1 V (p-p).  
11. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing  
level and the black level (back porch).  
1996 Jan 26  
28  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
12. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is  
switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a  
noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’  
mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to  
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be  
automatically or overruled by the I2C-bus.  
The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be  
used to close or open the first control loop when a video signal is present or not present on the input. This enables  
a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification  
circuit with the first loop can be defeated via the I2C-bus.  
To prevent that the horizontal synchronization being disturbed by anti-copy guard signals like Macrovision the phase  
detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage.  
The width of the gate pulse is approximately 22 µs, the phase position around the sync pulse is asymmetrical. During  
weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of  
the gate pulse is reduced to 5.7 µs so that the effect of the noise is reduced to a minimum.  
The output current of the phase detector in the various conditions are shown in Table 39.  
13. The ICs have two protection inputs. The protection on pin 43 is intended to be used as ‘flash’ protection. When this  
protection is activated the horizontal drive pulse is switched-off immediately and then switched on again via the slow  
start procedure. The protection on pin 49 is intended for overvoltage (X-ray) protection. When this protection is  
activated the horizontal drive can be switched-off (via the slow stop procedure). It is also possible to continue the  
horizontal drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the two  
modes of operation is made via the PRD bit.  
14. During switch-on the horizontal output starts with the double frequency and with a duty factor of 75% (VHOUT = high).  
After approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak  
currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to the double  
value and the RGB drive is set to maximum so that the EHT capacitor is discharged. After approximately 100 ms the  
RGB drive is set to minimum and 50 ms later the horizontal drive is switched-off.  
15. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This  
divider circuit has 3 modes of operation:  
a) Search mode ‘large window’.  
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per  
frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode  
the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz).  
b) Standard mode ‘narrow window’.  
This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window.  
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator  
is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch  
back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window.  
c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).  
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in  
accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the  
standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync  
pulse is missing.  
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this  
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.  
The vertical divider requires some waiting time during channel-switching of the tuner. When a fast reaction of the  
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit  
in subaddress 08.  
1996 Jan 26  
29  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
16. Conditions: frequency is 50 Hz; normal mode; VS = 1FH.  
17. The E-W output current range of the TDA8376A is higher than that of the TDA8376 because of the horizontal zoom  
function of the TDA8376A. The output range percentages mentioned for E-W control parameters are based on the  
assumption that 400 µA variation in E-W output current is equivalent to 20% variation in picture width.  
18. The TDA8376A has a zoom adjustment possibility for the vertical and horizontal deflection. For this reason an extra  
DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 75 to 138%  
of the nominal scan. At an amplitude of 106% of the nominal scan the output current is limited and the blanking of  
he RGB outputs is activated. This is illustrated in Fig.21. In addition to the variation of the vertical amplitude the  
vertical slope control range is also increased. This allows variation of the position of the bottom part of the picture  
independent of the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical ‘zoom’  
DAC.  
19. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude  
300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB.  
20. All frequency variations are referenced to a 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are  
measured with the Philips crystal series 9922 520 with a series capacitance of 18 pF. The oscillator circuit is rather  
insensitive to the spurious responses of the crystal. Provided the resonance resistance of the third overtone is higher  
than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal  
parameters for the crystals are:  
a) load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz  
b) motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal)  
c) parallel capacitance C0 = 5 pF for both crystals.  
The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures  
given in are therefore valid for the specified crystal series. In this, tolerances of the crystal with respect to nominal  
frequency, motional capacitance and ageing have been taken into account and have been counted for by gaussic  
addition. Whenever different typical crystal parameters are used the following equation might be helpful for  
calculating the impact on the detuning capabilities:  
CM  
Detuning range:  
--------------------------  
2
C0  
1 +  
------  
CL  
The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the  
crystal. The actual series capacitance in the application should be CL = 18 pF to account for parasitic capacitances  
on and off chip. For 3-normal applications with two crystals connected to one pin the maximum parasitic capacitance  
of the crystal pin should not exceed 15 pF.  
21. The −(R−Y) and −(B−Y) signals are demodulated with a phase difference of the reference carrier of 90° and a gain  
– (B – Y)  
ratio  
= 1.78 . The matrixing to the required signals is achieved in the control part.  
-----------------------  
– (R – Y)  
22. The subcarrier output signal can be supplied to the TDA8395 but it can also be used as drive signal for external comb  
filters. For this reason the signal is continuously available at the output. Only when SECAM has been identified the  
subcarrier signal is available only during the vertical retrace time. This is to avoid cross-talk between the SECAM  
input signal and the subcarrier signal. An external DC load on this pin is not allowed because this current will disturb  
the reliability of the communication between the TDA8376/TDA8376A and the TDA8395.  
23. At nominal setting of the gain control. When this amplitude is exceeded the peak-white limiting circuit will reduce the  
contrast. The control voltage is generated via the external capacitor connected to the beam-current limiting input.  
24. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).  
25. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain  
(white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a  
result the ‘black-current’ of each gun is adapted to the white point setting so that the background colour will follow  
the white point adjustment.  
1996 Jan 26  
30  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
Table 39 Output current of the phase detector in the various conditions  
I2C-BUS COMMANDS  
IC CONDITIONS  
ϕ-1 CURRENT/MODE  
VID  
POC  
FOA  
FOB  
IDENT  
COIN  
NOISE  
SCAN  
V-RETR GATING MODE  
−
−
−
−
−
0
−
0
0
0
0
0
0
1
0
0
0
0
1
−
−
0
0
1
1
−
−
−
yes  
yes  
yes  
yes  
yes  
no  
yes  
no  
yes  
yes  
−
yes  
no  
yes  
no  
−
30  
180  
30  
30  
270  
30  
yes(1)  
no  
auto  
auto  
slow  
fast  
yes  
yes  
no  
180  
180  
6
270  
270  
6
fast  
−
−
no  
OSD  
off  
−
−
−
−
−
−
Note  
1. Only during vertical retrace, pulse width 22 µs. In other conditions the pulse width is 5.7 µs and the gating is  
continuous.  
MLA738 - 1  
MLA739 - 1  
50  
30  
10  
10  
30  
50  
50  
30  
10  
10  
30  
50  
(deg)  
(%)  
0
10  
20  
30  
40  
0
4
8
C
F
10  
DAC (HEX)  
DAC (HEX)  
Overshoot in direction ‘black’.  
Fig.5 Peaking control curve.  
Fig.6 Hue control curve.  
1996 Jan 26  
31  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
MLA741 - 1  
MLA740 - 1  
250  
225  
200  
175  
150  
125  
100  
75  
100  
(%)  
(%)  
90  
80  
70  
60  
50  
40  
30  
20  
10  
50  
25  
0
0
10  
20  
30  
40  
0
10  
20  
30  
40  
DAC (HEX)  
DAC (HEX)  
Fig.7 Saturation control curve.  
Fig.8 Contrast control curve.  
MLA742 - 1  
MGE079  
100  
handbook, halfpage  
0.7  
(V)  
80  
output  
(IRE)  
0.35  
60  
40  
20  
0
B
B
(2)  
0.35  
0
A
(1)  
A
0.7  
0
−20  
0
20  
40  
60  
80  
100  
input (IRE)  
0
10  
20  
30  
40  
DAC (HEX)  
(1) Maximum black level shift.  
(2) Level shift at 15% of peak white.  
Relative variation with respect to the measuring pulse.  
Fig.9 Brightness control curve.  
Fig.10 I/O relationship of the black level stretcher.  
1996 Jan 26  
32  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
13 TEST AND APPLICATION INFORMATION  
SDA  
4
SCL  
3
RI2  
15  
GI2  
16  
BI2 RGBIN2  
RI1  
23  
GI1  
24  
BI1 RGBIN1  
17  
14  
25  
26  
21  
20  
19  
18  
22  
46  
47  
48  
40  
41  
RO  
CVBS  
INT  
9
GO  
BO  
CVBS  
EXT  
13  
7
BLKIN  
BCLIN  
EWD  
VDR  
CVBS/Y  
CHROMA  
PIPO  
TDA8376(A)  
(p)  
6
VDR  
(n)  
HOUT  
FBI  
11  
34  
XTAL2  
33  
38  
36  
30 29  
32  
BYO RYI  
31  
39  
CVBS/  
TXT  
RYO  
BYI  
SCO  
SEC  
ref  
XTAL1  
4.4  
3.6  
MHz  
MHz  
to text decoder  
TDA8395  
TDA4665  
MGE080  
Fig.11 Application diagram.  
The preferred value of Rc is 39 kΩ which results in a  
reference current of 100 µA (Vref = 3.9 V  
13.1 East-West output stage  
In order to obtain correct tracking of the vertical and  
horizontal EHT-correction, the E-W output stage should be  
dimensioned as illustrated in Fig.12.  
The value of REW must be:  
Vscan  
REW = R ×  
----------------------  
18 × Vref  
c
Resistor REW determines the gain of the E-W output stage.  
Resistor Rc determines the reference current for both the  
vertical sawtooth generator and the geometry processor.  
Example: With Vref = 3.9 V Rc = 39 kΩ and Vscan = 120 V  
then REW = 68 kΩ.  
1996 Jan 26  
33  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
V
DD  
HORIZONTAL  
DEFLECTION  
STAGE  
V
scan  
R
EW  
TDA8376(A)  
DIODE  
MODULATOR  
V
EW  
46  
EWD  
EW OUTPUT  
STAGE  
51  
50  
V
ref  
MGE081  
R
c
C
saw  
39 kΩ  
(2%)  
100 nF  
(5%)  
I
ref  
Fig.12 East-West output stage.  
MGE082  
MGE083  
600  
900  
handbook, halfpage  
handbook, halfpage  
700  
I
400  
vert  
I
vert  
(µA)  
500  
(µA)  
200  
300  
100  
0
−200  
−400  
−100  
−300  
−500  
−700  
−600  
0
1/2 t  
t
0
1/2 t  
t
time  
time  
VA = 0, 31H and 63H; VSH = 31H; SC = 0.  
VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0.  
Fig.13 Control range of vertical amplitude.  
Fig.14 Control range of vertical slope.  
1996 Jan 26  
34  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
MGE084  
MGE085  
600  
600  
handbook, halfpage  
handbook, halfpage  
400  
400  
I
I
vert  
vert  
(µA)  
(µA)  
200  
200  
0
0
-200  
-400  
−200  
−400  
−600  
-600  
0
0
1/2 t  
t
1/2 t  
t
time  
time  
SC = 0, 31H and 63H; VA = 31H; VHS = 31H.  
Picture height does not change with setting of S-correction for  
nominal vertical amplitude (VA = 31H).  
VSH = 0, 31H and 63H; VA = 31H; SC = 0.  
Fig.15 Control range of vertical shift.  
Fig.16 Control range of S-correction.  
MGE086  
MGE087  
1200  
900  
handbook, halfpage  
handbook, halfpage  
1000  
800  
I
I
EW  
EW  
(µA)  
(µA)  
800  
700  
600  
400  
200  
600  
500  
400  
0
0
300  
t
1/2 t  
0
1/2 t  
t
time  
time  
EW = 0, 31H and 63H; PW = 31H; CP = 31H.  
PW = 0, 31H and 63H; EW = 31H; CP = 31H.  
Fig.17 Control range of E-W width.  
Fig.18 Control range of E-W parabola/width ratio.  
1996 Jan 26  
35  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
MGE088  
MGE089  
900  
650  
handbook, halfpage  
handbook, halfpage  
800  
600  
I
I
EW  
EW  
(µA)  
(µA)  
700  
550  
600  
500  
400  
500  
450  
400  
300  
0
350  
0
1/2 t  
t
1/2 t  
t
time  
time  
CP = 0, 31H and 63H; EW = 31H; PW = 63H.  
TC = 0, 31H and 63H; EW = 31H; PW = 31H.  
Fig.19 Control range of E-W corner/parabola ratio.  
Fig.20 Control range of E-W trapezium correction.  
TOP  
70  
PICTURE  
60  
vertical  
position  
(%)  
50  
40  
138%  
100%  
75%  
30  
20  
10  
1/2 t  
time  
t
0
−10  
−20  
−30  
−40  
−50  
−60  
BOTTOM  
PICTURE  
blanking for expansion 138%  
MGE090  
TDA8376A only.  
Fig.21 Sawtooth waveform and blanking pulse.  
36  
1996 Jan 26  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
For adjustment of the vertical shift and vertical slope  
independent of each other, a special service blanking  
mode can be entered by setting the SB-bit HIGH. In this  
mode the RGB-outputs are blanked during the second half  
of the picture. There are two different methods for  
alignment of the picture in vertical direction. Both methods  
make use of the service blanking mode.  
13.2 Adjustment of geometry control parameters  
The deflection processor of the TDA8376/TDA8376A  
offers nine control parameters for picture alignment:  
• Vertical picture alignment  
– S-correction  
– vertical amplitude  
– vertical slope  
The first method is recommended for picture tubes that  
have a marking for the middle of the screen. With the  
vertical shift control the last line of the visible picture is  
positioned exactly in the middle of the screen. After this  
adjustment the vertical shift should not be changed. The  
top of the picture is placed by adjustment of the vertical  
amplitude, and the bottom by adjustment of the vertical  
slope.  
– vertical shift  
• Horizontal picture alignment  
– horizontal shift  
– E-W width  
– E-W parabola/width  
– E-W corner/parabola  
– E-W trapezium correction.  
The second method is recommended for picture tubes that  
have no marking for the middle of the screen. For this  
method a video signal is required in which the middle of the  
picture is indicated (e.g. the white line in the circle test  
pattern). With the vertical slope control the beginning of the  
blanking is positioned exactly on the middle of the picture.  
Then the top and bottom of the picture are placed  
symmetrical with respect to the middle of the screen by  
adjustment of the vertical amplitude and vertical shift.  
After this adjustment the vertical shift has the correct  
setting and should not be changed.  
It is important to notice that the TDA8376/ TDA8376A is  
designed for use with a DC-coupled vertical deflection  
stage. This is the reason why a vertical linearity alignment  
is not necessary (and therefore not available).  
For a particular combination of picture tube type, vertical  
output stage and E-W output stage it is determined which  
are the required values for the settings of S-correction,  
E-W parabola/width ratio and E-W corner/parabola ratio.  
These parameters can be preset via the I2C-bus, and do  
not need any additional adjustment. The remainder of the  
parameters are preset with the mid-value of their control  
range (i.e. 1FH), or with the values obtained by previous  
TV-set adjustments.  
If the vertical shift alignment is not required VSH should be  
set to its mid-value (i.e. VSH = 1FH). Then the top of the  
picture is placed by adjustment of the vertical amplitude  
and the bottom by adjustment of the vertical slope. After  
the vertical picture alignment the picture is positioned in  
the horizontal direction by adjustment of the E-W width and  
the horizontal shift. Finally (if necessary) the left and  
right-hand sides of the picture are aligned in parallel by  
adjusting the E-W trapezium control.  
The vertical shift control is intended for compensation of  
off-sets in the external vertical output stage or in the  
picture tube. It can be shown that without compensation  
these off-sets will result in a certain linearity error,  
especially with picture tubes that need large S-correction.  
The total linearity error is in first order approximation  
proportional to the value of the off-set, and to the square of  
the S-correction required. The necessity to use the vertical  
shift alignment depends on the expected off-sets in vertical  
output stage and picture tube, on the required value of the  
S-correction, and on the demands upon vertical linearity.  
To obtain the full range of the vertical zoom function of the  
TDA8376A the adjustment of the vertical geometry should  
be carried out at a nominal setting of the zoom DAC at  
position 19H.  
1996 Jan 26  
37  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
14 PACKAGE OUTLINES  
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)  
SOT247-1  
D
M
E
A
2
A
L
A
1
c
e
(e )  
1
w M  
Z
b
1
M
H
b
52  
27  
pin 1 index  
E
1
26  
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
A
A
2
max.  
(1)  
(1)  
Z
1
w
UNIT  
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.  
max.  
1.3  
0.8  
0.53  
0.40  
0.32  
0.23  
47.9  
47.1  
14.0  
13.7  
3.2  
2.8  
15.80  
15.24  
17.15  
15.90  
mm  
5.08  
0.51  
4.0  
1.778  
15.24  
0.18  
1.73  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
90-01-22  
95-03-11  
SOT247-1  
1996 Jan 26  
38  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm  
SOT319-2  
y
X
A
51  
33  
52  
32  
Z
E
e
A
2
H
A
E
(A )  
3
E
A
1
θ
w M  
p
pin 1 index  
L
p
b
L
20  
64  
detail X  
1
19  
w M  
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.25 2.90  
0.05 2.65  
0.50 0.25 20.1 14.1  
0.35 0.14 19.9 13.9  
24.2 18.2  
23.6 17.6  
1.0  
0.6  
1.2  
0.8  
1.2  
0.8  
mm  
3.20  
0.25  
1
1.95  
0.2  
0.2  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-02-04  
97-08-01  
SOT319-2  
1996 Jan 26  
39  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
15 SOLDERING  
15.1 Introduction  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
situations reflow soldering is often used.  
Several techniques exist for reflowing; for example,  
thermal conduction by heated belt. Dwell times vary from  
50 to 300 seconds depending on heating method. Typical  
reflow temperatures range from 215 to 250 °C.  
Preheating is necessary to dry the paste and evaporate  
the binding agent. Preheat for 45 minutes at 45 °C.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “IC Package Databook” (order code 9398 652 90011).  
15.3.2 WAVE SOLDERING  
Wave soldering is not recommended for QFP packages.  
This is because of the likelihood of solder bridging due to  
closely-spaced leads and the possibility of incomplete  
solder penetration in multi-lead devices.  
15.2 SDIP  
15.2.1 SOLDERING BY DIPPING OR BY WAVE  
The maximum permissible temperature of the solder is  
260 °C; solder at this temperature must not be in contact  
with the joint for more than 5 seconds. The total contact  
time of successive solder waves must not exceed  
5 seconds.  
If wave soldering cannot be avoided, the following  
conditions must be observed:  
• A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave)  
soldering technique should be used.  
The device may be mounted up to the seating plane, but  
the temperature of the plastic body must not exceed the  
specified maximum storage temperature (Tstg max). If the  
printed-circuit board has been pre-heated, forced cooling  
may be necessary immediately after soldering to keep the  
temperature within the permissible limit.  
• The footprint must be at an angle of 45° to the board  
direction and must incorporate solder thieves  
downstream and at the side corners.  
Even with these conditions, do not consider wave  
soldering the following packages: QFP52 (SOT379-1),  
QFP100 (SOT317-1), QFP100 (SOT317-2),  
QFP100 (SOT382-1) or QFP160 (SOT322-1).  
15.2.2 REPAIRING SOLDERED JOINTS  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured. Maximum permissible solder  
temperature is 260 °C, and maximum duration of package  
immersion in solder is 10 seconds, if cooled to less than  
150 °C within 6 seconds. Typical dwell time is 4 seconds  
at 250 °C.  
Apply a low voltage soldering iron (less than 24 V) to the  
lead(s) of the package, below the seating plane or not  
more than 2 mm above it. If the temperature of the  
soldering iron bit is less than 300 °C it may remain in  
contact for up to 10 seconds. If the bit temperature is  
between 300 and 400 °C, contact may be up to 5 seconds.  
15.3 QFP  
15.3.1 REFLOW SOLDERING  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Reflow soldering techniques are suitable for all QFP  
packages.  
15.3.3 REPAIRING SOLDERED JOINTS  
The choice of heating method may be influenced by larger  
plastic QFP packages (44 leads, or more). If infrared or  
vapour phase heating is used and the large packages are  
not absolutely dry (less than 0.1% moisture content by  
weight), vaporization of the small amount of moisture in  
them can cause cracking of the plastic body. For more  
information, refer to the Drypack chapter in our “Quality  
Reference Handbook” (order code 9397 750 00192).  
Fix the component by first soldering two diagonally-  
opposite end leads. Use only a low voltage soldering iron  
(less than 24 V) applied to the flat part of the lead. Contact  
time must be limited to 10 seconds at up to 300 °C. When  
using a dedicated tool, all other leads can be soldered in  
one operation within 2 to 5 seconds between  
270 and 320 °C.  
1996 Jan 26  
40  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
16 DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
17 LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
18 PURCHASE OF PHILIPS I2C COMPONENTS  
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the  
components in the I2C system provided the system conforms to the I2C specification defined by  
Philips. This specification can be ordered using the code 9398 393 40011.  
1996 Jan 26  
41  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
NOTES  
1996 Jan 26  
42  
Philips Semiconductors  
Objective specification  
I2C-bus controlled PAL/NTSC TV processors  
TDA8376; TDA8376A  
NOTES  
1996 Jan 26  
43  
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© Philips Electronics N.V. 1996  
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Date of release: 1996 Jan 26  
9397 750 00592  
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TDA8376;  
TDA8376A; I²C-bus  
controlled  
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PAL/NTSC TV  
processors  
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The TDA8376 and TDA8376A are alignment-free I²C-bus controlled video processors which contain a  
PAL/NTSC colour decoder, luminance processor, sync processor, RGB-control and deflection processor.  
The circuits have been designed for use with the baseband chrominance delay line TDA4665 and for DC-  
coupled vertical and East-West (E-W) output stages. Both ICs are pin compatible. The TDA8376A has a  
flexible horizontal and vertical zoom possibility for 16 : 9 applications.  
End of Life  
information  
Distributors Go  
Here!  
•
•
Models  
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The supply voltage for the ICs is 8 V. The ICs are available in an SDIP package with 52 pins and in a QFP  
package with 64 pins .  
SoC solutions  
The pin numbers indicated in this document are referenced to the SDIP52; SOT247-1 package; unless  
otherwise indicated.  
to
Features  
●
●
Source selection with 2 CVBS inputs and a Y/C (or extra CVBS) input  
Output signals of the video switch circuit for the teletext decoder and a Picture-In-Picture (PIP)  
processor  
●
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Video identification circuit which is independent of the synchronization for stable On Screen Display  
(OSD) under ‘no-signal’ conditions  
Integrated chrominance trap with pre-shoot compensation and bandpass filters (automatically  
calibrated)  
●
●
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Integrated luminance delay line  
Asymmetrical peaking in the luminance channel with a (defeatable) noise coring function  
Black stretcher circuit in the luminance channel  
PAL/NTSC colour decoder with automatic search system  
Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications  
RGB control circuit with black-current stabilization and white point adjustment; to obtain a good  
grey scale tracking the black-current ratio of the 3 guns depends on the white point adjustment  
Two linear RGB inputs and fast blanking  
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Horizontal synchronization with two control loops and alignment-free horizontal oscillator  
Vertical count-down circuit  
Geometry correction by modulation of the vertical and E-W drive  
Vertical and horizontal zoom possibility for 16 : 9 applications (TDA8376A only)  
I²C-bus control of various functions  
Low dissipation (700 mW)  
Small amount of peripheral components compared with competition ICs  
Y, U and V inputs and outputs.  
to
Applications  
AN00039_1: Application information for TDA8359J deflection output circuit (date 01-Aug-00)  
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Datasheet  
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(kB)  
TDA8376;  
TDA8376A  
I²C-bus  
26-Jan-96  
Objective  
specification  
44  
190  
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PAL/NTSC TV  
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Products, packages, availability and ordering  
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Ordering code  
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American (12NC)  
online  
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type  
number  
SOT247-1  
(SDIP52)  
Standard Marking *  
Tube  
Full production  
Full production  
TDA8376/N1  
9350 698 50112  
-
-
Standard Marking *  
9350 895 30518 Reel Dry Pack, SMD,  
13"  
SOT319  
TDA8376H/N2  
Products in the above table are all in production. Some variants are discontinued; click here for information  
on these variants.  
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TDA8376; TDA8376A links to the similar products page containing an overview of products that are  
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similar in function or related to the type number(s) as listed on this page. The similar products page includes  
products from the same catalog tree(s), relevant selection guides and products from the same functional  
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I²C-bus allocation table General(date 01-Mar-97)  
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