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935192720118 [NXP]

ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24;
935192720118
型号： 935192720118
厂家： NXP    NXP
描述：

ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24

输入元件 信息通信管理 光电二极管 输出元件 逻辑集成电路
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74ABT652A  
Octal transceiver/register; non-inverting; 3-state  
Rev. 02 — 12 March 2010  
Product data sheet  
1. General description  
The 74ABT652A high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT652A transceiver/register consists of bus transceiver circuits with 3-state  
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of  
data directly from the input bus or the internal registers. Data on the A or B bus will be  
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.  
Output Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for bus  
management.  
2. Features and benefits  
I Independent registers for A and B buses  
I Multiplexed real-time and stored data  
I 3-state outputs  
I Live insertion/extraction permitted  
I Power-up 3-state  
I Power-up reset  
I Output capability: +64 mA to −32 mA  
I Latch-up protection exceeds 500 mA per JESD78B class II level A  
I ESD protection:  
N HBM JESD22-A114F exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74ABT652AD  
−40 °C to +85 °C  
SO24  
plastic small outline package; 24 leads; body width  
7.5 mm  
SOT137-1  
74ABT652ADB −40 °C to +85 °C  
74ABT652APW −40 °C to +85 °C  
SSOP24  
plastic shrink small outline package; 24 leads; body width SOT340-1  
5.3 mm  
TSSOP24 plastic thin shrink small outline package; 24 leads; body SOT355-1  
width 4.4 mm  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
4. Block diagram  
21  
EN1[BA]  
3
EN2[AB]  
23  
C4  
22  
G5  
1
C6  
2
G7  
20  
4
≥1  
5
4D  
2
1
5
1
4
5
6
7
8
9
10 11  
6D  
7
≥1  
1
7
5
6
19  
18  
17  
16  
15  
14  
13  
A0 A1 A2 A3 A4 A5 A6 A7  
CPBA  
23  
22  
2
SBA  
OEAB  
OEBA  
3
7
SAB  
21  
8
1
CPAB  
9
B0 B1 B2 B3 B4 B5 B6 B7  
10  
11  
20 19 18 17 16 15 14 13  
001aae846  
001aae845  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
2 of 19  
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
REAL TIME BUS TRANSFER  
BUS B TO BUS A  
REAL TIME BUS TRANSFER  
BUS A TO BUS B  
STORAGE FROM  
A, B, OR A AND B  
TRANSFER STORED DATA  
TO A OR B  
A
B
A
B
A
B
A
B
OEAB OEBA CPAB CPBA SAB SBA  
OEAB OEBA CPAB CPBA SAB SBA  
OEAB OEBA CPAB CPBA SAB SBA  
OEAB OEBA CPAB CPBA SAB SBA  
H/L H/L  
L
L
X
X
X
L
H
H
X
X
L
X
X
L
L
H
X
H
X
X
X
X
X
X
X
H
L
H
H
X
001aae847  
Fig 3. Real time bus transfer and storage  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
21  
OEBA  
3
OEAB  
23  
CPBA  
22  
SBA  
1
CPAB  
2
SAB  
1 of 8 channels  
1D  
C1  
Q
4
20  
B0  
A0  
1D  
C1  
Q
5
A1  
6
19  
B1  
18  
B2  
17  
B3  
16  
A2  
7
A3  
8
DETAIL A × 7  
A4  
9
B4  
B5  
B6  
B7  
15  
14  
13  
A5  
10  
A6  
11  
A7  
001aae848  
Fig 4. Logic diagram  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
4 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
5. Pinning information  
5.1 Pinning  
74ABT652A  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CPAB  
SAB  
OEAB  
A0  
V
CC  
CPBA  
SBA  
OEBA  
B0  
3
4
5
A1  
6
A2  
B1  
7
A3  
B2  
8
A4  
B3  
9
A5  
B4  
10  
11  
12  
A6  
B5  
A7  
B6  
GND  
B7  
001aae844  
Fig 5. Pin configuration  
5.2 Pin description  
Table 2.  
Pin description  
Symbol  
Pin  
1
Description  
CPAB  
A to B clock input  
SAB  
2
A to B select input  
OEAB  
3
A to B output enable input  
data input/output (A side)  
ground (0 V)  
A0, A1, A2, A3, A4, A5, A6, A7  
4, 5, 6, 7, 8, 9, 10, 11  
12  
GND  
B0, B1, B2, B3, B4, B5, B6, B7  
20, 19, 18, 17, 16, 15, 14, 13  
data input/output (B side)  
B to A output enable input (active LOW)  
B to A select input  
OEBA  
SBA  
21  
22  
23  
24  
CPBA  
VCC  
B to A clock input  
positive supply voltage  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
5 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
6. Functional description  
6.1 Function table  
Table 3.  
Function table [1]  
Inputs  
Data I/O  
An  
Operating mode  
OEAB  
OEBA  
CPAB  
CPBA  
H or L  
↑
SAB  
X
SBA  
X
Bn  
L
L
X
H
H
H
H or L  
input  
input  
input  
input  
input  
isolation  
↑
↑
X
X
store A and B data  
store A, hold B  
H or L  
X
X
unspecified  
output [2]  
[3]  
H
L
L
H
X
L
↑
↑
↑
↑
X
input  
unspecified  
output [2]  
store A in both registers  
hold A, store B  
H or L  
X
X
X
unspecified  
output [2]  
input  
[3]  
↑
unspecified  
output [2]  
input  
store B in both registers  
L
L
X
X
X
X
L
L
output  
output  
input  
input  
real time B data to A bus  
stored B data to A bus  
real time A data to B bus  
store A data to B bus  
L
L
X
H or L  
X
H
X
X
H
input  
H
H
H
H
H
L
X
output  
output  
output  
H or L  
H or L  
X
H
H
input  
H or L  
output  
stored A data to B bus;  
stored B data to A bus  
[1] H = HIGH voltage level;  
L = LOW voltage level;  
X = don’t care;  
↑ = LOW-to-HIGH clock transition.  
[2] The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always  
enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.  
[3] If both select controls (SAB and SBA) are LOW, then clocks can occur simultaneously. If either select control is HIGH, the clocks must  
be staggered in order to load both registers.  
Figure 3 demonstrates the four fundamental bus-management functions that can be  
performed with the 74ABT652A.  
The select pins determine whether data is stored or transferred through the device in real  
time.  
The output enable pins determine the direction of the data flow.  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
6 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
−0.5  
−1.2  
−0.5  
−18  
−50  
-
Max  
+7.0  
+7.0  
+5.5  
-
Unit  
V
supply voltage  
[1]  
[1]  
input voltage  
V
VO  
output voltage  
output in OFF-state or HIGH-state  
VI < 0 V  
V
IIK  
input clamping current  
output clamping current  
output current  
mA  
mA  
mA  
°C  
°C  
IOK  
IO  
VO < 0 V  
-
output in LOW-state  
128  
150  
+150  
[2]  
Tj  
junction temperature  
storage temperature  
-
Tstg  
−65  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction  
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.  
8. Recommended operating conditions  
Table 5.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
4.5  
0
Typ  
Max  
5.5  
VCC  
-
Unit  
V
supply voltage  
-
-
-
-
-
-
-
-
VI  
input voltage  
V
VIH  
HIGH-level input voltage  
LOW-level input voltage  
HIGH-level output current  
LOW-level output current  
input transition rise and fall rate  
ambient temperature  
2.0  
-
V
VIL  
0.8  
-
V
IOH  
−32  
-
mA  
mA  
ns/V  
°C  
IOL  
64  
∆t/∆V  
Tamb  
0
10  
in free air  
−40  
+85  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
7 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
9. Static characteristics  
Table 6.  
Static characteristics  
Symbol Parameter  
Conditions  
25 °C  
−40 °C to +85 °C Unit  
Min  
Typ Max  
Min  
Max  
VIK  
input clamping voltage  
VCC = 4.5 V; IIK = −18 mA  
VI = VIL or VIH  
−1.2 −0.9  
-
−1.2  
-
V
VOH  
HIGH-level output  
voltage  
VCC = 4.5 V; IOH = −3 mA  
VCC = 5.0 V; IOH = −3 mA  
VCC = 4.5 V; IOH = −32 mA  
2.5  
3.0  
2.0  
-
3.0  
3.5  
2.4  
-
-
-
2.5  
3.0  
2.0  
-
-
V
V
V
V
-
-
VOL  
LOW-level output voltage VCC = 4.5 V; IOL = 64 mA;  
VI = VIL or VIH  
0.3 0.55  
0.55  
[1]  
VOL(pu) power-up LOW-level  
output voltage  
VCC = 5.5 V; IO = 1 mA;  
VI = GND or VCC  
-
0.13 0.55  
-
0.55  
V
II  
input leakage current  
VCC = 5.5 V; VI = GND or 5.5 V  
control pins  
-
-
-
-
±0.01 ±1.0  
±5 ±100  
±5.0 ±100  
±5.0 ±50  
-
-
-
-
±1.0  
µA  
data pins  
±100 µA  
±100 µA  
IOFF  
power-off leakage current VCC = 0 V; VI or VO ≤ 4.5 V  
[2]  
IO(pu/pd) power-up/power-down  
output current  
VCC = 2.1 V; VO = 0.5 V;  
VI = GND or VCC; OEAB, OEBA  
don’t care  
±50  
µA  
IOZ  
OFF-state output current VCC = 5.5 V; VI = VIL or VIH  
VO = 2.7 V  
VO = 0.5 V  
-
-
-
5.0  
−5.0 −50  
5.0 50  
50  
-
-
-
50  
−50  
50  
µA  
µA  
µA  
ILO  
output leakage current  
VCC = 5.5 V; HIGH-state;  
VO = 5.5 V; VI = GND or VCC  
[3][5]  
IO  
output current  
supply current  
VCC = 5.5 V; VO = 2.5 V  
VCC = 5.5 V; VI = GND or VCC  
outputs HIGH-state  
−180 −65 −40  
−180  
−40  
mA  
ICC  
-
-
-
-
110 250  
20 30  
110 250  
-
-
-
-
250  
30  
µA  
outputs LOW-state  
mA  
µA  
outputs disabled  
250  
1.5  
[4]  
∆ICC  
additional supply current per input pin; VCC = 5.5 V; one  
input at 3.4 V; other inputs at VCC  
or GND  
0.3  
1.5  
mA  
CI  
input capacitance  
output capacitance  
VI = 0 V or VCC  
-
-
4
7
-
-
-
-
-
-
pF  
pF  
CO  
outputs disabled; VO = 0 V  
or VCC  
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.  
[2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a  
transition time of up to 100 µs is permitted.  
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
[4] This is the increase in supply current for each input at 3.4 V.  
[5] This data sheet limit may vary among suppliers.  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
8 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
GND = 0 V; for test circuit, see Figure 12.  
Symbol Parameter  
Conditions  
25 °C; VCC = 5.0 V −40 °C to +85 °C; Unit  
V
CC = 5.0 V ± 0.5 V  
Min Typ Max  
Min  
Max  
fmax  
tPLH  
maximum  
frequency  
see Figure 6  
125 300  
-
125  
-
MHz  
LOW to HIGH  
propagation delay  
CPAB to Bn or CPBA to An; see Figure 6  
An to Bn or Bn to An; see Figure 7  
SAB to Bn or SBA to An; see Figure 8  
CPAB to Bn or CPBA to An; see Figure 6  
An to Bn or Bn to An; see Figure 7  
SAB to Bn or SBA to An; see Figure 8  
2.2  
1.5  
1.5  
1.7  
1.5  
1.5  
2
3.7  
3.0  
3.5  
4.3  
3.6  
5.1  
4.3  
5.1  
5.1  
4.6  
2.2  
1.5  
1.5  
1.7  
1.5  
1.5  
2
5.6  
4.8  
6.5  
5.6  
5.4  
5.9  
5.8  
6.5  
8.5  
7.4  
5.3[1]  
5.5  
4.1  
5.1  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPHL  
HIGH to LOW  
propagation delay  
4.2 5.2[1]  
tPZH  
tPZL  
tPHZ  
tPLZ  
OFF-state to HIGH OEBA to An; see Figure 10  
propagation delay  
3.2  
3.5  
4.5  
4.7  
4.6  
6.1  
6.8  
6.5  
OEAB to Bn; see Figure 10  
2
2
OFF-state to LOW OEBA to An; see Figure 11  
propagation delay  
3
3
OEAB to Bn; see Figure 11  
3
3
HIGH to OFF-state OEBA to An; see Figure 10  
propagation delay  
1.5  
1.5  
1.5  
1.5  
3.0  
3.0  
3.9 4.7[1]  
3.8 4.6[1]  
1.5  
1.5  
1.5  
1.5  
3.0  
3.0  
0.0  
0.0  
4.0  
4.0  
OEAB to Bn; see Figure 10  
LOW to OFF-state OEBA to An; see Figure 11  
propagation delay  
2.9  
3.0  
0.7  
0.7  
3.8  
OEAB to Bn; see Figure 11  
4.4  
tsu(H)  
tsu(L)  
th(H)  
th(L)  
tWH  
set-up time HIGH  
set-up time LOW  
hold time HIGH  
hold time LOW  
An to CPAB, Bn to CPBA; see Figure 9  
-
-
-
-
-
-
An to CPAB, Bn to CPBA; see Figure 9  
An to CPAB, Bn to CPBA; see Figure 9  
An to CPAB, Bn to CPBA; see Figure 9  
CPAB, CPBA; see Figure 6  
-
0.0 −0.5  
0.0 −0.5  
-
-
pulse width HIGH  
pulse width LOW  
4.0  
4.0  
1.0  
1.0  
-
tWL  
CPAB, CPBA; see Figure 6  
-
[1] This data sheet limit may vary among suppliers.  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
9 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
11. Waveforms  
1 / f  
max  
V
I
V
I
An or Bn  
GND  
V
V
M
M
CPBA or  
CPAB  
V
V
V
M
M
M
GND  
t
t
WL  
t
t
PHL  
WH  
PLH  
t
PLH  
t
V
PHL  
OH  
V
OH  
Bn or An  
V
V
M
M
An or Bn  
V
V
M
M
V
OL  
V
OL  
001aae904  
001aae839  
VM = 1.5 V  
VM = 1.5 V  
Fig 6. Propagation delay, clock input to output, clock  
pulse width, and maximum clock frequency  
Fig 7. Propagation delay, An to Bn or Bn to An  
V
I
SBA or SAB  
GND  
V
V
M
M
t
t
PHL  
PLH  
V
OH  
An or Bn  
V
M
V
M
V
OL  
001aae852  
VM = 1.5 V  
Fig 8. Propagation delay, SBA to An or SAB to Bn  
V
I
V
V
V
M
V
M
An, Bn  
M
M
GND  
t
t
t
t
h(L)  
su(H)  
h(H)  
su(L)  
t
WL  
V
I
CPBA or  
CPAB  
V
V
M
M
GND  
001aae849  
VM = 1.5 V  
The shaded areas indicate when the input is permitted to change for predictable output performance.  
Fig 9. Data set-up and hold times  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
10 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
V
OEBA  
I
V
V
M
M
OEAB GND  
t
t
PHZ  
PZH  
V
OH  
V
− 0.3 V  
OH  
An or Bn  
V
M
GND  
001aae851  
VM = 1.5 V  
Fig 10. 3-state output enable time to HIGH-level and output disable time from HIGH-level  
V
OEBA  
I
V
V
M
M
OEAB GND  
3.5 V  
t
t
PLZ  
PZL  
An or Bn  
V
M
V
OL  
+ 0.3 V  
V
OL  
001aae853  
VM = 1.5 V  
Fig 11. 3-state output enable time to LOW-level and output disable time from LOW-level  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
11 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
t
W
V
I
90 %  
90 %  
negative  
pulse  
V
EXT  
V
V
M
M
V
10 %  
10 %  
CC  
0 V  
R
L
V
V
O
t
t
r
I
f
G
DUT  
t
t
f
r
V
I
R
T
C
L
R
L
90 %  
90 %  
positive  
pulse  
V
M
V
M
mna616  
10 %  
10 %  
0 V  
t
W
001aai298  
a. Input pulse definition  
b. Test circuit  
Test data and VEXT levels are given in Table 8.  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
VEXT = Test voltage for switching times.  
Fig 12. Test circuit for measuring switching times  
Table 8.  
Input  
VI  
Test data  
Load  
CL  
VEXT  
fI  
tW  
tr, tf  
RL  
tPHL, tPLH  
open  
tPZH, tPHZ  
tPZL, tPLZ  
7.0 V  
3.0 V  
1 MHz  
500 ns  
≤ 2.5 ns  
50 pF  
500 Ω  
open  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
12 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
12. Package outline  
SO24: plastic small outline package; 24 leads; body width 7.5 mm  
SOT137-1  
D
E
A
X
c
H
v
M
A
E
y
Z
24  
13  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
12  
w
detail X  
e
M
b
p
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
max.  
(1)  
(1)  
(1)  
UNIT  
mm  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3  
0.1  
2.45  
2.25  
0.49  
0.36  
0.32  
0.23  
15.6  
15.2  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.1  
1.0  
0.9  
0.4  
2.65  
0.1  
0.25  
0.01  
1.27  
0.05  
1.4  
0.25  
0.25  
0.1  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.019 0.013 0.61  
0.014 0.009 0.60  
0.30  
0.29  
0.419  
0.394  
0.043 0.043  
0.016 0.039  
0.035  
0.016  
inches  
0.055  
0.01  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT137-1  
075E05  
MS-013  
Fig 13. Package outline SOT137-1 (SO24)  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
13 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm  
SOT340-1  
D
E
A
X
v
c
H
M
A
y
E
Z
24  
13  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
12  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
8.4  
8.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
0.8  
0.4  
mm  
2
0.65  
1.25  
0.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT340-1  
MO-150  
Fig 14. Package outline SOT340-1 (SSOP24)  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
14 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm  
SOT355-1  
D
E
A
X
c
H
v
M
A
y
E
Z
13  
24  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
1
12  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
7.9  
7.7  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.5  
0.2  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT355-1  
MO-153  
Fig 15. Package outline SOT355-1 (TSSOP24)  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
15 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
13. Abbreviations  
Table 9.  
Acronym  
BiCMOS  
DUT  
Abbreviations  
Description  
Bipolar Complementary Metal-Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
HBM  
Human Body Model  
MM  
Machine Model  
14. Revision history  
Table 10. Revision history  
Document ID  
74ABT652A_2  
Modifications:  
Release date  
20100312  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
74ABT652A  
• The format of this data sheet has been redesigned to comply with the new identity guidelines  
of NXP Semiconductors.  
• Legal texts have been adapted to the new company name where appropriate.  
• DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12  
“Package outline”.  
74ABT652A  
19950419  
Product specification  
-
-
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
16 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
suitable for use in medical, military, aircraft, space or life support equipment,  
15.2 Definitions  
nor in applications where failure or malfunction of an NXP Semiconductors  
product can reasonably be expected to result in personal injury, death or  
severe property or environmental damage. NXP Semiconductors accepts no  
liability for inclusion and/or use of NXP Semiconductors products in such  
equipment or applications and therefore such inclusion and/or use is at the  
customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on a weakness or default in the  
customer application/use or the application/use of customer’s third party  
customer(s) (hereinafter both referred to as “Application”). It is customer’s  
sole responsibility to check whether the NXP Semiconductors product is  
suitable and fit for the Application planned. Customer has to do all necessary  
testing for the Application in order to avoid a default of the Application and the  
product. NXP Semiconductors does not accept any liability in this respect.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
15.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation -  
lost profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use in automotive applications — This NXP  
Semiconductors product has been qualified for use in automotive  
applications. The product is not designed, authorized or warranted to be  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
17 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74ABT652A_2  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 02 — 12 March 2010  
18 of 19  
74ABT652A  
NXP Semiconductors  
Octal transceiver/register; non-inverting; 3-state  
17. Contents  
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 1  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
6
6.1  
7
Functional description . . . . . . . . . . . . . . . . . . . 6  
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Recommended operating conditions. . . . . . . . 7  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16  
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 18  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2010.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 12 March 2010  
Document identifier: 74ABT652A_2  

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