935198490118 [NXP]
IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16, FF/Latch;
| 型号： | 935198490118 |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总15页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112
Dual JK flip-flop with set and reset;
negative-edge trigger
1998 Jun 10
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
FEATURES
• Asynchronous set and reset
• Output capability: standard
• ICC category: flip-flops
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nSD) and reset (nRD) inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PHL/ tPLH
PARAMETER
CONDITIONS
UNIT
HC
HCT
t
propagation delay
nCP to nQ, nQ
CL = 15 pF; VCC = 5 V
17
15
18
66
3.5
27
19
ns
nSD to nQ, nQ
15
19
70
3.5
30
ns
nRD to nQ, nQ
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
CPD
power dissipation capacitance per flip-flop notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Jun 10
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
74HC112D;
74HCT112D
SO16
SSOP16
DIP16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC112DB;
74HCT112DB
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic dual in-line package; 16 leads (300 mil); long body
SOT338-1
SOT38-1
74HC112N;
74HCT112N
74HC112PW;
74HCT112PW
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
clock input (HIGH-to-LOW, edge triggered)
data inputs; flip-flops 1 and 2
data inputs; flip-flops 1 and 2
set inputs (active LOW)
true flip-flop outputs
1, 13
2, 12
3, 11
4, 10
5, 9
1CP, 2CP
1K, 2K
1J, 2J
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
6, 7
complement flip-flop outputs
ground (0 V)
8
15, 14
16
1RD, 2RD
VCC
reset inputs (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jun 10
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
nSD
nRD nCP nJ
nK
nQ
nQ
asynchronous set
asynchronous reset
undetermined
toggle
L
H
L
H
L
X
X
X
↓
X
X
X
h
l
X
X
X
h
h
l
H
L
L
H
L
L
H
q
H
H
H
H
H
H
H
H
q
load “0” (reset)
load “1” (set)
↓
L
H
L
↓
h
l
H
q
hold “no change”
↓
l
q
Note
1. If nSD and nRD simultaneously go from LOW to HIGH, the output states will
be unpredictable.
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition
q = lower case letters indicate the state of the referenced output one set-up
time prior to the HIGH-to-LOW CP transition
X = don’t care
Fig.4 Functional diagram.
↓ = HIGH-to-LOW CP transition
Fig.5 Logic diagram (one flip-flop).
1998 Jun 10
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
1998 Jun 10
5
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
55
20
16
55
20
16
58
21
17
50
18
14
19
7
175
35
220
44
265
53
2.0
propagation delay
nCP to nQ
t
PHL/ tPLH
PHL/ tPLH
PHL/ tPLH
PHL/ tPLH
ns
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6
30
37
45
175
35
220
44
265
53
propagation delay
nCP to nQ
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
30
37
45
180
36
225
45
270
54
propagation delay
nRD to nQ, nQ
31
38
46
155
31
295
39
235
47
propagation delay
nSD to nQ, nQ
26
33
40
75
95
110
22
tTHL/ tTLH output transition time
15
19
6
13
16
19
80
16
14
80
16
14
80
16
14
80
16
14
80
16
14
0
22
8
100
20
17
100
20
17
125
25
21
100
20
17
100
20
17
0
120
24
20
120
24
20
150
30
26
120
24
20
120
24
20
0
clock pulse width
HIGH or LOW
tW
6
22
8
set or reset pulse width
LOW
tW
6
22
8
removal time
nRD to nCP
trem
6
−19
−7
−6
19
7
removal time
nSD to nCP
trem
set-up time
tsu
nJ, nK to nCP
6
−11
−4
−3
20
60
71
hold time
nJ, nK to nCP
th
0
0
0
0
0
0
6
4.8
24
28
4.0
20
24
maximum clock pulse
frequency
fmax
30
35
1998 Jun 10
6
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
1SD, 2SD
1K, 2K
0.5
0.6
0.65
1
1RD, 2RD
1J, 2J
1CP, 2CP
1
1998 Jun 10
7
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
propagation delay
nCP to nQ
t
PHL/ tPLH
21
23
22
35
40
37
44
50
46
53
60
56
ns
ns
ns
4.5
4.5
4.5
Fig.6
Fig.6
Fig.7
propagation delay
nCP to nQ
tPHL/ tPLH
propagation delay
nRD to nQ, nQ
t
PHL/ tPLH
PHL/ tPLH
propagation delay
nSD to nQ, nQ
t
18
7
32
15
40
19
48
22
ns
ns
ns
4.5
4.5
4.5
Fig.7
Fig.6
Fig.6
tTHL/ tTLH output transition time
clock pulse width
HIGH or LOW
tW
16
18
20
20
16
0
8
20
23
25
25
20
0
24
27
30
30
24
0
set or reset pulse width
LOW
tW
10
11
−8
7
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
Fig.7
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6
removal time
nRD to nCP
trem
removal time
nSD to nCP
trem
set-up time
tsu
nJ, nK to nCP
hold time
nJ, nK to nCP
th
−7
64
maximum clock pulse
frequency
fmax
30
24
20
MHz 4.5
1998 Jun 10
8
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width,
the nJ, nK to nCP set-up times, the nCP to nJ, nK hold times, the output transition times and the maximum
clock pulse frequency.
(1)
V
M
nCP INPUT
t
rem
(1)
t
V
nS INPUT
D
M
t
W
rem
t
W
(1)
V
nR INPUT
D
M
t
t
PHL
PLH
(1)
nQ OUTPUT
V
M
t
t
PLH
PHL
(1)
nQ OUTPUT
V
M
MBK218
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set
and reset pulse width and the nRD and nSD to nCP removal time.
1998 Jun 10
9
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1998 Jun 10
10
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-01-14
95-02-04
SOT338-1
MO-150AC
1998 Jun 10
11
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1998 Jun 10
12
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT403-1
MO-153
1998 Jun 10
13
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
between 50 and 300 seconds depending on heating
method.
SOLDERING
Introduction
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
WAVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
DIP
SOLDERING BY DIPPING OR BY WAVE
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
SO, SSOP and TSSOP
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REFLOW SOLDERING
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
1998 Jun 10
14
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
one operation within 2 to 5 seconds between
270 and 320 °C.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 10
15
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