935203020118_技术文档

74LVT16500A

3.3 V 18-bit universal bus transceiver; 3-state

Rev. 03 — 29 May 2006

Product data sheet

1. General description

The 74LVT16500A is a high-performance BiCMOS product designed for V_CCoperation at

3.3 V.

This device is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data ﬂow in each direction is

controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock

(CPAB and CPBA) inputs. For A-to-B data ﬂow, the device operates in the transparent

mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a

HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on

the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When

OEAB is LOW, the outputs are in the high-impedance state.

Data ﬂow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).

Active bus-hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic

level.

2. Features

I 18-bit bidirectional bus interface

I 3-state buffers

I Output capability: +64 mA and −32 mA

I TTL input and output switching levels

I Input and output interface capability to systems at 5 V supply

I Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

I Live insertion/extraction permitted

I Power-up reset

I Power-up 3-state

I No bus current loading when output is tied to 5 V bus

I Negative edge-triggered clock inputs

I Latch-up protection:

N JESD78: exceeds 500 mA

I ESD protection:

N MIL STD 883 Method 3015: exceeds 2000 V

N CDM JESD22-C101-C exceeds 1000 V

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVT16500ADGG −40 °C to +85 °C

TSSOP56 plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

74LVT16500ADL −40 °C to +85 °C

SSOP56

plastic shrink small outline package; 56 leads;

body width 7.5 mm

SOT371-1

4. Functional diagram

1

OEAB

CPAB

LEAB

EN1

2C3

55

2

C3

G2

27

30

28

OEBA

CPBA

LEBA

EN4

5C6

C6

G5

30 28 27 55

2

1

3

54

A0

3D

4

1

B0

54

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

B0

A0

A1

3

5

6D

5

6

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

B1

A1

A2

B1

B2

A2

6

B2

8

B3

A3

8

A3

B3

9

B4

A4

9

A4

B4

10

12

13

14

15

16

17

19

20

21

23

24

26

B5

A5

10

12

13

14

15

16

17

19

20

21

23

24

26

A5

B5

B6

A6

B6

B7

A7

B7

B8

A8

B8

B9

A9

B9

B10

B11

B12

B13

B14

B15

B16

B17

A10

A11

A12

A13

A14

A15

A16

A17

A10

A11

A12

A13

A14

A15

A16

A17

B10

B11

B12

B13

B14

B15

B16

B17

001aaf038

001aaf039

Fig 1. Logic symbol

Fig 2. IEC logic symbol

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

2 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

1

OEAB

CPAB

LEAB

LEBA

CPBA

OEBA

A0

55

2

28

30

27

3

1D

C1

54

B0

CLK

1D

C1

CLK

001aaf035

to 17 other channels

Fig 3. Logic diagram

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

3 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

5. Pinning information

5.1 Pinning

74LVT16500A

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

OEAB

LEAB

A0

GND

CPAB

B0

2

3

4

GND

A1

GND

B1

5

6

A2

B2

7

V

CC

V

CC

8

A3

B3

9

A4

A5

B4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

B5

GND

A6

GND

B6

A7

B7

A8

B8

A9

B9

A10

A11

GND

A12

A13

A14

B10

B11

GND

B12

B13

B14

V

CC

V

CC

A15

A16

B15

B16

GND

A17

GND

B17

OEBA

LEBA

CPBA

GND

001aaf040

Fig 4. Pin conﬁguration

5.2 Pin description

Table 2.

Symbol

OEAB

LEAB

A0

Pin description

1

Description

A-to-B output enable input

A-to-B latch enable input

data input/output A0

ground (0 V)

2

3

GND

A1

4

5

data input/output A1

data input/output A2

supply voltage

A2

6

V_CC

7

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

4 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

Table 2.

Symbol

A3

Pin description …continued

8

Description

data input/output A3

A4

9

data input/output A4

data input/output A5

ground (0 V)

A5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

GND

A6

data input/output A6

data input/output A7

data input/output A8

data input/output A9

data input/output A10

data input/output A11

ground (0 V)

A7

A8

A9

A10

A11

GND

A12

A13

A14

V_CC

A15

A16

GND

A17

OEBA

LEBA

GND

CPBA

B17

GND

B16

B15

V_CC

B14

B13

B12

GND

B11

B10

B9

data input/output A12

data input/output A13

data input/output A14

supply voltage

data input/output A15

data input/output A16

ground (0 V)

data input/output A17

B-to-A output enable input (active LOW)

B-to-A latch enable input

ground (0 V)

B-to-A clock input (active falling edge)

data input/output B17

ground (0 V)

data input/output B16

data input/output B15

supply voltage

data input/output B14

data input/output B13

data input/output B12

ground (0 V)

data input/output B11

data input/output B10

data input/output B9

data input/output B8

data input/output B7

data input/output B6

ground (0 V)

B8

B7

B6

GND

B5

data input/output B5

data input/output B4

B4

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

5 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

Table 2.

Symbol

B3

Pin description …continued

49

50

51

52

53

54

55

56

Description

data input/output B3

V_CC

supply voltage

B2

data input/output B2

data input/output B1

ground (0 V)

B1

GND

B0

data input/output B0

A-to-B clock input (active falling edge)

ground (0 V)

CPAB

GND

6. Functional description

Table 3.

Function table^[1]

Operating mode

Control

Input

Internal

register

Output

OEAB

LEAB

CPAB

An

Bn

X

h

l

Bn

An

Z

OEBA

LEBA

CPBA

disabled

L

H

↓

X

H

L

disabled, latch data

disabled, hold data

disabled, clock data

transparent

L

X

Z

L

↓

X

Z

L

H

↓

H or L

X

h

l

NC

H

L

Z

L

↓

Z

L

↓

Z

H

X

H

L

h

l

H

L

H

L

transparent

X

latch data and display

clock data and display

hold data and display

X

H

L

H

L

↓

X

L

↓

h

l

H

L

H

L

↓

H or L

X

H

L

H

L

[1] H = HIGH voltage level;

h = HIGH voltage level one setup time prior to the enable or clock transition;

L = LOW voltage level;

l = LOW voltage level one setup time prior to the enable or clock transition;

NC = no change;

X = don’t care;

Z = high-impedance OFF-state;

↓ = HIGH-to-LOW enable or clock transition.

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

6 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max Unit

V_CC

V_I

supply voltage

input voltage

output voltage

−0.5 +4.6

−0.5 +7.0

V

[1]

V

V_O

I_IK

output in OFF-state or HIGH-state

V

input clamping current V_I< 0 V

output clamping current V_O< 0 V

-

−50

128

−64

mA

I_OK

I_O

-

output current

output in LOW-state

output in HIGH-state

-

T_stg

T_j

storage temperature

junction temperature

−65

+150 °C

150 °C

[2]

-

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings

are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal

environment can create junction temperatures which are detrimental to reliability.

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Conditions

Symbol Parameter

Min Typ Max Unit

V_CC

V_I

supply voltage

2.7

-

3.6

5.5

-

V

input voltage

0

V_IH

V_IL

I_OH

I_OL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output current

2.0

-

0.8

−32 mA

LOW-level output current none

32

64

mA

current duty cycle ≤ 50 %;

f_i≥ 1 kHz

∆t/∆V

input transition rise and

fall rate

outputs enabled

-

10

ns/V

T_amb

ambient temperature

in free air

−40

+85 °C

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

7 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to 85 °C^[1]

V_IK

input clamping voltage

V_CC= 2.7 V; I_IK= −18 mA

V_CC= 2.7 V to 3.6 V; I_OH= −100 µA

V_CC= 2.7 V; I_OH= −8 mA

V_CC= 3.0 V; I_OH= −32 mA

V_CC= 2.7 V

-

−0.85 −1.2

V

V_OH

HIGH-level output voltage

V

_CC− 0.2 V_CC

-

2.4

2.0

2.55

2.3

-

V_OL

LOW-level output voltage

I_OL= 100 µA

-

0.07

0.3

0.2

0.5

V

I_OL= 24 mA

V_CC= 3.0 V

I_OL= 16 mA

-

0.25

0.3

0.4

V

I_OL= 32 mA

0.5

I_OL= 64 mA

0.36

0.1

0.55

[2]

[3]

V_RST

I_LI

power-up output low voltage V_CC= 3.6 V; I_O= 1 mA; V_I= V_CCor GND

input leakage current

control pins

V_CC= 3.6 V; V_I= V_CCor GND

V_CC= 0 V or 3.6 V; V_I= 5.5 V

V_CC= 3.6 V

-

0.1

±1

µA

10

I/O data pins

V_I= 5.5 V

-

1.0

20

10

−5

µA

V_I= V_CC

0.1

V_I= 0 V

+0.1

1.0

I_OFF

power-off leakage current

bus hold current data input

V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

V_CC= 3 V

±100 µA

[4]

I_HOLD

V_I= 0.8 V

75

130

−130

-

µA

V_I= 2.0 V

−75

±500

-

V_I= 0 V to 3.6 V; V_CC= 3.6 V

-

I_EX

external current into output

output in the HIGH-state when V_O> V_CC

;

50

125

V_O= 5.5 V; V_CC= 3.0 V

[5]

I_O(pu/pd)power-up/power-down

output current

V

_CC≤ 1.2 V; V_O= 0.5 V to V_CC; V_I= GND

-

40

±100 µA

or V_CC; OEAB or OEBA don’t care

V_CC= 3.6 V; V_I= GND or V_CC; I_O= 0 A

outputs HIGH-state

I_CC

quiescent supply current

-

0.07

4

0.12

6

mA

outputs LOW-state

[6]

outputs disabled

0.07

0.12

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

8 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions

additional quiescent supply per input pin; V_CC= 3 V to 3.6 V; one input

Min

Typ

Max

Unit

[7]

∆I_CC

-

0.1

0.2

mA

current

at V_CC− 0.6 V; other inputs at V_CCor GND

C_i

input capacitance

input/output capacitance

control pins; V_I= 0 V or 3.0 V

-

3

9

-

pF

C_io

I/O pins; V_I/O= 0 V or 3.0 V

[1] Typical values are at V_CC= 3.3 V and T_amb= 25 °C.

[2] For valid test results, data must not be loaded into the ﬂip-ﬂops (or latches) after applying power.

[3] Unused pins at V_CCor GND.

[4] This is the bus hold overdrive current required to force the input to the opposite logic state.

[5] This parameter is valid for any V_CCbetween 0 V and 1.2 V with a transition time of up to 10 ms. From V_CC= 1.2 V to V_CC= 3.0 V ± 0.3 V

a transition time of 100 µs is permitted. This parameter is valid for T_amb= 25 °C only.

[6] I_CCis measured with outputs pulled to V_CCor GND.

[7] This is the increase in supply current for each input at the speciﬁed voltage level other than V_CCor GND.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_CC= 2.7 V; T_amb= −40 °C to 85 °C

t_PLH

propagation delay

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

-

5.4

6.4

ns

CPAB to Bn or CPBA to An

LEAB to Bn or LEBA to An

propagation delay

t_PHL

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

see Figure 8

see Figure 9

-

5.4

6.4

5.5

5.2

6.3

5.6

ns

CPAB to Bn or CPBA to An

LEAB to Bn or LEBA to An

output enable time to HIGH-level

output enable time to LOW-level

t_PZH

t_PZL

t_PHZ

t_PLZ

t_su(H)

output disable time from HIGH-level see Figure 8

output disable time from LOW-level see Figure 9

setup time HIGH

An to CPAB or Bn to CPBA

see Figure 10

2.5

2.2

-

ns

An to LEAB with CPAB LOW or

Bn to LEBA with CPBA LOW

An to LEAB with CPAB HIGH or see Figure 10

Bn to LEBA with CPBA HIGH

2.7

-

ns

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

9 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_su(L)

setup time LOW

An to CPAB or Bn to CPBA

see Figure 10

2.5

2.2

-

ns

An to LEAB with CPAB LOW or

Bn to LEBA with CPBA LOW

An to LEAB with CPAB HIGH or see Figure 10

Bn to LEBA with CPBA HIGH

2.7

-

ns

t_h(H)

t_h(L)

t_WH

t_WL

hold time HIGH

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

hold time LOW

see Figure 10

0

-

ns

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

pulse width HIGH

see Figure 10

0

-

ns

CPAB or CPBA

see Figure 6

see Figure 7

1.5

-

ns

LEAB or LEBA

pulse width LOW

CPAB or CPBA

see Figure 6

1.5

-

ns

V_CC= 3.0 V ± 0.3 V; T_amb= −40 °C to 85 °C^[1]

t_PLH

propagation delay

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

0.5

1.0

1.9

3.2

2.4

4.2

5.4

ns

CPAB to Bn or CPBA to An

LEAB to Bn or LEBA to An

propagation delay

t_PHL

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

see Figure 8

see Figure 9

0.5

1.0

1.9

3.2

2.9

2.4

2.2

2.8

3.2

4.2

5.4

4.8

5.8

5.2

ns

CPAB to Bn or CPBA to An

LEAB to Bn or LEBA to An

output enable time to HIGH-level

output enable time to LOW-level

t_PZH

t_PZL

t_PHZ

t_PLZ

t_su(H)

output disable time from HIGH-level see Figure 8

output disable time from LOW-level see Figure 9

setup time HIGH

An to CPAB or Bn to CPBA

see Figure 10

2.4

2.3

1.0

0.9

-

ns

An to LEAB with CPAB LOW or

Bn to LEBA with CPBA LOW

An to LEAB with CPAB HIGH or see Figure 10

Bn to LEBA with CPBA HIGH

2.4

0.9

-

ns

t_su(L)

setup time LOW

An to CPAB or Bn to CPBA

see Figure 10

2.4

2.3

0.7

0.9

-

ns

An to LEAB with CPAB LOW or

Bn to LEBA with CPBA LOW

An to LEAB with CPAB HIGH or see Figure 10

Bn to LEBA with CPBA HIGH

2.4

0.8

-

ns

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

10 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_h(H)

hold time HIGH

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

hold time LOW

see Figure 10

0

-

ns

t_h(L)

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

pulse width HIGH

see Figure 10

0

-

ns

t_WH

CPAB or CPBA

see Figure 6

see Figure 7

1.2

0.8

-

ns

LEAB or LEBA

t_WL

pulse width LOW

CPAB or CPBA

see Figure 6

1.2

0.8

-

ns

f_max

maximum input clock frequency

150

350

MHz

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

11. Waveforms

V

I

input

An or Bn

V

M

t

0 V

t

PLH

PHL

V

OH

output

Bn or An

V

M

V

OL

001aad308

Measurements points are given in Table 8.

V_OLand V_OHare typical voltage output drop that occur with the output load.

Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

11 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

1/f

max

V

I

input CPBA

or CPAB

V

t

V

t

M

0 V

t

WH

WL

PHL

PLH

V

OH

V

M

output An or Bn

M

V

OL

001aaf037

Measurements points are given in Table 8.

V_OLand V_OHare typical voltage output drop that occur with the output load.

Fig 6. Propagation delay clock (CPAB, CPBA) to output (An, Bn), clock (CPAB, CPBA)

pulse width and maximum clock frequency (CPAB, CPBA)

V

I

input LEAB

or LEBA

V

M

0 V

t

WH

t

PLH

PHL

V

OH

output

An or Bn

V

M

V

OL

001aad310

Measurements points are given in Table 8.

V_OLand V_OHare typical voltage output drop that occur with the output load.

Fig 7. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable

(LEAB, LEBA) pulse width

OEBA

input

V

I

V

M

t

0 V

OEAB

t

PZH

PHZ

V

OH

V

Y

output

An or Bn

V

M

0 V

001aad344

Measurements points are given in Table 8.

V_OHis typical voltage output drop that occur with the output load.

Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

12 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

V

I

OEBA

input

V

M

t

0 V

OEAB

t

PZL

PLZ

3.0 V or V

CC

output

An or Bn

V

M

V

X

V

OL

001aad346

Measurements points are given in Table 8.

V_OLis typical voltage output drop that occur with the output load.

Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level

CPAB or CPBA

input

3.0 V or V

CC

whichever is

less

V

M

LEAB or LEBA

0 V

t

h(L)

su(H)

h(H)

su(L)

3.0 V or V

CC

whichever is

less

input An, Bn

V

M

0 V

001aaf036

Measurements points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output

performance.

Fig 10. Data setup and hold times

Table 8.

Measurement points

Supply voltage

Input

V_M

Output

V_M

V_X

V_Y

2.7 V

3.3 V

1.5 V

V_OL+ 0.3 V

V

_OH− 0.3 V

V

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

13 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

V

CC

R

L

V

O

I

PULSE

GENERATOR

DUT

R

T

C

L

R

L

001aae235

Test data is given in Table 9.

Deﬁnitions test circuit:

R_L= Load resistor.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= Test voltage for switching times.

Fig 11. Load circuitry for switching times

Table 9.

Input

V_I

Test data

Load

C_L

V_EXT

f_i

t_W

t_r, t_f

R_L

t_PHZ, t_PZHt_PLZ, t_PZLt_PLH, t_PHL

2.7 V

≤ 10 MHz 500 ns

≤ 2.5 ns 50 pF

500 Ω

GND

6 V

open

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

14 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

12. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig 12. Package outline SOT364-1 (TSSOP56)

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

15 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm

SOT371-1

D

E

A

X

c

y

H

v

M

A

E

Z

29

56

Q

A

2

A

(A )

3

1

θ

pin 1 index

L

p

L

28

1

detail X

w

M

b

p

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

Q

v

w

y

Z

θ

p

1

2

3

max.

8^o

0^o

0.4

0.2

2.35

2.20

0.3

0.2

0.22 18.55

0.13 18.30

7.6

7.4

10.4

10.1

1.0

0.6

1.2

1.0

0.85

0.40

mm

2.8

0.25

0.635

1.4

0.25

0.18

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT371-1

MO-118

Fig 13. Package outline SOT371-1 (SSOP56)

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

16 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

BiCMOS

DUT

Description

Bipolar Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Transistor-Transistor Logic

TTL

14. Revision history

Table 11. Revision history

Document ID

74LVT16500A_3

Modiﬁcations:

Release date

20060529

Data sheet status

Change notice

Supersedes

Product data sheet

-

74LVT16500A_2

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of Philips Semiconductors

• Section 2 “Features”: replaced JEDEC JC40.2 Std 17 with JESD78

• Figure 3 “Logic diagram”: corrected clock names and pin names

• Table 7 “Dynamic characteristics”: splitting up t_su(H)and t_su(L)parameter ‘An to LEAB or Bn

to LEBA’ in 2 parameters with clock conditions and new values

74LVT16500A_2

(9397 750 03556)

19980219

Product speciﬁcation

-

74LVT16500A_1

74LVT16500A

19970612

19950320

Product speciﬁcation

-

74LVT16500A

-

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

17 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.semiconductors.philips.com.

malfunction of a Philips Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. Philips Semiconductors accepts no liability for inclusion and/or use

of Philips Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is for the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. Philips Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Philips Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local Philips Semiconductors

sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet,

the full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — Philips Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.semiconductors.philips.com/proﬁle/terms, including those

pertaining to warranty, intellectual property rights infringement and limitation

of liability, unless explicitly otherwise agreed to in writing by Philips

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, Philips Semiconductors does not give any representations

or warranties, expressed or implied, as to the accuracy or completeness of

such information and shall have no liability for the consequences of use of

such information.

Semiconductors. In case of any inconsistency or conﬂict between information

in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — Philips Semiconductors reserves the right to

make changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — Philips Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

74LVT16500A_3

Product data sheet

Rev. 03 — 29 May 2006

18 of 19

74LVT16500A

Philips Semiconductors

3.3 V 18-bit universal bus transceiver; 3-state

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 6

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended operating conditions. . . . . . . . 7

Static characteristics. . . . . . . . . . . . . . . . . . . . . 8

Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.semiconductors.philips.com.

For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.

Date of release: 29 May 2006

Document identifier: 74LVT16500A_3


型号：	935203020118
厂家：	NXP
描述：	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56 光电二极管输出元件
文件：	总19页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935203020118 [NXP]

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