935203330118 [NXP]

ABT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48;


型号：	935203330118
厂家：	NXP
描述：	ABT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 驱动光电二极管输出元件
文件：	总11页 (文件大小：98K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

74ABT16373B

16-bit transparent latch (3-State)

Product data

2004 Feb 27

Replaces 74ABT16373B/74ABTH16373B of 1998 Feb 27

Philips

Semiconductors

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

FEATURES

PIN CONFIGURATION

• 16-bit transparent latch

1OE

1Q0

1Q1

GND

1Q2

1Q3

• Multiple V and GND pins minimize switching noise

1D0

• Power-up 3-State

46 1D1

GND

1D2

• Live insertion/extraction permitted

• Power-up reset

43 1D3

• 3-State output buffers

• Output capability: +64 mA/–32 mA

1Q4

1Q5

1D4

1D5

• I

–19 mA maximum

CCL

GND

• Latch-up protection exceeds 500 mA per JEDEC Std 17

1Q6

1Q7

2Q0

2Q1

GND

1D6

1D7

2D0

2D1

GND

• ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

DESCRIPTION

The 74ABT16373B high-performance BiCMOS device combines

low static and dynamic power dissipation with high speed and high

output drive.

2Q2

2Q3

2D2

2D3

The 74ABT16373B device is a dual octal transparent latch coupled

to two sets of eight 3-State output buffers. The two sections of the

device are controlled independently by Enable (nE) and Output

Enable (nOE) control gates.

2Q4

2D4

29 2D5

2Q5 20

GND

2Q6

GND

2D6

The data on each set of D inputs are transferred to the latch outputs

when the Latch Enable (nE) input is HIGH. The latch remains

transparent to the data inputs while nE is HIGH, and stores the data

that is present one set-up time before the HIGH-to-LOW enable

transition.

2Q7

2OE

2D7

SA00379

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors. Each

active-LOW Output Enable (nOE) controls eight 3-State buffers

independent of the latch operation.

When nOE is LOW, the latched or transparent data appears at the

outputs. When nOE is HIGH, the outputs are in the high-impedance

“OFF” state, which means they will neither drive nor load the bus.

QUICK REFERENCE DATA

CONDITIONS

= 25 °C; GND = 0 V

SYMBOL

PARAMETER

TYPICAL

UNIT

amb

Propagation delay

Dn to Qn

2.5

2.0

PLH

PHL

C = 50 pF; V = 5 V

Input capacitance

Output capacitance

V = 0 V or V

V = 0 V or V ; 3-State

O CC

OUT

CCZ

Outputs disabled; V = 5.5 V

500

µA

Quiescent supply current

Outputs low; V = 5.5 V

CCL

ORDERING INFORMATION

amb

= –40 °C to +85 °C

Package

Name

Type number

Description

Version

74ABT16373BDL

SSOP48

TSSOP48

plastic shrink small outline package; 48 leads; body width 7.5 mm

plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT370-1

SOT362-1

74ABT16373BDGG

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

PIN DESCRIPTION

LOGIC SYMBOL (IEEE/IEC)

PIN NUMBER

SYMBOL

FUNCTION

Data inputs

47, 46, 44, 43, 41, 40,

38, 37, 36, 35, 33, 32,

30, 29, 27, 26

1EN

1OE

1D0 – 1D7

2D0 – 2D7

2EN

2OE

2, 3, 5, 6, 8, 9, 11, 12,

13, 14, 16, 17, 19, 20,

22, 23

1Q0 – 1Q7

2Q0 – 2Q7

Data outputs

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

Output enable inputs

(active-LOW)

1, 24

1OE, 2OE

1E, 2E

GND

Enable inputs

(active-HIGH)

48, 25

4, 10, 15, 21, 28, 34,

39, 45

Ground (0 V)

7, 18, 31, 42

Positive supply voltage

LOGIC SYMBOL

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

47 46 44 43 41 40 38 37

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

1OE

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

SA00380

11 12

36 35 33 32 30 29 27 26

2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

13 14 16 17 19 20 22 23

SA00044

LOGIC DIAGRAM

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

SA00046

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

FUNCTION TABLE

INPUTS

OUTPUTS

nQ0 – nQ7

INTERNAL

OPERATING MODE

nOE

nDx

Enable and read register

↓

Latch and read register

Hold

Disable outputs

HIGH voltage level

HIGH voltage level one set-up time prior to the HIGH-to-LOW E transition

LOW voltage level

LOW voltage level one set-up time prior to the HIGH-to-LOW E transition

NC= No change

↓

Don’t care

High-impedance “off” state

HIGH-to-LOW E transition

1, 2

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

–0.5 to +7.0

–18

UNIT

DC input diode current

V < 0 V

DC input voltage

–1.2 to +7.0

–50

DC output diode current

< 0 V

OUT

DC output voltage

output in Off or HIGH state

output in LOW state

–0.5 to +5.5

128

DC output current

OUT

output in HIGH state

–64

stg

Storage temperature range

–65 to 150

°C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

UNIT

MIN

4.5

MAX

DC supply voltage

5.5

Input voltage

HIGH-level input voltage

LOW-level Input voltage

HIGH-level output current

LOW-level output current

Input transition rise or fall rate

Operating free-air temperature range

2.0

–

0.8

–32

–

ns/V

°C

–

∆t/∆v

amb

–40

+85

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

DC ELECTRICAL CHARACTERISTICS

LIMITS

= +25 °C

= –40 °C

to +85 °C

amb

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

–0.9

2.9

MAX

–1.2

–

MIN

MAX

–1.2

–

Input clamp voltage

= 4.5 V; I = –18 mA

–

2.5

3.0

2.0

–

= 4.5 V; I = –3 mA; V = V or V

2.5

3.0

2.0

–

High-level output voltage

Low-level output voltage

= 5.0 V; I = –3 mA; V = V or V

3.4

–

= 4.5 V; I = –32 mA; V = V or V

2.4

–

= 4.5 V; I = 64 mA; V = V or V

0.42

0.13

0.55

±1

0.55

±1

RST

Power-up output voltage

Input leakage current

= 5.5 V; I = 1 mA; V = GND or V

–

= 5.5 V; V = V or GND

–

±0.01

±5.0

–

µA

Power-off leakage current

Power-up/down 3-State

= 0.0 V; V or V ≤ 4.5 V

–

±100

–

±100

OFF

= 2.1 V; V = 0.5 V; V = GND or V

;

–

±5.0

±50

–

±50

µA

PU PD

output current

= GND

3-State output HIGH

current

= 5.5 V; V = 5.5 V; V = V or V

0.5

OZH

3-State output LOW current

= 5.5 V; V = 0.0 V; V = V or V

–

–0.5

–70

–10

µA

OZL

Output current

= 5.5 V; V = 2.5 V

–50

–180

–50

–

–180

Output HIGH leakage

current

= 5.5 V; V = 5.5 V; V = GND or V

–

0.1

0.5

µA

CEX

CCH

= 5.5 V; Outputs HIGH;

–

V = GND or V

= 5.5 V; Outputs Low;

Quiescent supply current

CCL

V = GND or V

= 5.5 V; Outputs 3-State;

0.5

CCZ

V = GND or V

Additional supply current

= 5.5 V; one input at 3.4 V, other inputs

∆I

100

per input pin

at V or GND

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4 V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V between 0 V and 2.1 V, with a transition time of up to 10 msec. From V = 2.1 to V = 5 V ± 10% a

transition time of up to 100 µsec is permitted.

5. Unused pins at V or GND.

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

AC CHARACTERISTICS

GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω

LIMITS

= +25 °C

= +5.0 V

= –40 °C to +85 °C

amb

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0V ± 0.5 V

MIN

TYP

MAX

MIN

MAX

Propagation delay

nDx to nQx

1.5

1.1

2.5

2.0

3.8

3.1

1.5

1.1

4.4

3.8

PLH

PHL

Propagation delay

nE to nQx

1.6

1.3

2.5

2.1

3.8

3.1

1.6

1.3

4.4

3.6

PLH

PHL

Output enable time

to HIGH and LOW level

1.2

1.3

2.3

3.5

1.2

1.3

4.6

4.5

PZH

PZL

Output disable time

from HIGH and LOW level

1.9

1.7

3.1

2.6

4.5

3.8

1.9

1.7

5.3

4.2

PHZ

PLZ

AC SET-UP REQUIREMENTS

GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω

LIMITS

= +25 °C

= +5.0 V

= –40 °C to +85 °C

amb

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0 V ± 0.5 V

MIN

TYP

MIN

t (H)

t (L)

Set-up time, HIGH or LOW

nDx to nE

1.0

0.0

0.3

1.0

t (H)

Hold time, HIGH or LOW

nDx to nE

0.5

–0.2

0.0

0.5

t (L)

Enable pulse width

HIGH

t (H)

2.5

1.0

2.5

AC WAVEFORMS

For all waveforms, V = 1.5 V.

nDx

nQx

(H)

PLH

PHL

PLH

PHL

nQx

SA00047

SA00048

Waveform 1. Propagation Delay, Enable to Output, and

Enable Pulse Width

Waveform 2. Propagation Delay for Data to Outputs

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

nDx

nOE

nQx

t (H)

t (L)

t (H)

t (L)

PLZ

PZL

+ 0.3V

NOTE: The shaded areas indicate when the input is per-

mitted to change for predictable output performance.

SA00051

SA00049

Waveform 3. Data Set-up and Hold Times

Waveform 5. 3-State Output Enable Time to LOW Level and

Output Disable Time from LOW Level

nOE

nQx

PHZ

PZH

– 0.3V

SA00050

Waveform 4. 3-State Output Enable Time to HIGH Level and

Output Disable Time from HIGH Level

TEST CIRCUIT AND WAVEFORM

AMP (V)

90%

7.0 V

NEGATIVE

PULSE

10%

90%

0 V

OUT

PULSE

GENERATOR

D.U.T.

)

TLH

)

THL

)

(t )

TLH

THL F

AMP (V)

90%

POSITIVE

PULSE

Test Circuit for 3-State Outputs

10%

0 V

SWITCH POSITION

= 1.5 V

TEST

SWITCH

Input Pulse Definition

closed

PLZ

closed

open

PZL

All other

INPUT PULSE REQUIREMENTS

DEFINITIONS

R = Load resistor; see AC CHARACTERISTICS for value.

FAMILY

Amplitude

3.0 V

Rep. Rate

1 MHz

C = Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

74ABT

500 ns 2.5 ns 2.5 ns

R = Termination resistance should be equal to Z

OUT

pulse generators.

SA00654

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

SOT370-1

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

REVISION HISTORY

Rev

Date

Description

20040227

Product data (9397 750 12821); 853-1751 ECN 01–A15429 of 27 January 2004.

Replaces data sheet 74ABT_H16373B_2 of 1998 Feb 27 (9397 750 03491).

Modifications:

• Delete all references to 74ABTH16373B (product discontinued).

19980227

19950803

Product specification (9397 750 03491); ECN 853-1751 19027 of 27 February 1998.

Supersedes data of 1995 Aug 03.

2004 Feb 27

Philips Semiconductors

Product data

16-bit transparent latch (3-State)

74ABT16373B

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 01-04

9397 750 12985

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

2004 Feb 27

935203330118 [NXP]

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