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74ALVT16501

18-bit universal bus transceiver; 3-state

Rev. 04 — 8 August 2005

Product data sheet

1. General description

The 74ALVT16501 is a high-performance Bipolar Complementary Metal Oxide

Semiconductor (BiCMOS) product designed for V_CCoperation at 2.5 V and 3.3 V with

I/O compatibility up to 5 V. This device is an 18-bit universal transceiver featuring

non-inverting 3-state bus compatible outputs in both send and receive directions.

Data ﬂow in each direction is controlled by output enable (OEAB and OEBA), latch enable

(LEAB and LEBA), and clock (CPAB and CPBA) inputs.

For A-to-B data ﬂow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.

If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on the LOW-to-HIGH

transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the

outputs are in the high-impedance state.

Active bus hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic

level.

Data ﬂow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).

2. Features

■ 18-bit bidirectional bus interface

■ 5 V I/O compatible

■ 3-state buffers

■ Output capability: +64 mA to −32 mA

■ TTL and LVTTL input and output switching levels

■ Bus hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

■ Live insertion and extraction permitted

■ Power-up reset

■ Power-up 3-state

■ No bus current loading when output is tied to 5 V bus

■ Positive-edge triggered clock inputs

■ Latch-up protection:

◆ JESD78: exceeds 500 mA

■ ESD protection:

◆ MIL STD 883, method 3015: exceeds 2000 V

◆ Machine model: exceeds 400 V

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C.

Symbol Parameter

V_CC= 2.5 V

Conditions

Min

Typ

Max Unit

t_PLH

propagation delay An to Bn or

Bn to An

C_L= 30 pF

-

2.0

2.1

-

ns

t_PHL

propagation delay An to Bn or

Bn to An

C_i

input capacitance of control pins V_I= 0 V or V_CC

-

4

8

-

pF

C_io

input/output capacitance of

I/O pins

V_I/O= 0 V or V_CC

I_CC

quiescent supply current

outputs disabled

-

40

-

µA

V_CC= 3.3 V

t_PLHpropagation delay An to Bn or

C_L= 50 pF

-

1.8

1.9

-

ns

Bn to An

t_PHL

propagation delay An to Bn or

Bn to An

C_i

input capacitance of control pins V_I= 0 V or V_CC

-

4

8

-

pF

C_io

input/output capacitance of

I/O pins

V_I/O= 0 V or V_CC

I_CC

quiescent supply current

outputs disabled

-

60

-

µA

4. Ordering information

Table 2:

Ordering information

Type number

Package

Temperature range Name

Description

Version

74ALVT16501DL

−40 °C to +85 °C

SSOP56

plastic shrink small outline package; 56 leads;

body width 7.5 mm

SOT371-1

74ALVT16501DGG −40 °C to +85 °C

TSSOP56

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

2 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

5. Functional diagram

1

OEAB

CPAB

LEAB

EN1

2C3

55

2

C3

G2

30 28 27 55

2

1

27

30

28

OEBA

CPBA

LEBA

EN4

5C6

54

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

B0

A0

A1

3

5

C6

G5

B1

B2

A2

6

3

54

B3

A3

8

A0

3D

4

1

B0

B4

A4

9

6D

5

6

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

B5

A5

10

12

13

14

15

16

17

19

20

21

23

24

26

A1

A2

B1

B6

A6

B2

8

B7

A7

A3

B3

9

B8

A8

A4

B4

10

12

13

14

15

16

17

19

20

21

23

24

26

B9

A9

A5

B5

B10

B11

B12

B13

B14

B15

B16

B17

A10

A11

A12

A13

A14

A15

A16

A17

A6

B6

A7

B7

A8

B8

A9

B9

A10

A11

A12

A13

A14

A15

A16

A17

B10

B11

B12

B13

B14

B15

B16

B17

001aad339

001aad338

Fig 1. Logic symbol

Fig 2. IEC logic symbol

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

3 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

1

OEAB

LEBA

CPBA

CPAB

LEAB

28

30

55

2

27

OEBA

C1

ID

C1

ID

1 of 18 channels

3

54

A0

B0

C1

ID

C1

ID

001aad340

to 17 other channels

Fig 3. Logic diagram

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

4 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

6. Pinning information

6.1 Pinning

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

OEAB

LEAB

A0

GND

CPAB

B0

2

3

4

GND

A1

GND

B1

5

6

A2

B2

7

V

CC

V

CC

8

A3

B3

9

A4

A5

B4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

B5

GND

A6

GND

B6

A7

B7

A8

B8

16501

A9

B9

A10

A11

GND

A12

A13

A14

B10

B11

GND

B12

B13

B14

V

CC

V

CC

A15

A16

B15

B16

GND

A17

GND

B17

OEBA

LEBA

CPBA

GND

001aad337

Fig 4. Pin conﬁguration

6.2 Pin description

Table 3:

Symbol

OEAB

LEAB

A0

Pin description

1

Description

A-to-B output enable input

A-to-B latch enable input

data input or output (A side)

ground (0 V)

2

3

GND

A1

4

5

data input or output (A side)

voltage supply

A2

6

V_CC

7

A3

8

data input or output (A side)

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

5 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

Table 3:

Symbol

A4

Pin description …continued

9

Description

data input or output (A side)

A5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

data input or output (A side)

ground (0 V)

GND

A6

data input or output (A side)

ground (0 V)

A7

A8

A9

A10

A11

GND

A12

A13

A14

V_CC

A15

A16

GND

A17

OEBA

LEBA

GND

CPBA

B17

GND

B16

B15

V_CC

B14

B13

B12

GND

B11

B10

B9

data input or output (A side)

voltage supply

data input or output (A side)

ground (0 V)

data input or output (A side)

B-to-A output enable input (active LOW)

B-to-A latch enable input

ground (0 V)

B-to-A clock input (active rising edge)

data input or output (B side)

ground (0 V)

data input or output (B side)

voltage supply

data input or output (B side)

ground (0 V)

data input or output (B side)

ground (0 V)

B8

B7

B6

GND

B5

data input or output (B side)

B4

B3

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

6 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

Table 3:

Symbol

V_CC

Pin description …continued

50

51

52

53

54

55

56

Description

voltage supply

B2

data input or output (B side)

ground (0 V)

B1

GND

B0

data input or output (B side)

A-to-B clock input (active rising edge)

ground (0 V)

CPAB

GND

7. Functional description

7.1 Function table

Table 4:

Function table^[1]

Operating mode

Control

Input

Internal

Output

registers

OEAB

LEAB

LEBA

H

CPAB

CPBA

X

An

Bn

X

h

l

Bn

An

Z

OEBA

Disabled

L

X

H

L

Disabled, latch data

↓

X

Z

Disabled, hold data

Disabled, clock data

L

H or L

X

h

l

NC

H

L

Z

↑

Z

Transparent

H

↓

X

H

L

h

l

H

L

H

L

Latch data and display

Clock data and display

Hold data and display

X

H

L

H

L

↑

h

l

H

L

H

L

H or L

X

H

L

H

L

[1] H = HIGH voltage level;

h = HIGH voltage level one setup time prior to the enable or clock transition;

L = LOW voltage level;

I = LOW voltage level one setup time prior to the enable or clock transition;

NC = no change;

X = don’t care;

Z = high-impedance OFF-state;

↓ = HIGH-to-LOW enable or clock transition;

↑ = LOW-to-HIGH enable or clock transition.

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

7 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

8. Limiting values

Table 5:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max Unit

V_CC

V_I

supply voltage

input voltage

−0.5 +4.6

−0.5 +7.0

V

[1]

V

V_O

I_IK

output voltage

output in OFF-state or HIGH-state

V_I< 0 V

V

input diode current

output diode current

output current

-

−50

128

−64

mA

I_OK

I_O

V_O< 0 V

-

output in LOW-state

output in HIGH-state

-

T_stg

T_j

storage temperature

junction temperature

−65

+150 °C

150 °C

[2]

-

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings

are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal

environment can create junction temperatures which are detrimental to reliability.

9. Recommended operating conditions

Table 6:

Recommended operating conditions

Symbol Parameter

Conditions

Min

Typ

Max Unit

V_CC= 2.5 V ± 0.2 V

V_CC

V_I

supply voltage

2.3

-

2.7

5.5

-

V

input voltage

0

V

V_IH

V_IL

I_OH

I_OL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output current

1.7

V

-

0.7

−8

8

V

mA

LOW-level output current none

current duty cycle ≤ 50 %;

24

f ≥ 1 kHz

∆t/∆V

input transition rise or fall outputs enabled

rate

-

10

ns/V

T_amb

ambient temperature

free air

−40

+85

°C

V_CC= 3.3 V ± 0.3 V

V_CC

V_I

supply voltage

3.0

0

-

3.6

5.5

-

V

input voltage

V

V_IH

V_IL

I_OH

HIGH-level input voltage

LOW-level input voltage

HIGH-level output current

2.0

-

V

0.8

−32

V

-

mA

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

8 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

Table 6:

Recommended operating conditions …continued

Conditions

LOW-level output current none

Symbol Parameter

Min

Typ

Max Unit

I_OL

-

32

64

mA

current duty cycle ≤ 50 %;

f ≥ 1 kHz

∆t/∆V

input transition rise or fall outputs enabled

rate

-

10

ns/V

T_amb

ambient temperature

free air

−40

+85

°C

10. Static characteristics

Table 7:

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

_amb= −40 °C to +85 °C.

Static characteristics

T

Symbol Parameter

Conditions

Min

Typ

Max Unit

V_CC= 2.5 V ± 0.2 V^[1]

V_IK

input diode voltage

V_CC= 2.3 V; I_IK= −18 mA

-

−0.85 −1.2

V

V_OH

HIGH-level output voltage

V_CC= 2.3 V to 3.6 V; I_OH= −100 µA

V_CC

0.2

−

-

V_CC= 2.3 V; I_OH= −8 mA

V_CC= 2.3 V; I_OL= 100 µA

V_CC= 2.3 V; I_OL= 24 mA

V_CC= 2.3 V; I_OL= 8 mA

1.8

-

V

V_OL

LOW-level output voltage

-

0.07 0.2

0.3

0.5

-

0.4

[2]

V_RST

I_LI

power-up LOW-state output voltage

V_CC= 2.7 V; I_O= 1 mA;

V_I= V_CCor GND

0.55

input leakage current

control pins

V_CC= 2.7 V; V_I= V_CCor GND

V_CC= 0 V or 2.7 V; V_I= 5.5 V

V_CC= 2.7 V; V_I= V_CC

-

0.1

±1

10

1

µA

[3]

I/O data pins

-

V_CC= 2.7 V; V_I= 0 V

+0.1 −5

I_OFF

power-down leakage current

bus hold current data inputs

V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

V_CC= 2.3 V; V_I= 0.7 V

0.1

90

−75

5

±100 µA

[4]

I_HOLD

-

µA

V_CC= 2.3 V; V_I= 1.7 V

-

I_EX

external current into output

output in HIGH-state when V_O> V_CC

V_O= 5.5 V; V_CC= 2.3 V

;

125

[5]

I_PU, I_PDpower-up/down 3-state output current V_CC≤ 1.2 V; V_O= 0.5 V to V_CC

;

-

4

100

µA

V_I= GND or V_CC; OEAB or OEBA

don’t care

I_CC

quiescent supply current

V_CC= 2.7 V; V_I= GND or V_CC; I_O= 0 A

outputs HIGH-state

-

0.04 0.1

2.5 4.5

mA

outputs LOW-state

[6]

[7]

outputs disabled

0.04 0.1

0.01 0.4

∆I_CC

additional quiescent supply current

per input pin

V_CC= 2.3 V to 2.7 V; one input at

_CC− 0.6 V, other inputs at

V

V_CCor GND

C_i

input capacitance of control pins

V_I= 0 V or V_CC

-

4

-

pF

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

9 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

Table 7:

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

_amb= −40 °C to +85 °C.

Static characteristics …continued

T

Symbol Parameter

Conditions

Min

Typ

Max Unit

C_io

input/output capacitance of I/O pins

V_I/O= 0 V or V_CC

-

8

-

pF

V_CC= 3.3 V ± 0.3 V^[8]

V_IK

input diode voltage

V_CC= 3.0 V; I_IK= −18 mA

-

−0.85 −1.2

V

V_OH

HIGH-level output voltage

V_CC= 3.0 V to 3.6 V; I_OH= −100 µA

V

_CC− V_CC

-

0.2

V_CC= 3.0 V; I_OH= −32 mA

V_CC= 3.0 V; I_OL= 100 µA

V_CC= 3.0 V; I_OL= 16 mA

V_CC= 3.0 V; I_OL= 32 mA

V_CC= 3.0 V; I_OL= 64 mA

2.0

2.3

-

V

V_OL

LOW-level output voltage

-

0.07 0.2

0.25 0.4

0.3

0.4

-

0.5

0.55

[2]

V_RST

I_LI

power-up LOW-state output voltage

V_CC= 3.6 V; I_O= 1 mA;

V_I= V_CCor GND

input leakage current

control pins

V_CC= 3.6 V; V_I= V_CCor GND

V_CC= 0 V or 3.6 V; V_I= 5.5 V

V_CC= 3.6 V; V_I= 5.5 V

-

0.1

0.5

±1

10

20

10

µA

-

[3]

I/O data pins

-

V_CC= 3.6 V; V_I= V_CC

-

V_CC= 3.6 V; V_I= 0 V

-

+0.1 −5

I_OFF

power-down leakage current

bus hold current data inputs

V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

V_CC= 3 V; V_I= 0.8 V

-

0.1

130

−140

-

±100 µA

[9]

I_HOLD

75

-

µA

V_CC= 3 V; V_I= 2.0 V

−75

±500

-

V_CC= 0 V to 3.6 V; V_I= 3.6 V

-

I_EX

external current into output

output in HIGH-state when V_O> V_CC

V_O= 5.5 V; V_CC= 3.0 V

;

10

125

[10]

I_PU, I_PDpower-up/down 3-state output current V_CC≤ 1.2 V; V_O= 0.5 V to V_CC

;

-

1.0

±100 µA

V_I= GND or V_CC; OEAB or OEBA

don’t care

I_CC

quiescent supply current

V_CC= 3.6 V; V_I= GND or V_CC; I_O= 0 A

outputs HIGH-state

-

0.06 0.1

3.5

mA

outputs LOW-state

5

[6]

[7]

outputs disabled

0.06 0.1

0.04 0.4

∆I_CC

additional quiescent supply current

per input pin

V_CC= 3 V to 3.6 V; one input at

_CC− 0.6 V, other inputs at

V

V_CCor GND

C_i

input capacitance of control pins

input/output capacitance of I/O pins

V_I= 0 V or V_CC

-

4

8

-

pF

C_io

V_I/O= 0 V or V_CC

[1] All typical values are at V_CC= 2.5 V and T_amb= 25 °C.

[2] For valid test results, data must not be loaded into the ﬂip-ﬂops (or latches) after applying power.

[3] Unused pins at V_CCor GND.

[4] Not guaranteed.

[5] This parameter is valid for any V_CCbetween 0 V and 1.2 V with a transition time of up to 10 ms. From V_CC= 1.2 V to V_CC= 2.5 V ± 0.2 V

a transition time of 100 µs is permitted. This parameter is valid for T_amb= 25 °C only.

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

10 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

[6] I_CCis measured with outputs pulled up to V_CCor pulled down to ground.

[7] This is the increase in supply current for each input at the speciﬁed voltage level other than V_CCor GND.

[8] All typical values are at V_CC= 3.3 V and T_amb= 25 °C.

[9] This is the bus hold overdrive current required to force the input to the opposite logic state.

[10] This parameter is valid for any V_CCbetween 0 V and 1.2 V with a transition time of up to 10 ms. From V_CC= 1.2 V to V_CC= 3.3 V ± 0.3 V

a transition time of 100 µs is permitted. This parameter is valid for T_amb= 25 °C only.

11. Dynamic characteristics

Table 8:

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

_amb= −40 °C to +85 °C.

Dynamic characteristics

T

Symbol Parameter

Conditions

Min

Typ

Max Unit

V_CC= 2.5 V ± 0.2 V^[1]; C_L= 30 pF

t_PLH

propagation delay

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

1.0

1.5

2.2

2.0

2.4

3.6

3.0

4.0

5.4

ns

LEAB to Bn or LEBA to An

CPAB to Bn or CPBA to An

propagation delay

t_PHL

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

see Figure 9

see Figure 10

see Figure 9

see Figure 10

1.4

1.5

1.9

2.3

1.9

2.2

1.6

2.1

2.3

3.2

3.9

3.3

3.4

2.8

3.5

4.0

5.4

5.0

4.4

3.4

ns

LEAB to Bn or LEBA to An

CPAB to Bn or CPBA to An

output enable time to HIGH-level

output enable time to LOW-level

output disable time from HIGH-level

output disable time from LOW-level

hold time HIGH

t_PZH

t_PZL

t_PHZ

t_PLZ

t_h(H)

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEAB

hold time LOW

see Figure 8

0

−1.2

-

ns

+1.0 −0.5

t_h(L)

t_su(H)

t_su(L)

t_WH

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEAB

set-up time HIGH

see Figure 8

+1.0 −0.4

-

ns

2.0

1.0

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

set-up time LOW

see Figure 8

1.9

0

0.4

-

ns

−1.0

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

pulse width HIGH

see Figure 8

2.5

1.2

-

ns

+1.0 −0.5

CPAB or CPBA

see Figure 7

see Figure 6

3.0

1.5

-

ns

LEAB or LEBA

t_WL

pulse width LOW

CPAB or CPBA

see Figure 7

3.0

-

ns

f_max

maximum clock frequency

150

MHz

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

11 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

Table 8:

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

T

_amb= −40 °C to +85 °C.

Symbol Parameter

Conditions

Min

Typ

Max Unit

V_CC= 3.3 V ± 0.3 V^[2]; C_L= 50 pF

t_PLH

propagation delay

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

1.2

1.5

2.1

1.8

2.4

3.0

2.9

3.5

4.3

ns

LEAB to Bn or LEBA to An

CPAB to Bn or CPBA to An

propagation delay

t_PHL

An to Bn or Bn to An

see Figure 5

see Figure 6

see Figure 7

see Figure 9

see Figure 10

see Figure 9

see Figure 10

1.1

1.4

1.7

2.2

1.6

2.7

2.1

1.9

2.1

2.6

3.3

2.5

3.6

3.0

2.8

3.6

4.1

4.5

3.6

4.9

4.0

ns

LEAB to Bn or LEBA to An

CPAB to Bn or CPBA to An

output enable time to HIGH-level

output enable time to LOW-level

output disable time from HIGH-level

output disable time from LOW-level

hold time HIGH

t_PZH

t_PZL

t_PHZ

t_PLZ

t_h(H)

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEAB

hold time LOW

see Figure 8

+1.0 −0.6

1.0 0.1

-

ns

t_h(L)

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEAB

set-up time HIGH

see Figure 8

+1.0 −0.3

-

ns

1.5

0.6

t_su(H)

t_su(L)

t_WH

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

set-up time LOW

see Figure 8

2.0

0.5

-

ns

+1.0 −0.6

An to CPAB or Bn to CPBA

An to LEAB or Bn to LEBA

pulse width HIGH

see Figure 8

2.0

0.7

-

ns

+1.0 −0.1

CPAB or CPBA

see Figure 7

see Figure 6

2.0

1.5

-

ns

LEAB or LEBA

t_WL

pulse width LOW

CPAB or CPBA

see Figure 7

2.0

-

ns

f_max

maximum clock frequency

150

MHz

[1] All typical values are measured at V_CC= 2.5 V and T_amb= 25 °C.

[2] All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

12 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

12. Waveforms

V

I

input

An or Bn

V

M

t

0 V

t

PLH

PHL

V

OH

output

Bn or An

V

M

V

OL

001aad308

Measurement points are given in Table 9.

V_OLand V_OHare typical voltage output drop that occur with the output load.

Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode

V

I

input LEAB

or LEBA

V

M

0 V

t

WH

t

PLH

PHL

V

OH

output

An or Bn

V

M

V

OL

001aad310

Measurement points are given in Table 9.

V_OLand V_OHare typical voltage output drop that occur with the output load.

Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable

(LEAB, LEBA) pulse width

1/f

max

V

I

input CPBA

or CPAB

V

M

0 V

t

WL

WH

t

PLH

PHL

V

OH

output

An or Bn

V

M

V

OL

001aad254

Measurement points are given in Table 9.

V_OLand V_OHare typical voltage output drop that occur with the output load.

Fig 7. Propagation delay clock (CPAB, CPBA) to output (An, Bn), clock (CPAB, CPBA)

pulse width and maximum clock frequency (CPAB, CPBA)

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

13 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

V

I

LEAB or LEBA

input

V

M

V

M

CPAB or CPBA 0 V

t

h(L)

su(H)

h(H)

su(L)

V

I

input An, Bn

V

M

0 V

001aad342

Measurement points are given in Table 9.

The shaded areas indicate when the input is permitted to change for predictable output

performance.

Fig 8. Data setup and hold times

OEBA

input

V

I

V

M

t

0 V

OEAB

t

PZH

PHZ

V

OH

V

Y

output

An or Bn

V

M

0 V

001aad344

Measurement points are given in Table 9.

V_OHis typical voltage output drop that occur with the output load.

Fig 9. 3-state output enable time to HIGH-level and output disable time from HIGH-level

V

I

OEBA

input

V

M

t

0 V

OEAB

t

PZL

PLZ

3.0 V or V

CC

output

An or Bn

V

M

V

X

V

OL

001aad346

Measurement points are given in Table 9.

V_OLis typical voltage output drop that occur with the output load.

Fig 10. 3-state output enable time to LOW-level and output disable time from LOW-level

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

14 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

Table 9:

Measurement points

Supply voltage

Input

V_M

Output

V_M

V_X

V_Y

≥ 3.0 V

≤ 2.7 V

1.5 V

V_OL+ 0.30 V

V_OL+ 0.15 V

V

_OH− 0.30 V

_OH− 0.15 V

0.5 × V_CC

V

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

(t )

f

t

(t )

TLH r

THL

t

(t )

t

(t )

THL f

TLH

r

V

I

90 %

positive

pulse

V

M

V

M

10 %

0 V

t

W

001aac221

Measurement points are given in Table 9.

a. Input pulse deﬁnition

V

EXT

V

CC

R

L

V

O

I

PULSE

GENERATOR

DUT

C

L

R

L

R

T

mna616

Test data is given in Table 10.

Deﬁnitions test circuit:

R_L= Load resistor.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= Test voltage for switching times.

b. Test circuit

Fig 11. Load circuitry for switching times

Table 10: Test data

Input

Load

C_L

V_EXT

V_I

f_i

t_W

t_r, t_f

R_L

t_PLZ, t_PZLt_PLH, t_PHLt_PHZ, t_PZH

3.0 V or V_CC≤ 10 MHz 500 ns ≤ 2.5 ns 30 pFor 500 Ω 6 V or 2 × open

GND

whichever is

less

50 pF

V_CC

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

15 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

13. Package outline

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm

SOT371-1

D

E

A

X

c

y

H

v

M

A

E

Z

29

56

Q

A

2

A

(A )

3

1

θ

pin 1 index

L

p

L

28

1

detail X

w

M

b

p

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

Q

v

w

y

Z

θ

p

1

2

3

max.

8^o

0^o

0.4

0.2

2.35

2.20

0.3

0.2

0.22 18.55

0.13 18.30

7.6

7.4

10.4

10.1

1.0

0.6

1.2

1.0

0.85

0.40

mm

2.8

0.25

0.635

1.4

0.25

0.18

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT371-1

MO-118

Fig 12. Package outline SOT371-1 (SSOP56)

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

16 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig 13. Package outline SOT364-1 (TSSOP56)

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

17 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

14. Revision history

Table 11: Revision history

Document ID

74ALVT16501_4

Modiﬁcations:

Release date Data sheet status

20050808 Product data sheet

Change notice Doc. number

Supersedes

-

74ALVT16501_3

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of Philips Semiconductors.

• Section 2 “Features”: modiﬁed ‘JEDEC Std. 17’ into ‘JESD78’.

• Table 8 “Dynamic characteristics”: changed maximum values of propagation delay, output

enable time and output disable time.

74ALVT16501_3

74ALVT16501_2

74ALVT16501_1

19980213

Product speciﬁcation

-

9397 750 03567 74ALVT16501_2

-

74ALVT16501_1

-

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

18 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

15. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

16. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Trademarks

Notice — All referenced brands, product names, service names and

17. Disclaimers

trademarks are the property of their respective owners.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

74ALVT16501_4

Product data sheet

Rev. 04 — 8 August 2005

19 of 20

74ALVT16501

Philips Semiconductors

18-bit universal bus transceiver; 3-state

20. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 7

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended operating conditions. . . . . . . . 8

Static characteristics. . . . . . . . . . . . . . . . . . . . . 9

Dynamic characteristics . . . . . . . . . . . . . . . . . 11

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Contact information . . . . . . . . . . . . . . . . . . . . 19

9

10

11

12

13

14

15

16

17

18

19

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 8 August 2005

Document number: 74ALVT16501_4

Published in The Netherlands


型号：	935219420512
厂家：	NXP
描述：	ALVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56 信息通信管理光电二极管输出元件逻辑集成电路
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