935245400518 [NXP]
IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, PLASTIC, SOT-307-2, QFP-44, Analog to Digital Converter;
| 型号： | 935245400518 |
| 厂家： | 
NXP |
| 描述： | IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, PLASTIC, SOT-307-2, QFP-44, Analog to Digital Converter 转换器 |
| 文件： | 总23页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8768
12-bit high-speed Analog-to-Digital
Converter (ADC)
1998 Aug 26
Preliminary specification
Supersedes data of 1998 Feb 25
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
FEATURES
APPLICATIONS
• 12-bit resolution
• High-speed analog-to-digital conversion for
– Video signal digitizing
• Sampling rate up to 55 MHz
• −3 dB bandwidth of 190 MHz
• 5 V power supplies
– High Definition TV (HDTV)
– Imaging (camera scanner)
– Medical imaging
• Binary or twos-complement CMOS outputs
• In-range CMOS-compatible output
• TLL-CMOS compatible static digital inputs
• 3 to 5 V CMOS-compatible digital outputs
– Telecommunication
– Base-station receiver.
GENERAL DESCRIPTION
• Differential clock input; Positive Emitter Coupled Logic
(PECL)-compatible
The TDA8768 is a bipolar 12-bit Analog-to-Digital
Converter (ADC) optimized for telecommunications and
professional imaging. It converts the analog input signal
into 12-bit binary coded digital words at a maximum
sampling rate of 55 MHz. All static digital inputs (SH, CE
and OTC) are TTL and CMOS compatible and all outputs
are CMOS compatible. A sine wave clock input signal can
also be used.
• Power dissipation 325 mW (typical)
• Low analog input capacitance (typical 2 pF), no buffer
amplifier required
• Integrated sample-and-hold amplifier
• Differential analog input
• External amplitude range control
• Voltage controlled regulator included.
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
CONDITIONS
MIN.
TYP.
5.0
MAX. UNIT
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
integral non-linearity
differential non-linearity
maximum clock frequency
TDA8768H/4
4.75
4.75
3.0
−
5.25
5.25
5.25
tbf
V
VCCD
VCCO
ICCA
5.0
3.3
33
V
V
mA
mA
mA
LSB
LSB
ICCD
−
30
tbf
ICCO
fCLK = 4 MHz; fi = 400 kHz
fCLK = 4 MHz; fi = 400 kHz
fCLK = 4 MHz; fi = 400 kHz
−
3.2
±2.0
±0.6
tbf
INL
−
±4.5
±1.0
DNL
fCLK(max)
−
40
55
−
−
−
MHz
MHz
mW
TDA8768H/5
−
−
Ptot
total power dissipation
325
tbf
ORDERING INFORMATION
TYPE
PACKAGE
SAMPLING
NUMBER
FREQUENCY (MHz)
NAME
DESCRIPTION
VERSION
TDA8768H/4
QFP44
plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm
40
55
SOT307-2
TDA8768H/5
1998 Aug 26
2
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
BLOCK DIAGRAM
V
V
V
V
V
V
CLK
35
CLK
36
OTC
18
CE
19
CCA1 CCA2
CCA3 CCA4
CCD1 CCD2
2
9
3
41
37 15
21 D11
1, 5 to 8, 12 to 14, 16
11
MSB
n.c.
CLOCK DRIVER
22 D10
23 D9
24 D8
25 D7
26 D6
27 D5
28 D4
TDA8768
V
ref
AMP
CMOS
OUTPUTS
data outputs
43
42
V
I
ANALOG-TO-DIGITAL
CONVERTER
LATCHES
29 D3
30 D2
31 D1
32 D0
V
I
sample-
and-hold
39
LSB
SH
33
20
V
CCO
OVERFLOW/
UNDERFLOW
LATCH
CMOS
OUTPUT
IR
44
10
4
40
38
17
34
MGR470
AGND1 AGND2 AGND3 AGND4
DGND1 DGND2
OGND
Fig.1 Block diagram.
1998 Aug 26
3
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
PINNING
SYMBOL PIN
DESCRIPTION
not connected
SYMBOL PIN
DESCRIPTION
n.c.
1
2
3
4
5
6
7
8
9
D9
23 data output; bit 9
24 data output; bit 8
VCCA1
VCCA3
AGND3
n.c.
analog supply voltage 1 (+5 V)
analog supply voltage 3 (+5 V)
analog ground 3
D8
D7
25 data output; bit 7
26 data output; bit 6
27 data output; bit 5
28 data output; bit 4
29 data output; bit 3
30 data output; bit 2
31 data output; bit 1
32 data output; bit 0 (LSB)
33 output supply voltage (3 to 5.25 V)
34 output ground
D6
not connected
D5
n.c.
not connected
D4
n.c.
not connected
D3
n.c.
not connected
D2
VCCA2
AGND2
Vref
analog supply voltage 2 (+5 V)
D1
10 analog ground 2
11 reference voltage input
12 not connected
D0
VCCO
OGND
CLK
n.c.
n.c.
13 not connected
35 complementary clock input; active
LOW
n.c.
14 not connected
CLK
36 clock input
VCCD2
n.c.
15 digital supply voltage 2 (+5 V)
16 not connected
VCCD1
DGND1
SH
37 digital supply voltage 1 (+5 V)
38 digital ground 1
DGND2
OTC
17 digital ground 2
39 sample-and-hold enable input
(CMOS level; active HIGH)
18 control input twos complement
output; active HIGH
AGND4
VCCA4
VI
40 analog ground 4
CE
19 chip enable input
(CMOS level; active LOW)
41 analog supply voltage 4 (+5 V)
42 positive analog input voltage
43 negative analog input voltage
44 analog ground 1
IR
20 in-range output
D11
D10
21 data output; bit 11 (MSB)
22 data output; bit 10
VI
AGND1
1998 Aug 26
4
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
V
33
n.c.
1
2
CCO
V
V
32 D0
31 D1
30 D2
29 D3
28 D4
27 D5
26 D6
25 D7
24 D8
23 D9
CCA1
CCA3
3
4
AGND3
n.c.
5
TDA8768H
n.c.
6
7
n.c.
n.c.
8
V
9
CCA2
10
11
AGND2
V
ref
MGR469
Fig.2 Pin configuration.
1998 Aug 26
5
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+7.0
UNIT
note 1
note 1
note 1
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
output supply voltage
supply voltage difference
−0.3
−0.3
+7.0
+7.0
V
V
V
CCA − VCCD
CCD − VCCO
CCA − VCCO
−1.0
−1.0
−1.0
0.3
+1.0
+4.0
+4.0
VCCA
VCCD
V
V
V
V
V
VI
input voltage at pins 42 and 43
referenced to AGND
Vi(p-p)
input voltage at pins 35 and 36 for
differential clock drive (peak-to-peak
value)
−
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
−10
−
+150
+85
150
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITION
VALUE
UNIT
thermal resistance from junction to ambient
in free air
75
K/W
1998 Aug 26
6
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
CHARACTERISTICS
V
V
CCA = V2 to V44, V9 to V10, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V;
CCO = V33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C, VI(p-p) − VI(p-p) = 2.0 V and CL = 10 pF; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
ICCA
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
4.75
5.0
5.25
V
4.75
3.0
−
5.0
3.3
33
5.25
5.25
45
V
V
mA
mA
mA
mA
ICCD
−
30
37
ICCO
fCLK = 4 MHz; fi = 400 kHz
−
3.2
11
tbf
fCLK = 40 MHz; fi = 4.43 MHz
−
tbf
Inputs
CLK AND CLK (REFERENCED TO DGND)
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input impedance
VCCD = 5 V; note 1
VCCD = 5 V; note 1
VCLK or VCLK = 3.19 V
VCLK or VCLK = 3.83 V
fCLK = 40 MHz
3.19
3.83
−10
−
−
−
−
−
−
−
−
3.52
4.12
−
V
VIH
V
IIL
µA
µA
kΩ
pF
V
IIH
10
−
Zi
2
Ci
input capacitance
fCLK = 40 MHz
−
2
∆VCLK(p-p)
differential AC input voltage
(peak-to-peak value) for
DC voltage level = 2.5 V
0.5
2.0
switching (VCLK − VCLK
)
OTC, SH AND CE (REFERENCED TO DGND); see Tables 1 and 2
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
0.8
VCCD
−
V
2.0
−20
−
V
VIL = 0.8 V
VIH = 2.0 V
µA
µA
IIH
+20
VI AND VI (REFERENCED TO AGND); VREF = VCCA − 1.825 V; see Table 1
IIL
LOW-level input current
HIGH-level input current
input resistance
−
10
10
−
−
−
−
2
µA
µA
kΩ
pF
IIH
−
Ri
fi = 4.43 MHz
fi = 4.43 MHz
100
−
Ci
input capacitance
−
VI(CM)
common mode input voltage VI = VI; output code 2047
CCA = 5 V
VCCA = 4.75 V
CCA = 5.25 V
V
tbf
tbf
tbf
3.6
tbf
tbf
tbf
V
V
V
3.35
3.85
V
1998 Aug 26
7
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage controlled regulator input Vref (referenced to AGND); note 2
Vref(FS)
Iref
full-scale fixed voltage
input current
VCCA = 5 V
−
−
−
3.175
0.5
−
V
10
µA
V
I(p-p) − VI(p-p) input voltage amplitude
(peak-to-peak value)
Vref = VCCA − 1.825 V
2.0
−
V
Outputs (referenced to OGND)
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)
VOL
VOH
Io
LOW-level output voltage
HIGH-level output voltage
output current in 3-state
IOL = 2 mA
0
−
−
−
0.5
V
IOH = −0.4 mA
V
CCO − 0.5
VCCO
+20
V
output level between 0.5 V
and VCCO
−20
µA
Switching characteristics
CLOCK FREQUENCY fCLK; see Fig.3
fCLK(min)
fCLK(max)
minimum clock frequency
SH = HIGH
−
−
2
MHz
maximum clock frequency
TDA8768H/4
40
−
−
−
−
−
−
−
−
MHz
MHz
ns
TDA8768H/5
55
tCLKH
tCLKL
clock pulse width HIGH
clock pulse width LOW
8.5
8.5
ns
Analog signal processing; 50% clock duty factor; VI − VI = 2.0 V; Vref = VCCA − 1.825 V; see Table 1
LINEARITY
INL
integral non-linearity
fCLK = 4 MHz; fi = 400 kHz
fCLK = 4 MHz; fi = 400 kHz;
−
−
±2.0
±0.6
±4.5
±1.0
LSB
LSB
DNL
differential non-linearity
no missing code
Eoffset
offset error
VCCA = VCCD = VCCO = 5 V;
tbf
−11
tbf
+5
mV
%
T
amb = 25 °C; VI = VI;
output code = 2047
EG(FS)
gain error amplitude
(full scale); spread from
device to device
VCCA = VCCD = VCCO = 5 V;
Tamb = 25 °C;
−5
−
V
I(p-p) − VI(p-p) = 2.0 V
BANDWIDTH (fCLK = 55 MHz); note 3
analog bandwidth
HARMONICS (fCLK = 40 MHz)
hfund(FS) fundamental harmonics
B
−3 dB; full scale input
tbf
190
−
MHz
dB
fi = 4.43 MHz
fi = 4.43 MHz
−
−
0
(full scale)
htot(FS)
harmonics (full scale);
all components
second harmonic
third harmonic
−
−
−
−75
−70
−66
−
−
−
dB
dB
dB
THD
total harmonic distortion
fi = 4.43 MHz; note 4
8
1998 Aug 26
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
THERMAL NOISE
Nth(rms)
thermal noise (RMS value)
grounded input;
fCLK = 40 MHz
−
0.25
tbf
LSB
SPURIOUS FREE DYNAMIC RANGE
DRsf
spurious free dynamic range fi = 4.43 MHz
tbf
tbf
tbf
69
tbf
tbf
−
−
−
dB
dB
dB
fi = 10 MHz
fi = 20 MHz
SIGNAL-TO-NOISE RATIO; note 5
S/N
signal-to-noise ratio
without harmonics;
CLK = 40 MHz; fi = 4.43 MHz
−
67
−
dB
f
EFFECTIVE NUMBER OF BITS; note 5
Nbit
effective number of bits
TDA8768H/4 (fCLK = 40 MHz)
fi = 4.43 MHz
fi = 10 MHz
fi = 15 MHz
fi = 4.43 MHz
fi = 10 MHz
fi = 15 MHz
fi = 20 MHz
−
−
−
−
−
−
−
10.3
tbf
−
−
−
−
−
−
−
bits
bits
bits
bits
bits
bits
bits
tbf
effective number of bits
TDA8768H/5 (fCLK = 55 MHz)
9.9
tbf
tbf
tbf
INTERMODULATION; note 6
TTIR
two-tone intermodulation
rejection
f
CLK = 40 MHz
tbf
tbf
66
67
−
−
dB
dB
d3
third order intermodulation
distortion
fCLK = 40 MHz
BIT ERROR RATE
BER
bit error rate
fCLK = 40 MHz;
−
10−15 tbf
times/
fi = 4.43 MHz;
sample
VI = ±16 LSB at code 2047
Timing (CL = 10 pF); see Fig.3 and note 7
td(s)
th
sampling delay time
output hold time
−
4
−
−
2
ns
ns
ns
ns
−
−
td
output delay time
VCCO = 5.25 V
10
13
15
18
V
CCO = 3.0 V
3-state output delay times; see Fig.4
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
14
16
16
14
18
20
20
18
ns
ns
ns
ns
1998 Aug 26
9
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
Notes
1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
a) PECL mode 1: (DC level varies 1 : 1 with VCCD) CLK and CLK inputs are at differential PECL levels.
b) PECL mode 2: (DC level varies 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the falling
edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF
capacitor.
c) PECL mode 3: (DC level varies 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the rising
edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF
capacitor.
d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (peak-to-peak
value) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
2. It is possible with an external reference connected to pin Vref to adjust the ADC input range. This voltage has to be
referenced to VCCA. For VCCA − 1.825 V, the differential input voltage amplitude is 2 V (peak-to-peak value).
3. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.
4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
F
THD = 20 log---------------------------------------------------------------------------------------------------------------
2
2
2
2
2
(2nd) + (3rd) + (4th) + (5th) + (6th)
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = Nbit × 6.02 + 1.76 dB.
6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB
below full-scale for each input signal).
d3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation
product.
7. Output data acquisition: the output data is available after the maximum delay of td.
1998 Aug 26
10
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
Table 1 Output coding with differential inputs (typical values to AGND); VI(p-p) − VI(p-p) = 2.0 V; Vref = VCCA − 1.825 V
TWOS COMPLEMENT
BINARY OUTPUTS
OUTPUTS
CODE
VI(p-p)
VI(p-p)
IR
D11 TO D0
D11 TO D0
Underflow
<3.1
3.1
−
>4.1
4.1
−
0
1
1
↓
1
↓
1
1
0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1
↓
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
↓
0
1
↓
−
−
2047
↓
3.6
−
3.6
−
0 1 1 1 1 1 1 1 1 1 1 1
↓
1 1 1 1 1 1 1 1 1 1 1 1
↓
4094
4095
Overflow
−
−
1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1
4.1
>4.1
3.1
<3.1
Table 2 Mode selection
OTC
CE
D0 TO D11 AND IR
0
1
X(1)
0
0
1
binary; active
twos complement; active
high impedance
Note
1. X = don’t care.
Table 3 Sample-and-hold selection
SH
SAMPLE-AND-HOLD
1
0
active
inactive; tracking mode
1998 Aug 26
11
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
t
CLKL
t
CLKH
HIGH
CLK
50 %
LOW
sample N
sample N + 1
sample N + 2
V
I
t
t
h
ds
HIGH
50 %
LOW
DATA
D0 to D11
DATA
N − 2
DATA
N − 1
DATA
N
DATA
N + 1
t
d
MGR472
Fig.3 Timing diagram.
V
CCD
CE
50 %
0 V
t
t
dHZ
dZH
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
10 %
TEST
S1
V
CCD
t
V
CCD
dLZ
3.3 kΩ
15 pF
t
V
CCD
dZL
S1
TDA8768
t
DGND
DGND
dHZ
t
dZH
CE
MBG856
fCE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
12
1998 Aug 26
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
APPLICATION INFORMATION
5 V
SH
mode
5 V
220 nF
100 nF
100 nF
V
V
1 : 1
I
I
input
CLK
(1)
CLK
100 Ω
100 Ω
5 V
100 nF
V
44 43 42 41 40 39 38 37 36 35 34
CCA
n.c.
1
2
33
32
31
30
29
28
27
26
25
24
23
R1
(2)
D0 (LSB)
D1
5 V
100
nF
3
4
D2
10
nF
4.7 µF
R2
n.c.
n.c.
n.c.
n.c.
5
D3
6
TDA8768
D4
7
D5
100
nF
8
D6
9
D7
5 V
100
nF
(3)
10
11
D8
D9
V
ref
12 13 14 15 16 17 18 19 20 21 22
n.c.
n.c.
n.c.
IR
D10
D11
(MSB)
n.c.
5 V
100
nF
chip select input
MGR471
output format select
The analog, digital and output supplies should be separated and decoupled.
(1) Single-ended clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage.
In addition, to ensure a sufficient analog input stability, the minimum current into these resistors must be approximately 1 mA.
(3) Vref must be decoupled to VCCA
.
Fig.5 Application diagram.
1998 Aug 26
13
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
R2
220 Ω
100 nF
R1
500 Ω
270 Ω
CLK
CLK
35
36
(1)
TTL
input
Z0 = 50 Ω
D
PECL
TRANSLATOR
Z0 = 50 Ω
R1
500 Ω
270 Ω
TDA8768
100 nF
R2
220 Ω
MGL474
If the clock lines are more than 1 inch long they must be matched. In fact, the 27 Ω resistor will be changed
by the series connection of R1 and R2, with R1 = Zo placed close to pins CLK and CLK.
(1) 50 Ω matched line (Zo, L).
Fig.6 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator.
100 nF
V
CCD
R1
R1
82 Ω
82 Ω
CLK
35
36
(1)
TTL
input
D
PECL
TRANSLATOR
CLK
TDA8768
R2
120 Ω
R2
120 Ω
MGL473
The value of R1 and R2 must be chosen in order to meet the following relations:
V
CCD × R2
R1 × R2
----------------------
R1 + R2
3 V =
and Z0 =
----------------------------
R1 + R2
(1) 50 Ω matched line (Zo, L).
Fig.7 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator
and Thevenin parallel terminations.
1998 Aug 26
14
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95
0.55
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT307-2
1998 Aug 26
15
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering
Reflow soldering techniques are suitable for all QFP
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in the “Data Handbook
IC26; Integrated Circuit Packages; Section: Packing
Methods”.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Aug 26
16
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Aug 26
17
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
NOTES
1998 Aug 26
18
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
NOTES
1998 Aug 26
19
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/02/pp20
Date of release: 1998 Aug 26
Document order number: 9397 750 03378
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The TDA8768 is a bipolar 12-bit Analog-to-Digital Converter (ADC) optimized for telecommunications and professional imaging. It converts
the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 55 MHz. All static digital inputs (SH, CE and
OTC) are TTL and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used.
PC/PC-peripherals
Cross reference
Models
Features
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
l 12-bit resolution
l Sampling rate up to 55 MHz
l -3 dB bandwidth of 190 MHz
l 5 V power supplies
l Binary or twos-complement CMOS outputs
l In-range CMOS-compatible output
l TLL-CMOS compatible static digital inputs
l 3 to 5 V CMOS-compatible digital outputs
l Differential clock input; Positive Emitter Coupled Logic (PECL)-compatible
l Power dissipation 325 mW (typical)
l Low analog input capacitance (typical 2 pF), no buffer amplifier required
l Integrated sample-and-hold amplifier
l Differential analog input
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TDA8768
TDA8768
l External amplitude range control
l Voltage controlled regulator included.
Applications
l High-speed analog-to-digital conversion for
- Video signal digitizing
- High Definition TV (HDTV)
- Imaging (camera scanner)
- Medical imaging
- Telecommunication
- Base-station receiver.
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr. Title
Datasheet
Download
TDA8768 12-bit high-speed Analog-to-Digital
Converter (ADC)
26-Aug-98
Preliminary
Specification
20
126
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status
buy online
Standard Marking * Tray Dry
Pack, Bakeable, Single
TDA8768AH/4/C1
TDA8768AH/5/C1
TDA8768AH/7/C1
9352 628 36551
SOT307 Development
-
-
-
Standard Marking * Tray Dry
Pack, Bakeable, Single
9352 628 37551
9352 628 38551
9352 454 00518
9352 454 00551
9352 454 00557
9352 454 10518
9352 454 10551
9352 454 10557
SOT307 Development
Standard Marking * Tray Dry
Pack, Bakeable, Single
SOT307 Development
Standard Marking * Reel Dry
Pack, SMD, 13"
TDA8768H/4/C1 TDA8768H/4B-T
TDA8768H/4B-S
SOT307 Samples available
SOT307 Samples available
SOT307 Samples available
SOT307 Samples available
SOT307 Samples available
SOT307 Samples available
Standard Marking * Tray Dry
Pack, Bakeable, Single
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
TDA8768H/4B
Standard Marking * Reel Dry
Pack, SMD, 13"
TDA8768H/5/C1 TDA8768H/5B-T
TDA8768H/5B-S
Standard Marking * Tray Dry
Pack, Bakeable, Single
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
TDA8768H/5B
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Royal Philips Electronics
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