935262696118 [NXP]
IC SPECIALTY TELECOM CIRCUIT, PDSO16, PLASTIC, SOT-109, SO-16, Telecom IC:Other;
| 型号： | 935262696118 |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY TELECOM CIRCUIT, PDSO16, PLASTIC, SOT-109, SO-16, Telecom IC:Other 光电二极管 |
| 文件： | 总31页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TZA3044; TZA3044B
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet
postamplifiers
Product specification
1999 Nov 03
Supersedes data of 1999 Mar 16
File under Integrated Circuits, IC19
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
FEATURES
APPLICATIONS
• Pin compatible with the NE/SA5224 and NE/SA5225 but
with extended power supply range and less external
component count
• Digital fibre optic receiver for SDH/SONET STM4/OC12
and Gigabit Ethernet applications
• Wideband RF gain block.
• Wideband operation from 1.0 kHz to 1.25 GHz typical
• Applicable in 622 Mbits/s SDH/SONET receivers and
1.25 Gbits/s Gigabit Ethernet receivers
GENERAL DESCRIPTION
The TZA3044 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3043 and TZA3023. It is pin compatible with
the NE/SA5224 and NE/SA5225 but with extended power
supply range, and needs less external components.
Capable of operating up to 1.25 Gbits/s, the chip has input
signal level detection with a user-programmable threshold.
The data and level detection status outputs are differential
outputs for optimum noise margin and ease of use.
The TZA3044B has the same functionality as the
TZA3044, but with TTL compatible status outputs
(pins ST and STQ), and TTL compatible JAM input.
• Single supply voltage from 3.0 to 5.5 V
• Positive Emitter Coupled Logic (PECL) compatible data
outputs
• Positive Emitter Coupled Logic (PECL) compatible
status outputs (TTL compatible status outputs for the
TZA3044B)
• Programmable input signal level detection to be
adjusted using a single external resistor
• On-chip DC offset compensation without external
capacitor.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
VERSION
TZA3044T
SO16
SOT109-1
SOT403-1
−
TZA3044TT
TZA3044U
TZA3044BT
TZA3044BTT
TZA3044BU
−
bare die in waffle pack carriers; die dimensions 1.55 × 1.55 mm
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SOT403-1
−
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
−
bare die in waffle pack carriers; die dimensions 1.55 × 1.55 mm
1999 Nov 03
2
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
BLOCK DIAGRAM
TEST
2
(2, 10, 15, 21, 26)
DC-OFFSET
TZA3044
COMPENSATION
(24) 13
(23) 12
4 (7)
5 (8)
DIN
DOUT
A1
A2
A3
DOUTQ
DINQ
(16) 8
25 kΩ
JAM
RECTIFIER
(18) 10
(17) 9
ST
16 (30)
15 (29)
A4
RSET
STQ
1 kΩ
BAND GAP
REFERENCE
V
ref
(3, 4, 6, 9) (1, 14)
(11, 12)
6
(13) (19, 20, 22, 25) (27, 28)
3
1
7
11
14
AGND
SUB
V
CF DGND
V
CCD
MGR240
CCA
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.1 Block diagram.
handbook, halfpage
handbook, halfpage
SUB
TEST
AGND
DIN
1
2
3
4
16
15
14
13
12
11
10
9
RSET
SUB
TEST
AGND
DIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RSET
V
V
ref
ref
V
V
CCD
CCD
DOUT
DOUTQ
DGND
ST
DOUT
DOUTQ
DGND
ST
TZA3044TT
TZA3044BTT
TZA3044T
TZA3044BT
5
6
7
8
DINQ
DINQ
V
V
CCA
CCA
CF
CF
STQ
STQ
JAM
JAM
MBK998
MGR241
Fig.2 Pin configuration of TZA3044T and
TZA3044BT.
Fig.3 Pin configuration of TZA3044TT and
TZA3044BTT.
1999 Nov 03
3
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
PINNING
PIN
PAD
TZA3044U
SYMBOL TZA3044T
TZA3044TT
TYPE(1)
DESCRIPTION
SUB
1
2
1, 14
S
substrate pin; must be at the same potential as pin AGND
for test purpose only; to be left open in the application
TEST
2, 10, 15,
21, 26
−
AGND
DIN
3
4
3, 4, 6, 9
7
S
I
analog ground; must be at the same potential as pin DGND
differential input; complementary to pin DINQ; DC bias level is set
internally at approximately 2.1 V
DINQ
5
8
I
differential input; complementary to pin DIN; DC bias level is set
internally at approximately 2.1 V
VCCA
CF
6
7
11, 12
13
S
A
analog supply voltage; must be at the same potential as pin VCCD
input for connection of capacitor to set time constant of level
detector input filter (optional); the capacitor should be connected
between VCCA and pin CF
JAM
8
16
I
PECL-compatible input (TTL compatible for the TZA3044B);
controls the output buffers pins DOUTand DOUTQ; when a LOW
signal is applied, the outputs will follow the input signal; when a
HIGH signal is applied, the output buffers will latch into LOW and
HIGH states respectively; when not connected, pin JAM is actively
pulled LOW
STQ
ST
9
17
18
O
O
PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is HIGH;
complementary to pin ST
10
PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is LOW;
complementary to pin STQ
DGND
DOUTQ
DOUT
11
12
13
19, 20, 22,
25
S
O
O
digital ground; must be at the same potential as pin AGND
23
PECL-compatible differential output; forced into a HIGH condition
when pin JAM is HIGH; complementary to pin DOUT
24
PECL-compatible differential output; forced into a LOW condition
when pin JAM is HIGH; complementary to pin DOUTQ
VCCD
Vref
14
15
27, 28
29
S
digital supply voltage; must be at the same potential as VCCA
O
band gap reference voltage; typical value is 1.2 V; internal series
resistor of 1 kΩ
RSET
16
30
A
input signal level detector programming; nominal DC voltage is
VCCA − 1.5 V; threshold level is set by connecting an external
resistor between VCCA and pin RSET or by forcing a current into
pin RSET; default value for this resistor is 180 kΩ which
corresponds with approximately 4 mV (p-p) differential input signal
n.c.
−
5, 31, 32
−
not connected
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
1999 Nov 03
4
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
FUNCTIONAL DESCRIPTION
If AC coupling is used to remove any DC compatibility
requirement, the coupling capacitors must be large
enough to pass the lowest input frequency of interest.
For example, 1 nF coupling capacitors react with the
internal 4.5 kΩ input bias resistors to yield a lower −3 dB
frequency of 35 kHz. This then sets a limit on the
maximum number of consecutive pulses that can be
sensed accurately at the system data rate. Capacitor
tolerance and resistor variation must be included for an
accurate calculation.
The TZA3044 accepts up to 1.25 Gbits/s data streams,
with amplitudes from 2 mV (p-p) up to 1.5 V (p-p)
single-ended. The input signal will be amplified and limited
to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
DC-offset compensation
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3044, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
A control loop connected between the inputs of buffer A3
and amplifier A1 (see Fig.1) will keep the input of buffer A3
at its toggle point in the absence of any input signal.
Because of the active offset compensation which is
integrated in the TZA3044, no external capacitor is
required. The loop time constant determines the lower
cut-off frequency of the amplifier chain, which is set at
approximately 850 Hz.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL
outputs ST and STQ (TTL for the TZA3044B). This flag
can also be used to prevent the PECL outputs DOUT and
DOUTQ from reacting to noise in the absence of a valid
input signal, by connecting pin STQ to pin JAM. This
guarantees that data will only be transmitted when the
input signal-to-noise ratio is sufficient for low bit error rate
system operation.
Input signal level detection
The TZA3044 allows for user-programmable input signal
level detection and can automatically disable the switching
of the PECL outputs if the input signal is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of a valid input signal, and insures that data
will only be transmitted when the signal-to-noise ratio of
the input signal is sufficient for low bit-error-rate system
operation. Complementary PECL (TTL for the TZA3044B)
flags (pins ST and STQ) indicate whether the input signal
is above or below the programmed threshold level.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The input signal is amplified and rectified before being
compared to a programmable threshold reference. A filter
is included to prevent noise spikes from triggering the level
detector. This filter has a nominal 1 µs time constant and
additional filtering can be achieved by using an external
capacitor between VCCA and pin CF (the internal driving
impedance nominally is 25 kΩ). The resultant signal is
then compared to a threshold current through pin RSET.
This current can be set by connecting an external resistor
between VCCA and pin RSET, or by forcing a current into
pin RSET (see Fig.6).
The inputs, pins DIN and DINQ, are DC biased at
approximately 2.1 V by an internal reference generator
(see Fig.5). The TZA3044 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (1.3 V to VCCA). Also a DC offset voltage of more
than a few millivolts should be avoided, since the internal
DC offset compensation circuit has a limited correction
range.
1999 Nov 03
5
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
The relationship between the threshold current and the
detected input voltage is approximately:
approximately 30 kHz and a maximum assert time of
30 µs.
IRSET = 0.0018 × (VDIN – VDINQ)[A]
(1)
Dissipation
In the formulas (1) and (3), the voltage on
pins DIN and DINQ is measured as peak-to-peak value.
Since the thermal resistance from junction to ambient
Rth(j-a) of the TSSOP package is higher than the thermal
resistance of the SO package (see Chapter “Thermal
characteristics”), the dissipation should be considered
when using the TZA3044TT version.
Since the voltage on pin RSET is held constant at 1.5 V
below VCCA, the current flowing into this pin will be:
1.5
IRSET
=
[A ]
(2)
-------------
The formula to calculate the worst case die temperature is:
RADJ
Tj = Tamb + Rth(j – a) × Pmax
(4)
Combining these two formulas results in a general formula
to calculate RADJ for a given input signal level detection:
where
830
(VDIN – VDINQ
Tj = junction temperature
RADJ
=
[Ω ]
(3)
-------------------------------------
)
Tamb = ambient temperature
Rth(j-a) = thermal resistance from junction to ambient
Pmax = maximum power dissipation.
Example: Detection should occur if the differential voltage
of the input signals drops below 4 mV (p-p). In this case, a
reference current of 0.0018 × 0.004 = 7.2 µA should flow
into pin RSET. This can be set using a current source or
simply by connecting a resistor of the appropriate value.
The resistor must be connected between VCCA and
pin RSET. In this example the value would be:
For the TZA3044T (SO package), the worst case die
temperature Tj = 85 + 115 × 0.3 = 119.5 °C which is below
the maximum operating temperature.
For the TZA3044TT (TSSOP package), the worst case die
temperature Tj = 85 + 150 × 0.3 = 130 °C which is higher
than the maximum operating temperature, and therefore
strongly discouraged. It is recommended to lower the
thermal resistance from junction to ambient, e.g. by means
of a dedicated board layout.
830
RADJ
=
= 207.5 kΩ
--------------
0.004
The hysteresis is fixed internally at 3 dB electrical. In the
example of above, a differential level below 4 mV (p-p) of
the input signal will drive pin ST to LOW, and an input
signal level above 5.7 mV (p-p) will drive pin ST to HIGH.
However, if the ambient temperature is limited to 75 °C or
the power supply is limited to 3.3 ±0.3 V, the junction
temperature will stay below the maximum value without
further precautions.
A function is provided to automatically disable the signal
transmission when the chip senses that the input signal is
below the programmed threshold level. This function can
be put into operation by connecting pin JAM with pin STQ.
When the input signal is below the programmed threshold
level, the data outputs are then forced to a predetermined
state (pin DOUT = LOW and pin DOUTQ = HIGH).
Output circuits
The output circuit of ST and STQ is given in Fig.7.
The output circuit of DOUT and DOUTQ is given in Fig.8.
Some PECL termination schemes are given in Fig.9.
Response time of the input signal level detection circuit is
determined by the time constant of the input capacitors,
together with the filter time constant (1 µs internal plus the
additional capacitor at pin CF). For SDH/SONET
applications couple capacitors of 1.5 nF are
recommended, leading to a high-pass frequency of
1999 Nov 03
6
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
V
handbook, halfpage
CC
V
V
OH(max)
OH(min)
(1)
(2)
V
V
OL(max)
OL(min)
GND
MGS812
(1) Output signal on pin DOUT or pin ST; complementary to output signal (2).
(2) Output signal on pin DOUTQ or pin STQ; complementary to output signal (1)
Fig.4 Logic level symbol definitions for PECL.
V
handbook, halfpage
CC
DIN
DINQ
4.5 kΩ
4.5 kΩ
2.1 V
1 mA
MGR958
Fig.5 Data input circuit DIN and DINQ.
7
1999 Nov 03
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
V
handbook, halfpage
CCA
R
ADJ
RSET
RSET
V
RSET
TZA3044
I
MGS815
VRSET = VCCA − 1.5 V
Fig.6 Level detect input circuit RSET.
V
V
CC
CC
V
V
LOW
HIGH
ST
ST
10 kΩ
MGS816
Output STQ is complementary to output ST.
Fig.7 Output circuit ST and STQ for the TZA3044 (left) and TZA3044B (right).
V
handbook, halfpage
CC
105 Ω
105 Ω
DOUT
DOUTQ
0.5 mA
9 mA
0.5 mA
MGR247
Fig.8 PECL output circuit DOUT and DOUTQ.
8
1999 Nov 03
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
V
− 2 V
CC
R1 = 50 Ω
R1 = 50 Ω
V
V
O
V
I
Z
= 50 Ω
o
V
IQ
MGR248
OQ
V
= 3.3 V
CC
R1 = 127 Ω
R1 = 127 Ω
V
O
V
I
Z
= 50 Ω
o
V
IQ
V
OQ
R2 = 82.5 Ω
R2 = 82.5 Ω
GND
MGR249
V
= 5.0 V
CC
R1 = 83.3 Ω
R1 = 83.3 Ω
V
V
O
V
I
Z
= 50 Ω
o
V
IQ
OQ
R2 = 125 Ω
R2 = 125 Ω
GND
MGR250
Fig.9 PECL output termination schemes.
9
1999 Nov 03
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCC
Vn
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
+6
UNIT
supply voltage
DC voltage
V
pins DIN, DINQ, CF, JAM and RSET
pins ST, STQ, DOUT and DOUTQ
pin Vref
−0.5
V
CC + 0.5
V
V
V
note 1
VCC − 2
VCC + 0.5
+3.2
−0.5
In
DC current
pins DIN, DINQ, CF and JAM
pins ST, STQ, DOUT and DOUTQ
pin Vref
−1
−25
−2
−2
−
+1
mA
mA
mA
mA
mW
°C
+10
+2.5
+2
pin RSET
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
ambient temperature
300
+150
150
+85
−65
−
°C
Tamb
−40
°C
Note
1. For the TZA3044B the minimum value is −0.5 V for ST and STQ outputs.
HANDLING
This device is ESD sensitive and should be handled with care. Precautions should be taken to avoid damage through
electrostatic discharge. This is particularly important during assembly and handling of the bare die. Additional safety can
be obtained by bonding the VCC and GND pads first, the remaining pads may then be bonded to their external
connections in any order.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
SO16 package
note 1
115
150
K/W
K/W
TSSOP16 package
Note
1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single-sided
57 × 57 × 1.6 mm FR4 epoxy printed-circuit board with 35 µm thick copper traces. The measurements are performed
in still air.
1999 Nov 03
10
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
CHARACTERISTICS
For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient
temperature range and supply voltage range; all voltages are measured with respect to ground; unless otherwise
specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
ICCD
ICCA
Ptot
Tj
supply voltage
3
3.3
18
5.5
31
24
V
digital supply current
analog supply current
total power dissipation
junction temperature
ambient temperature
notes 1 and 2
−
mA
mA
mW
°C
note 2
−
15
notes 1 and 2
−
110
−
300
−40
−40
+125
+85
Tamb
+25
°C
Input signal pins DIN and DINQ
Vi(se)(p-p) single-ended input signal
voltage (peak-to-peak)
note 3
note 3
0.002
0.004
−
−
1.5
3.0
V
V
Vi(dif)(p-p) differential input signal
voltage (peak-to-peak)
VI
absolute input signal voltage
1.3
2.1
VCCA
50
V
VIO(eq)
equivalent input signal offset
voltage
−
−
µV
VIO(cor)
input offset voltage correction note 4; positive
note 4; negative
−
3
−
mV
mV
kΩ
pF
−
−3
4.5
−
−
Ri
input resistance
single-ended
2.9
−
7.6
2.5
145
Ci
input capacitance
single-ended; note 5
notes 5 and 6
Vn(i)(rms)
equivalent input RMS noise
voltage
−
100
µV
Input signal level detect pin RSET
IRSET
reference current
notes 5 and 7
5
−
60
µA
V
VRSET
Vth(p-p)
reference voltage
referred to VCCA
V
CCA − 1.65
V
CCA − 1.5
VCCA − 1.4
threshold adjusting range
(single-ended, peak-to-peak) 27 − 1 sequence; note 5
Vi = 1.25 Gbits/s PRBS
2
−
12
mV
hys
RF
tF
hysteresis
electrically measured
CF = 0; note 5
2
3
6
dB
kΩ
µs
filter resistance
filter time constant
14
0.5
25
41
2.0
1.0
PECL output pins DOUT and DOUTQ
VOL
VOH
tr
LOW-level output voltage
HIGH-level output voltage
rise time
note 8
V
V
−
−
−
−
−
CC − 1.84
−
V
CC − 1.6
CC − 0.9
V
note 8
CC − 1.1
−
V
V
20% to 80%; note 5
80% to 20%; note 5
note 5
200
200
−
250
250
30
ps
tf
fall time
ps
tPWD
f−3dB(l)
f−3dB(h)
pulse width distortion
low frequency −3 dB point
high frequency −3 dB point
ps
0.85
1000
1.5
−
kHz
MHz
note 9
1999 Nov 03
11
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PECL output pins ST and STQ (TZA3044)
VOL
VOH
CL
LOW-level output voltage
HIGH-level output voltage
load capacitance
note 8
V
V
−
−
−
CC − 1.84
−
−
−
−
−
V
CC − 1.6
CC − 0.9
V
note 8
CC − 1.1
V
V
RL = ∞
20
pF
pF
pF
RL = 1 kΩ
RL = 50 Ω
100
1000
TTL output pins ST and STQ (TZA3044B)
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = 4 mA
−
−
−
0.4
V
V
IOH = −400 µA
2.4
−
PECL input pin JAM (TZA3044)
VIL
LOW-level input voltage
HIGH-level input voltage
JAM input current
−
−
V
CC − 1.49
V
VIH
V
CC − 1.165 −
−
V
II(JAM)
note 10
−20
−
+20
µA
TTL input pin JAM (TZA3044B)
VIL
LOW-level input voltage
HIGH-level input voltage
JAM input current
−
−
−
−
0.8
−
V
VIH
2.0
−20
V
II(JAM)
note 10
note 11
+20
µA
Reference voltage output pin Vref
Vref
reference voltage
1.165
1.20
1.235
V
Notes
1. PECL outputs (pins DOUT, DOUTQ, ST and STQ) are not connected.
2. Maximum currents are specified at Tj = 125 °C, VCC = 5.5 V and worst case processing.
3. 2 mV (p-p) single-ended is the minimum input signal to achieve full clipping of the output signal. Typical an input
signal of 0.8 mV (p-p) single-ended results in a Bit Error Rate (BER) of less than 10−10
.
4. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to
avoid malfunctioning of the DC offset compensation circuit.
5. Specifications guaranteed by design and characterisation. Each device is tested at full operating speed to guarantee
RF functionality.
total output RMS noise
low frequency gain
6. Input RMS noise =
------------------------------------------------------------
7. The reference current can be set by connecting a resistor between VCCA and pin RSET. The corresponding input
signal level detect range is from 2 to 12 mV (p-p) single-ended. See Section “Input signal level detection” for detailed
information.
8. RL = 50 Ω connected to a level of VCC − 2 V (see Fig.9).
9. Large signal response of TZA3044T and TZA3044TT show very little deviation, although the small signal frequency
response of the TZA3044TT is more flat and shows a larger bandwidth.
10. Internal pull-down resistor of 500 kΩ to DGND.
11. Internal series resistor of 1 kΩ.
1999 Nov 03
12
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
TYPICAL PERFORMANCE CHARACTERISTICS
MGR959
MGR960
1.40
50
handbook, halfpage
handbook, halfpage
V
o(dif)
I
CC
(mA)
(V)
1.36
40
(1)
(2)
1.32
1.28
1.24
1.20
30
20
10
−40
1.16
0
40
80
120
−40
0
40
80
120
T (°C)
T (°C)
j
j
PECL outputs not connected
(1) VCC = 5.5 V.
(2) VCC = 3.0 V.
Vo(dif) = VDOUT − VDOUTQ.
Fig.10 Total power supply current as function of
junction temperature.
Fig.11 Differential output voltage as function of
junction temperature.
MGR961
MGR962
1.4
260
handbook, halfpage
handbook, halfpage
V
o(dif)
t
(V)
(ps)
1.3
220
t
r
t
f
1.2
1.1
1
180
140
100
−3
−2
−1
−3
−2
−1
10
10
10
1
10
10
10
10
1
10
V
(V)
V
(V)
i(dif)(p-p)
i(dif)(p-p)
Vo(dif) = VDOUT − VDOUTQ
.
Fig.12 Differential output voltage as function of
differential input voltage.
Fig.13 Differential output rise time and fall time as
function of differential input voltage.
1999 Nov 03
13
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
MGR964
MGR963
50
300
handbook, halfpage
handbook, halfpage
V
i(dif)
(mV)
t
(ps)
40
(1)
(2)
t
t
r
f
200
30
20
10
(3)
(4)
100
0
5
0
−40
15
25
35
I
45
(µA)
0
40
80
120
T (°C)
j
RSET
Vi(dif) = VDIN − VDINQ
.
(1) Input high threshold for 1 0 1 0 pattern (pin ST = HIGH).
(2) Input high threshold for 27 − 1 PRBS pattern (pin ST = HIGH).
(3) Input low threshold for 1 0 1 0 pattern (pin ST = LOW).
(4) Input low threshold for 27 − 1 PRBS pattern (pin ST = LOW).
Fig.14 Differential output rise time and fall time as
function of junction temperature.
Fig.15 Status detect level as function of IRSET
.
MGR965
MGR966
40
6
handbook, halfpage
handbook, halfpage
V
(1)
(2)
i(dif)
(mV)
hys
(dB)
30
20
10
0
4
(1)
(2)
2
0
(3)
(4)
−40
0
40
80
120
5
15
25
35
I
45
(µA)
T (°C)
j
RSET
Vi(dif) = VDIN − VDINQ
.
(1) Input high threshold for 1 0 1 0 pattern (pin ST = HIGH).
(2) Input high threshold for 27 − 1 PRBS pattern (pin ST = HIGH).
(3) Input low threshold for 1 0 1 0 pattern (pin ST = LOW).
(4) Input low threshold for 27 − 1 PRBS pattern (pin ST = LOW).
(1) 1 0 1 0 pattern.
(2) 27 − 1 PRBS pattern.
Fig.16 Status detect level as function of junction
temperature.
Fig.17 Status detect hysteresis as function of
IRSET
.
1999 Nov 03
14
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
MGR968
MGR967
0.003
handbook, halfpage
4
handbook, halfpage
Ratio
(A/V)
(1)
(2)
hys
(dB)
(1)
(2)
0.002
0.001
3
2
0
5
1
−40
15
25
35
I
45
(µA)
0
40
80
120
RSET
T (°C)
j
IRSET
Ratio =
where Vi(dif) = input low threshold (pin ST = LOW).
--------------
Vi(dif)
(1) IRSET = 45 µA.
(2) IRSET = 10 µA.
(1) 27 − 1 PRBS pattern.
(2) 1 0 1 0 pattern.
Fig.18 Status detect hysteresis as function of
junction temperature.
Fig.19 Status detect ratio as function of IRSET
.
MGR970
MGR969
40
1.555
handbook, halfpage
handbook, halfpage
t
PWD
(ns)
V
RSET
(V)
30
1.545
(1)
20
10
0
(2)
1.535
1.525
−40
0
40
80
120
−3
−2
−1
10
10
10
1
10
T (°C)
j
V
(V)
i(dif)(p-p)
VRSET = VCCA − 1.5 V.
(1) VCC = 5.5 V.
(2) VCC = 3.0 V.
Fig.20 Pulse Width Distortion (tPWD) as function of
differential input voltage.
Fig.21 VRSET as function of junction temperature.
1999 Nov 03
15
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
MGR956
200 mV/div
Fig.22 Differential output waveform with 4 mV differential input voltage.
MGR957
200 mV/div
Fig.23 Differential output waveform with 2 V differential input voltage.
16
1999 Nov 03
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
APPLICATION INFORMATION
V
CC
100 nF
100 nF
180 kΩ
RSET
16
CF
V
V
CCD
V
ref
CCA
7
15
(29)
14
(27, 28)
6
(30)
(13)
(11, 12)
1.5 nF
1.5 nF
DIN
DOUT
4 (7)
(24) 13
data in
data out
TZA3044
DINQ
DOUTQ
5 (8)
(23) 12
(3, 4, 6, 9) (1, 14) (16)
(17)
9
(18) (19, 20, 22, 25)
10 11
3
1
8
AGND SUB JAM
STQ ST
DGND
level detect
status
1 kΩ
50 Ω
50 Ω
V
− 2 V
CC
MGR251
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.24 Application diagram.
1999 Nov 03
17
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d
V
CC
680 nF
(1)
(1)
(1)
22 nF
100 nF
100 nF
61 kΩ
V
RSET
CF
V
V
CCD
V
CC
ref
CCA
8
16
(30)
7
(13)
15
(29)
14
(27, 28)
6
(11, 12)
1.5 nF
DREF
IPhoto
OUTQ
OUT
DIN
DOUT
1
4 (7)
7
(24) 13
data out
TZA3043T
TZA3044
100 Ω
1.5 nF
4 pF
1 µF
DOUTQ
DINQ
5 (8)
(23) 12
6
5
3
2
noise filter:
1-pole, 800 MHz
(3, 4, 6, 9) (1, 14) (16)
(17)
9
(18) (19, 20, 22, 25)
10 11
3
1
8
4
AGND SUB JAM
STQ ST
DGND
GND GND GND
level detect
status
1 kΩ
50 Ω
50 Ω
V
− 2 V
CC
MGR252
(1) Ferrite bead e.g. Murata BLM10A700S.
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.25 Gigabit Ethernet receiver using the TZA3043T and TZA3044.
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a
V
CC
680 nF
(1)
(1)
(1)
100 nF
100 nF
61 kΩ
V
RSET
CF
V
V
CCD
V
CC
ref
CCA
8
16
(30)
7
(13)
15
(29)
14
(27, 28)
6
(11, 12)
1.5 nF
DREF
IPhoto
OUTQ
OUT
DIN
DOUT
1
4 (7)
7
(24) 13
100 Ω
data out
TZA3023T
8 pF
TZA3044
1.5 nF
DINQ
DOUTQ
6
5
5 (8)
(23) 12
3
2
noise filter:
1-pole, 400 MHz
(3, 4, 6, 9) (1, 14) (16)
(17)
9
(18) (19, 20, 22, 25)
10 11
3
1
8
4
AGND SUB JAM
STQ ST
DGND
GND GND GND
16.4 nH
level detect
status
7.5
pF
1.1
pF
1 kΩ
50 Ω
50 Ω
16.4 nH
V
− 2 V
CC
MBK999
optional noise filter:
3-pole, 470 MHz Bessel
(1) Ferrite bead e.g. Murata BLM10A700S.
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.26 STM4/OC12 receiver using the TZA3023T and TZA3044.
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
BONDING PADS
COORDINATES(1)
SYMBOL
PAD
X
Y
SUB
1
−235.7
−392.8
−532.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−532.8
−392.8
−235.7
−78.6
+647.8
+647.8
+647.8
+507.1
+350.0
+210.0
+70.0
TEST
AGND
AGND
n.c.
2
3
4
5
AGND
DIN
6
7
DINQ
AGND
TEST
VCCA
VCCA
CF
8
−70.0
9
−210.0
−350.0
−507.1
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−507.1
−350.0
−210.0
−70.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SUB
TEST
JAM
+61.4
STQ
+218.5
+375.6
+532.7
+647.8
+647.8
+647.8
+647.8
+647.8
+647.8
+647.8
+647.8
+532.7
+392.7
+235.6
+78.5
ST
DGND
DGND
TEST
DGND
DOUTQ
DOUT
DGND
TEST
VCCD
VCCD
Vref
+70.0
+210.0
+350.0
+507.1
+647.8
+647.8
+647.8
+647.8
+647.8
RSET
n.c.
n.c.
−78.6
Note
1. The x and y coordinates represent the position of the
centre of the pad with respect to the centre of the die
(see Fig.27).
1999 Nov 03
20
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
3
2
1
32
31
30
29 28
V
27
AGND
4
CCD
n.c.
AGND
DIN
26
25
24
23
22
21
5
6
TEST
DGND
DOUT
DOUTQ
DGND
TEST
7
(1)
x
1.55
mm
0
8
DINQ
AGND
TEST
0
y
9
TZA3044U
TZA3044BU
10
V
20
11
DGND
CCA
12 13
14
15 16
17
18
19
(1)
1.55 mm
MGR242
(1) Typical value.
Fig.27 Bonding pad locations of TZA3044U and TZA3044BU.
Physical characteristics of bare die
PARAMETER
VALUE
Glass passivation
Bonding pad dimension
Metallization
Thickness
2.1 µm PSG (PhosphoSilicate Glass) on top of 0.65 µm oxynitride
minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm)
1.22 µm W/AlCu/TiW
380 µm nominal
Size
1.55 × 1.55 mm (2.4 mm2)
Backing
silicon; electrically connected to GND potential through substrate contacts
Attache temperature
Attache time
<440 °C; recommended die attache is glue
<15 s
1999 Nov 03
21
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1999 Nov 03
22
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT403-1
MO-153
1999 Nov 03
23
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Nov 03
24
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Nov 03
25
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1999 Nov 03
26
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044; TZA3044B
NOTES
1999 Nov 03
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465012/100/03/pp28
Date of release: 1999 Nov 03
Document order number: 9397 750 06335
Go to Philips Semiconductors' home page
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TZA3044; TZA3044B; SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers
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Systems
Communications
The TZA3044 is a high gain limiting amplifier that is designed to process signals from fibre optic preamplifiers like the TZA3043 and
TZA3023. It is pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range, and needs less external
components.
Capable of operating up to 1.25 Gbits/s, the chip has input signal level detection with a user-programmable threshold. The data and level
detection status outputs are differential outputs for optimum noise margin and ease of use.
The TZA3044B has the same functionality as the TZA3044, but with TTL compatible status outputs (pins ST and STQ), and TTL
compatible JAM input.
PC/PC-peripherals
Cross reference
Models
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
Features
l Pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range and less external component count
l Wideband operation from 1.0 kHz to 1.25 GHz typical
l Applicable in 622 Mbits/s SDH/SONET receivers and 1.25 Gbits/s Gigabit Ethernet receivers
l Single supply voltage from 3.0 to 5.5 V
l Positive Emitter Coupled Logic (PECL) compatible data outputs
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l Positive Emitter Coupled Logic (PECL) compatible status outputs (TTL compatible status outputs for the TZA3044B)
l Programmable input signal level detection to be adjusted using a single external resistor
l On-chip DC offset compensation without external capacitor.
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TZA3044; TZA3044B
TZA3044; TZA3044B
Applications
l Digital fibre optic receiver for SDH/SONET STM4/OC12 and Gigabit Ethernet applications
l Wideband RF gain block.
Datasheet
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(kB)
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release date Datasheet status
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TZA3044; TZA3044B SDH/SONET STM4/OC12 and 1.25
Gbits/s Gigabit Ethernet
03-Nov-99
Product
Specification
28
151
postamplifiers
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
TZA3044BT/C2
9352 668 12112 Standard Marking * Tube
SOT109 Full production
SOT109 Full production
SOT403 Full production
SOT403 Full production
-
-
-
-
Standard Marking * Reel Pack,
9352 668 12118
SMD, 13"
TZA3044BTT/C2
9352 668 13112 Standard Marking * Tube
Standard Marking * Reel Pack,
9352 668 13118
SMD, 13"
No Marking * Die In Waffle
TZA3044BU/C2
9352 668 10026
Carriers
NONE
NONE
Full production
Full production
-
-
No Marking * Chips on Wafer, Un-
9352 668 09025
TZA3044BU/T/C2
TZA3044T/C2
Sawn, Electrical Tested
TZA3044TD
9352 626 96112 Standard Marking * Tube
SOT96 Full production
SOT96 Full production
SOT403 Full production
SOT403 Full production
Standard Marking * Reel Pack,
9352 626 96118
SMD, 13"
-
-
-
TZA3044TT/C2
9352 635 30112 Standard Marking * Tube
Standard Marking * Reel Pack,
9352 635 30118
SMD, 13"
No Marking * Die In Waffle
TZA3044U/C2
9352 626 98026
Carriers
NONE
NONE
Full production
Full production
-
-
No Marking * Chips on Wafer, Un-
9352 633 81025
TZA3044U/T/C2
Sawn, Electrical Tested
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guides and products from the same functional category.
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Royal Philips Electronics
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