935270793151 [NXP]
LVC/LCX/Z SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PBGA56, 4.50 X 7 MM, 0.65 MM PITCH, PLASTIC, MO-225, SOT-702-1, VFBGA-56;
| 型号： | 935270793151 |
| 厂家： | 
NXP |
| 描述： | LVC/LCX/Z SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PBGA56, 4.50 X 7 MM, 0.65 MM PITCH, PLASTIC, MO-225, SOT-702-1, VFBGA-56 输出元件 逻辑集成电路 |
| 文件： | 总25页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction
pin; 5 V tolerant (3-state)
Product specification
2003 Jan 30
Supersedes data of 2002 Oct 30
Philips Semiconductors
Product specification
74LVC16245A;
74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
FEATURES
DESCRIPTION
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• MULTIBYTETM flow-through standard pin-out
architecture
The 74LVC(H)16245A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 Volt. These features allow the use of
these devices as a mixed 3.3 and 5 V environment.
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
The 74LVC(H)16245A is a 16-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. The device features two output
enable (nOE) inputs for easy cascading and two
send/receive (nDIR) inputs for direction control. nOE
controls the outputs so that the buses are effectively
isolated. This device can be used as two 8-bit transceivers
or one 16-bit transceiver.
• Direct interface with TTL levels
• High-impedance when VCC = 0 V
• All data inputs have bushold (74LVCH16245A only)
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
The 74LVCH16245A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
3.0
UNIT
t
PHL/tPLH
propagation delay nAn to nBn; nBn to nAn CL = 50 pF; VCC = 3.3 V
input capacitance
ns
pF
pF
pF
CI
5.0
10
30
CI/O
CPD
input/output capacitance
power dissipation capacitance per gate
VI = GND to VCC; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2003 Jan 30
2
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC16245ADL
74LVCH16245ADL
74LVC16245ADGG
74LVCH16245ADGG
74LVC16245AEV
74LVCH16245AEV
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
48
48
48
48
56
56
SSOP48
SSOP48
plastic
plastic
plastic
plastic
plastic
plastic
SOT370-1
SOT370-1
SOT362-1
SOT362-1
SOT702-1
SOT702-1
TSSOP48
TSSOP48
VFBGA56
VFBGA56
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nOE
nDIR
nAn
nBn
L
L
L
H
X
A = B
inputs
Z
inputs
B = A
Z
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
2003 Jan 30
3
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
PINNING
SYMBOL
1DIR
PINS
BALLS
DESCRIPTION
direction control input
1
2
3
A1
B2
B1
1B0
data inputs/output
data inputs/output
ground (0 V)
1B1
GND
4, 10, 15, 21, 28, B3, B4, D3, D4,
34, 39, 45
G3, G4, J3, J4
1B2
1B3
VCC1
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2DIR
2OE
2A7
2A6
2A5
2A4
VCC2
2A3
2A2
2A1
2A0
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0
1OE
5
C2
data inputs/output
data inputs/output
supply voltage
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data output
6
C1
7, 18
8
C3, H3
D2
9
D1
11
12
13
14
16
17
19
20
22
23
24
25
26
27
29
30
31, 42
32
33
35
36
37
38
40
41
43
44
46
47
48
E2
E1
F1
F2
data output
G1
data output
G2
data output
H1
data output
H2
data output
J1
data output
J2
data output
K1
direction control input
K6
output enable input (active LOW)
data inputs/output
data inputs/output
data inputs/output
data inputs/output
supply voltage
J5
J6
H5
H6
H4, C4
G5
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
data inputs/output
output enable input (active LOW)
G6
F5
F6
E6
E5
D6
D5
C6
C5
B6
B5
A6
2003 Jan 30
4
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
handbook, halfpage
1DIR
1OE
1
2
3
4
5
6
7
8
9
48
47
46
1B
0
1A
0
1B
1
1A
1
GND
45 GND
A
B
C
D
E
F
1DIR
1OE
1B
2
1A
1A
V
44
43
42
41
40
2
3
1B
3
1B
1
1B
1B
1B
1B
2B
2B
2B
2B
GND GND
1A
1A
1A
1A
2A
2A
2A
2A
1A
1A
1A
1A
2A
2A
2A
2A
0
2
4
6
1
3
5
7
0
2
4
6
1
3
5
7
1
3
5
7
0
2
4
6
V
CC1
CC2
1B
3
V
V
CC1 CC2
1B
4
1A
4
5
1B
5
1A
1B
5
GND GND
GND 10
39 GND
1B
7
1B
1B
2B
2B
1A
1A
2A
2A
11
12
13
14
38
37
36
35
6
7
0
1
6
7
0
1
2B
0
16245
G
H
J
2B
2
GND GND
GND 15
34 GND
2B
4
V
V
CC1 CC2
2B
2B
2A
2A
V
16
17
18
19
20
33
32
31
30
29
2
3
2
3
2B
6
GND GND
V
CC1
CC2
K
2DIR
1
2OE
2B
4
2A
4
5
2
3
4
5
6
2B
5
2A
MNA707
GND 21
28 GND
2B
2B
2A
2A
22
23
27
26
25
6
7
6
7
2DIR 24
2OE
MNA710
Fig.1 Pin configuration SSOP48 and TSSOP48.
Fig.2 Pin configuration VFBGA56.
2003 Jan 30
5
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
1
24
1DIR
2DIR
48
2
25
1OE
2OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1A
0
2A
0
13
1B
0
2B
0
1A
1
2A
1
3
14
1B
1
2B
1
1A
2
2A
2
5
16
1B
2
2B
2
1A
3
2A
3
6
17
1B
3
2B
3
1A
4
2A
4
8
19
1B
4
2B
4
1A
5
2A
5
9
20
1B
5
2B
5
1A
6
2A
6
11
12
22
1B
6
2B
6
1A
7
2A
7
23
1B
7
2B
7
MNA708
Fig.3 Logic symbol.
2003 Jan 30
6
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
48
1
handbook, halfpage
1OE
G3
3EN1 BA
[
]
1DIR
[
]
3EN2 AB
25
24
G6
2OE
2DIR
[
]
]
6EN4 BA
[
6EN5 AB
47
2
1
1A
0
1B
0
2
3
5
46
44
43
41
40
1B
1B
1B
1B
1B
1B
1B
2B
V
CC
1A
1
handbook, halfpage
1
2
3
4
5
6
7
0
1A
2
6
1A
3
1A
4
1A
5
8
9
data input
to internal circuit
11
12
13
38
37
36
1A
6
1A
7
2A
0
MNA705
4
5
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2A
1
2B
1
2A
2
2B
2B
2B
2B
2B
2B
2
3
4
5
6
7
2A
3
2A
4
2A
5
2A
6
2A
7
MNA709
Fig.4 Logic symbol (IEEE/IEC).
Fig.5 Bushold circuit.
2003 Jan 30
7
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
UNIT
VCC
for maximum speed performance
for low voltage applications
2.7
1.2
0
3.6
3.6
5.5
V
V
V
V
V
VI
input voltage
VO
output voltage
output HIGH or LOW state
output 3-state
0
VCC
5.5
0
Tamb
tr, tf
operating ambient
temperature
in free air
−40
+85
°C
input rise and fall times
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
0
0
20
10
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
±50
mA
V
output HIGH or LOW state; note 1 −0.5
VCC + 0.5
+6.5
output 3-state; note 1
−0.5
−
V
IO
output source or sink current VO = 0 to VCC
VCC or GND current
±50
mA
mA
°C
ICC, IGND
−
±100
+150
Tstg
Ptot
storage temperature
−65
power dissipation
SSOP and TSSOP package temperature range from
−
−
500
mW
mW
−40 to +85 °C; note 2
VFBGA package
temperature range from
1000
−40 to +85 °C; note 3
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 60 °C the value of PD derates linearly with 5.5 mW/K.
3. Above 70 °C the value of PD derates linearly with 1.8 mW/K.
2003 Jan 30
8
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP. (1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH
VIL
HIGH-level input voltage
1.2
VCC
−
−
−
V
2.7 to 3.6
1.2
2.0
−
−
−
−
V
V
V
LOW-level input voltage
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −12 mA
IO = −100 µA
IO = −18 mA
IO = −24 mA
2.7
3.0
3.0
3.0
V
V
V
V
CC − 0.5
−
−
−
−
−
V
V
V
V
CC − 0.2
CC − 0.6
CC − 0.8
VCC
−
−
VOL
LOW-level output voltage VI = VIH or VIL
IO = 12 mA
IO = 100 µA
IO = 24 mA
2.7
3.0
3.0
3.6
−
−
−
−
−
0.40
0.20
0.55
±5
V
−
V
−
V
ILI
input leakage current
VI = 5.5 V or GND;
note 2
±0.1
µA
IOZ
3-state output OFF-state VI = VIH or VIL;
current VO = 5.5 V or GND
3.6
−
0.1
±5
µA
Ioff
power off leakage supply VI or VO = 5.5 V
0.0
3.6
−
−
0.1
0.1
±10
µA
µA
ICC
quiescent supply current VI = VCC or GND;
IO = 0
20
∆ICC
IBHL
additional quiescent
supply current per pin
VI =VCC − 0.6 V;
IO = 0
2.7 to 3.6
3.0
−
5
−
−
−
−
500
−
µA
µA
µA
µA
µA
bushold LOW sustaining VI = 0.8 V;
current
75
notes 3, 4 and 5
IBHH
bushold HIGH sustaining VI = 2.0 V;
current
3.0
−75
500
−500
−
notes 3, 4 and 5
IBHLO
IBHHO
bushold LOW overdrive
current
notes 3, 4 and 6
3.6
−
bushold HIGH overdrive notes 3, 4 and 6
current
3.6
−
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bushold parts (74LVCH16245A) only.
4. For data inputs only, control inputs do not have a bushold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite input state.
2003 Jan 30
9
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay nAn to nBn;
nBn to nAn
see Figs 6 and 8
1.2
2.7
−
13.0
−
ns
1.5
−
5.5
4.5
−
ns
ns
ns
ns
ns
ns
ns
ns
3.0 to 3.6 1.5
3.0(1)
15.0
−
4.0(1)
11.0
−
tPZH/tPZL
3-state output enable time nOE see Figs 7 and 8
to nAn; nOE to nBn
1.2
2.7
−
1.5
7.1
6.1
−
3.0 to 3.6 1.5
tPHZ/tPLZ
3-state output disable time nOE see Figs 7 and 8
to nAn; nOE to nBn
1.2
2.7
−
1.5
6.6
5.6
3.0 to 3.6 1.5
4.0(1)
Note
1. Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
AC WAVEFORMS
V
handbook, halfpage
I
nA , nB
n
n
V
M
input
GND
t
t
PHL
PLH
V
OH
nB , nA
n
output
n
V
M
MNA477
V
OL
INPUT
VCC
VM
0.5 × VCC VCC
VI
tr = tf
1.2 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 The input (nAn, nBn) to output (nBn, nAn) propagation delays.
2003 Jan 30
10
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA362
INPUT
VCC
VM
0.5 × VCC VCC
VI
tr = tf
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.1 V at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 V at VCC < 2.7 V.
1.2 V
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.7 V
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 3-state enable and disable times.
2003 Jan 30
11
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
VCC
CL
RL
1.2 V
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
open
open
open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
2.7 V
2.7 V
2.7 V
3.0 to 3.6 V
Definitions for test circuits:
L = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
R
Fig.8 Load circuitry for switching times.
2003 Jan 30
12
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT370-1
MO-118
2003 Jan 30
13
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.25
0.5
1
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-10
99-12-27
SOT362-1
MO-153
2003 Jan 30
14
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
b
e
v
M
C
C
A B
w
M
y
y
1/2
e
C
1
K
J
H
G
F
e
e
2
E
D
C
B
A
1/2
e
X
ball A1
index area
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
A
A
A
b
e
y
UNIT
D
E
e
e
v
w
y
1
1
2
0
2.5
5 mm
1
2
max.
0.3
0.2
0.7
0.6
0.45
0.35
4.6
4.4
7.1
6.9
scale
mm
1
3.25 5.85
0.08
0.1
0.65
0.15 0.08
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
01-06-25
02-08-08
SOT702-1
MO-225
2003 Jan 30
15
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Jan 30
16
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Jan 30
17
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jan 30
18
Philips Semiconductors
Product specification
16-bit bus transceiver with direction pin; 5 V tolerant
(3-state)
74LVC16245A;
74LVCH16245A
NOTES
2003 Jan 30
19
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/06/pp20
Date of release: 2003 Jan 30
Document order number: 9397 750 10749
mit Q
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The 74LVC(H)16245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5
Volt. These features allow the use of these devices as a mixed 3.3 and 5 V environment.
End of Life
information
Distributors Go
Here!
•
•
The 74LVC(H)16245A is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive
directions. The device features two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for
direction control. nOE controls the outputs so that the buses are effectively isolated. This device can be used as two 8-bit
transceivers or one 16-bit transceiver.
Models
•
•
SoC solutions
The 74LVCH16245A bushold data inputs eliminates the need for external pull-up resistors to hold unused inputs.
Features
●
●
●
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
●
●
●
●
MULTIBYTE TM flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
High-impedance when VCC =0 V
●
●
●
All data inputs have bushold (74LVCH16245A only)
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Applications
AN240: Interfacing 3 Volt and 5 Volt Applications
Datasheet
Type number
Title
Publication
release date
Datasheet status
Page
count
File
size
(kB)
Datasheet
74LVC16245A;
74LVCH16245A
16-bit bus
1/30/2003
Product
specification
20
109
Download
transceiver with
direction pin; 5 V
tolerant (3-State)
Parametrics
Type number
Package
Description Propagation Voltage No. Power
Logic
Output
Delay(ns)
of
Dissipation
Switching Drive
Pins Considerations Levels
Capability
3.3V 16-Bit
Transceiver
with
Direction
Pin; Non-
Inverting (3-
State)
Low Power or
48 Battery
Applications
SOT362-1
(TSSOP48)
74LVC16245ADGG
4~6
Low
Low
TTL
TTL
Medium
3.3V 16-Bit
Transceiver
with
Direction
Pin; Non-
Inverting (3-
State)
Low Power or
48 Battery
SOT370-1
(SSOP48)
74LVC16245ADL
4~6
4~6
Medium
Medium
Applications
3.3V 16-Bit
Transceiver
with
Direction
Pin; Non-
Inverting
with Bus
Hold (3-
State)
Low Power or
48 Battery
SOT362-1
(TSSOP48)
74LVCH16245ADGG
Low
TTL
Applications
3.3V 16-Bit
Transceiver
with
Direction
Pin; Non-
Inverting
with Bus
Hold (3-
State)
Low Power or
48 Battery
Applications
SOT370-1
(SSOP48)
74LVCH16245ADL
4~6
Low
TTL
Medium
Products, packages, availability and ordering
Type number
North American
type number
Ordering code Marking/Packing Package Device
Buy online
IC packing info
(12NC)
status
SOT362-1
Standard Marking
* Tube
Full production
74LVC16245ADGG 74LVC16245ADG 9352 350 90112
(TSSOP48)
Standard Marking
SMD, 13"
SOT362-1
74LVC16245ADG-
T
Full production
Full production
Full production
9352 350 90118 * Reel Pack,
(TSSOP48)
SOT370-1
(SSOP48)
Standard Marking
* Tube
74LVC16245ADL
74LVC16245AEV
74LVC16245ADL
9352 349 00112
Standard Marking
9352 349 00118 * Reel Pack,
SMD, 13"
SOT370-1
(SSOP48)
74LVC16245ADL-
T
Standard Marking
9352 707 93118 * Reel Pack,
SMD, 13"
SOT702-1
Full production
Full production
-
-
(VFBGA56)
Standard Marking
9352 707 93151 * Tray Pack,
Bakeable, Single
SOT702-1
(VFBGA56)
Standard Marking
* Tray Pack,
Bakeable,
SOT702-1
Full production
Full production
9352 707 93157
-
(VFBGA56)
Multiple
SOT362-1
Standard Marking
* Tube
74LVCH16245ADGG 74LVCH16245ADG 9352 384 70112
74LVCH16245ADG-
(TSSOP48)
Standard Marking
SMD, 13"
SOT362-1
Full production
Full production
Full production
9352 384 70118 * Reel Pack,
(TSSOP48)
T
SOT370-1
(SSOP48)
Standard Marking
* Tube
74LVCH16245ADL 74LVCH16245ADL 9352 384 60112
74LVCH16245ADL-
Standard Marking
9352 384 60118 * Reel Pack,
SOT370-1
(SSOP48)
T
SMD, 13"
Standard Marking
SOT702-1
Full production
Full production
74LVCH16245AEV
9352 719 44118 * Reel Pack,
-
-
(VFBGA56)
SMD, 13"
Standard Marking
* Tray Pack,
Bakeable,
SOT702-1
9352 719 44157
(VFBGA56)
Multiple
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74LVC16245A; 74LVCH16245A links to the similar products page containing an overview of products that are similar in
function or related to the type number(s) as listed on this page. The similar products page includes products from the same
catalog tree(s), relevant selection guides and products from the same functional category.
Support & tools
I²C Bus Solutions, Typical I²C Bus Arrangement
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