935271266157_技术文档

INTEGRATED CIRCUITS

SSTV16859

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

Product data

2002 Feb 19

2000 Dec 01

File under Integrated Circuits — ICL03

Philips

Semiconductors

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules.

Different from traditional SDRAM, DDR SDRAM transfers data on

both clock edges (rising and falling), thus doubling the peak bus

bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of

266 MHz.

FEATURES

• Stub-series terminated logic for 2.5 V V (SSTL_2)

DD

• Optimized for stacked DDR (Double Data Rate) SDRAM

applications

The device data inputs consist of different receivers. One differential

input is tied to the input pin while the other is tied to a reference

input pad, which is shared by all inputs.

• Supports SSTL_2 signal inputs as per JESD 8–9

• Flow-through architecture optimizes PCB layout

The clock input is fully differential (CK and CK) to be compatible with

DRAM devices that are installed on the DIMM. Data are registered

at the crossing of CK going high, and CK going low. However, since

the control inputs to the SDRAM change at only half the data rate,

the device must only change state on the positive transition of the

CK signal. In order to be able to provide defined outputs from the

device even before a stable clock has been supplied, the device has

an asynchronous input pin (RESET), which when held to the LOW

state, resets all registers and all outputs to the LOW state.

• ESD classification testing is done to JEDEC Standard JESD22.

Protection exceeds 2000 V to HBM per method A114.

• Latch-up testing is done to JEDEC Standard JESD78, which

exceeds 100 mA.

• Supports efficient low power standby operation

• Full DDR 200/266 solution for stacked DIMMs at 2.5 V when used

with PCKV857

The device supports low-power standby operation. When RESET is

low, the differential input receivers are disabled, and undriven

• See SSTV16857 for JEDEC compliant register support in

unstacked DIMM applications

(floating) data, clock, and reference voltage (V ) inputs are

REF

allowed. In addition, when RESET is low, all registers are reset, and

all outputs are forced low. The LVCMOS RESET input must always

be held at a valid logic high or low level.

• See SSTV16856 for driver/buffer version with mode select.

To ensure defined outputs from the register before a stable clock

has been supplied, RESET must be held in the low state during

power-up.

DESCRIPTION

The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with

differential clock inputs, designed to operate between 2.3 V and

2.7 V. All inputs are compatible with the JEDEC standard for

In the DDR DIMM application, RESET is specified to be completely

asynchronous with respect to CK and CK. Therefore, no timing

relationship can be guaranteed between the two. When entering

RESET, the register will be cleared and the outputs will be driven

low. As long as the data inputs are low, and the clock is stable

during the time from the low-to-high transition of RESET until the

input receivers are fully enabled, the outputs will remain low.

SSTL_2 with V

normally at 0.5*V , except the LVCMOS reset

REF

DD

(RESET) input. All outputs are SSTL_2, Class II compatible which

can be used for standard stub-series applications or capacitive

loads. Master reset (RESET) asynchronously resets all registers to

zero.

The SSTV16859 is intended to be incorporated into standard DIMM

(Dual In-Line Memory Module) designs defined by JEDEC, such as

Available in 64-pin plastic thin shrink small outline package.

QUICK REFERENCE DATA

GND = 0 V; T

= 25°C; t = t v2.5 ns

amb

r

f

SYMBOL

/t

PARAMETER

CONDITIONS

TYPICAL

2.4

UNIT

ns

t

Propagation delay; CLK to Qn

Input capacitance

C = 30 pF; V = 2.5 V

PHL PLH

L

DD

C

V

CC

= 2.5 V

2.7

pF

I

NOTE:

1. C is used to determine the dynamic power dissipation (P in µW) P = C × V

2

× f + Σ (C × V

× f ) where:

o

PD

D

PD

CC

i

L

CC

f = input frequency in MHz; C = output load capacity in pF; f = output frequency in MHz; V = supply voltage in V;

i

L

o

CC

2

Σ (C × V

× f ) = sum of the outputs.

L

CC

o

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

0 to +70 °C

ORDER CODE

SSTV16859DGG

SSTV16859EC

SSTV16859BS

DWG NUMBER

SOT646AA1

SOT536-1

64-Pin Plastic TSSOP

96-Ball Plastic LFBGA

56-Terminal Plastic HVQFN

0 to +70 °C

SOT684-1

2

2002 Feb 19

853–2233 27756

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

PIN CONFIGURATION

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1, 2, 3, 4, 5, 8,

9, 10, 11, 12,

13, 14, 16

Q13A–Q1A Data output

Q13A

V

DD

1

2

64

63

Q12A

Q11A

Q10A

Q9A

GND

17, 19, 20, 21,

22, 23, 24, 25,

28, 29, 30, 31,

32

3

62 D13

Q13B–Q1B Data output

4

61

60

59

58

57

56

55

54

53

52

D12

5

V

DD

6, 18, 27, 33,

37, 38, 46, 47,

59, 60, 64

6

V

DD

Power supply voltage

V

DD

7

GND

Q8A

Q7A

Q6A

Q5A

GND

D11

7, 15, 26, 34,

39, 43, 50, 54,

58, 63

8

GND

Ground

9

D10

D9

10

11

35, 36, 40, 41,

42, 44, 52, 53,

55, 56, 57, 61,

62

Data input: clocked in on the

crossing of the rising edge of CK

and the falling edge of CK

GND

D8

D1–D13

Q4A 12

13

D7

Q3A

45

V

REF

Input reference voltage

14

15

16

17

18

51 RESET

50

Q2A

GND

Q1A

Positive and negative master

clock input

48, 49

CK, CK

GND

49 CK

Asynchronous reset input:

resets registers and disables

data and clock differential input

receivers

48

CK

Q13B

51

RESET

V

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

V

DD

Q12B 19

20

V

Q11B

REF

21

22

23

24

Q10B

Q9B

Q8B

Q7B

D6

GND

D5

D4

Q6B 25

GND 26

D3

GND

V

27

28

29

30

31

32

DD

V

DD

Q5B

Q4B

D2

D1

Q3B

Q2B

Q1B

GND

V

DD

SW00749

3

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

56-TERMINAL CONFIGURATION

TERMINAL DESCRIPTION

TERMINAL

SYMBOL

NUMBER

NAME AND FUNCTION

1, 2, 3, 4, 5, 6,

7, 50, 51, 52,

53, 54, 56

Q13A–Q1A Data output

42

41

40

39

1

2

3

4

5

D10

D9

Q7A

Q6A

Q5A

10, 11, 12, 13,

14, 15, 16, 18,

19, 20, 21, 22

D8

D7

Q13B–Q1B Data output

Q4A

Q3A

38 RESET

9, 17, 23, 27,

34, 44, 49, 55

V

DDQ

Power supply voltage

37

6

GND

Q2A

Q1A

36

7

CLK

26, 33, 45

37, 48

V

Power supply voltage

Ground

DDI

CLK

35

8

Q13B

GND

34

33

32

31

30

29

V

9

V

DDQ

DDI

DDQ

24, 25, 28, 29,

30, 31, 39, 40,

41, 42, 43, 46,

47

V

10

11

12

13

Q12B

Data input: clocked in on the

crossing of the rising edge of CK

and the falling edge of CK

Q11B

Q10B

Q9B

V

REF

D1–D13

D6

D5

D4

32

V

REF

Input reference voltage

14

Q8B

Positive and negative master

clock input

35, 36

CK, CK

Asynchronous reset input:

resets registers and disables

data and clock differential input

receivers

SW01040

51

RESET

4

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

BALL CONFIGURATION

1

2

3

4

5

6

A

B

—

Q12A

Q13A

GND

—

C

D

Q10A

Q8A

Q11A

Q9A

—

V

D13

D12

DDQ

E

F

Q6A

Q4A

Q7A

Q5A

V

D11

D9

D10

D8

DDQ

G

Q2A

Q3A

GND

D7

RESET

H

J

Q1A

Q13B

Q11B

GND

—

CK

Q12B

V

REF

K

L

Q10B

Q8B

Q9B

Q7B

V

—

DDQ

D5

D6

M

N

Q6B

Q4B

Q5B

Q3B

V

D3

D4

DDQ

GND

D1

—

D2

—

P

R

Q2B

—

Q1B

—

GND

—

GND

—

T

—

SW00944

LOGIC DIAGRAM

H

L

↑

#

L

H

X

L

H

51

RESET

L or H

Q

0

16

32

X or

floating

X or

floating

X or

floating

L

1D

C1

Q1A

48

CK

49

H = High voltage level

L = Low voltage level

↓ = High-to-Low transition

↑ = Low-to-High transition

X = Don’t care

CK

Q1B

R

35

D1

45

V

REF

to 12 other channels

SW00750

FUNCTION TABLE (each flip flop)

INPUTS

OUTPUT

Q

RESET

CLK

D

5

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

1

ABSOLUTE MAXIMUM RATINGS

LIMITS

SYMBOL

PARAMETER

CONDITION

UNIT

MIN

–0.5

—

MAX

V

DD

Supply voltage range

Input voltage range

+3.6

V

Notes 2 and 3

V

DD

V

DD

+ 0.5

I

O

V

Output voltage range

+ 0.5

V

I

IK

Input clamp current

V < 0 or V > V

±50

mA

I

DD

I

Output clamp current

V

< 0 or V > V

DD

—

±50

OK

O

I

O

Continuous output current

V

O

= 0 to V

DD

—

Continuous current through each

—

±100

mA

V

DD

or GND

T

stg

Storage temperature range

–65

+150

°C

NOTES:

1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

3. This value is limited to 3.6 V maximum.

4. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

1

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

—

MAX

2.7

UNIT

V

DD

Supply voltage

V

DD

V

Reference voltage

1.15

1.25

1.35

V

REF

V

(V

REF

= V /2)

DD

V

Termination voltage

Input voltage

V

REF

– 40 mV

V

V + 40 mV

REF

V

TT

REF

V

0

—

V

DD

I

V

AC HIGH-level input voltage

AC LOW-level input voltage

DC HIGH-level input voltage

DC LOW-level input voltage

HIGH-level input voltage

LOW-level input voltage

Common-mode input range

Differential input voltage

HIGH-level output current

LOW-level output current

Operating free-air temperature range

Data inputs

RESET

V

+ 310 mV

—

V

IH

REF

V

—

+ 150 mV

—

V

– 310 mV

—

V

IL

REF

V

IH

V

REF

V

– 150 mV

V

IL

REF

V

IH

1.7

V

DD

V

0.0

0.7

1.53

—

V

IL

V

ICR

CK, CK

0.97

360

—

V

ID

mV

mA

°C

I

–20

20

OH

I

OL

—

T

amb

0

+70

NOTE:

1. The RESET input of the device must be held at V or GND to ensure proper device operation. The differential inputs must not be floating,

DD

unless RESET is low.

6

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

T

amb

= 0 to +70 °C

UNIT

MIN

TYP

—

MAX

–1.2

—

V

I = –18 mA, V = 2.3 V

—

V

IK

I

DD

I

= –100 µA, V = 2.3 to 2.7 V

V – 0.2

DD

—

OH

OL

DD

V

OH

= –16 mA, V = 2.3 V

1.95

—

DD

= 100 µA, V = 2.3 to 2.7 V

—

0.2

DD

V

OL

V

= 16 mA, V = 2.3 V

—

0.35

±5

DD

I

All inputs

V = V or GND, V = 2.7 V

—

µA

I

DD

Static standby

RESET = GND

RESET = V , V = V

—

0.01

I

IO = 0, V = 2.7 V

mA

DD

or

DD

I

IH(AC)

Static operating

—

45

V

IL(AC)

RESET = V , V = V

DD

I

Dynamic operating –

clock only

V

IL(AC)

, CK and CK switching

90

—

µA/ clock MHz

50% duty cycle.

RESET = V , V = V or

IH(AC)

DD

I

IO = 0, V = 2.7 V

DD

DDD

V

IL(AC)

, CK and CK switching

Dynamic operating –

per each data input

µA/ clock MHz/

data input

50% duty cycle. One data input

switching at half clock frequency,

50% duty cycle.

20

—

r

Output high

Output low

I

= –20 mA, V = 2.3 to 2.7 V

7

—

20

Ω

OH

OL

DD

r

= 20 mA, V = 2.3 to 2.7 V

DD

OL

|r – r

|

OL

OH

r

I

= 20 mA, T

= 25°C, V = 2.5 V

—

4

Ω

∆

O( )

O

amb

DD

each separate bit

Data inputs

CK and CK

RESET

V = V

± 310 mV, V = 2.5 V

2.5

—

2.74

3.15

2.27

3.5

—

I

REF

DD

V

= 1.25 V, V

= 360 mV, V = 2.5 V

I(PP) DD

C

pF

ICR

i

V = V or GND, V = 2.5 V

I

DD

7

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

TIMING REQUIREMENTS

Over recommended operating conditions; T

= 0 to +70 °C (unless otherwise noted) (see Figure 1)

amb

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

V

DD

= 2.5 V ±0.2 V

MIN

—

MAX

f

Clock frequency

200

—

MHz

ns

clock

t

w

Pulse duration, CK, CK HIGH or LOW

Differential inputs active time

2.5

—

t

act

Notes 1, 2

Notes 1, 3

22

ns

t

Differential inputs inactive time

—

ns

inact

Setup time, fast slew rate

(see Notes 4 and 6)

0.75

0.9

t

Data before CK↑, CK↓

Data after CK↑, CK↓

ns

su

Setup time, slow slew rate

(see Notes 5 and 6)

Hold time, fast slew rate

(see Notes 4 and 6)

0.75

0.9

t

ns

h

Hold time, slow slew rate

(see Notes 5 and 6)

t

SL

Output slew

1

6

V/ns

NOTES:

1. This parameter is not necessarily production tested.

2. Data inputs must be below a minimum time of t max, after RESET is taken high.

act

3. Data and clock inputs must be held at valid levels (not floating) a minimum time of t

4. For data signal input slew rate ≥ 1 V/ns.

max, after RESET is taken low.

inact

5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.

6. CK, CK signals input slew rates are ≥ 1 V/ns.

SWITCHING CHARACTERISTICS

Over recommended operating conditions; T

= 0 to +70 °C; V = 2.3 – 2.7 V

DD .

amb

Class I, V

= V = V × 0.5 and C = 10 pF (unless otherwise noted) (see Figure 1)

REF

TT

DD

L

LIMITS

FROM

(INPUT)

TO

(OUTPUT)

SYMBOL

UNIT

V

DD

= 2.5 V ±0.2 V

MIN

200

1.1

MAX

f

—

2.8

5

MHz

ns

max

t

pd

CK and CK

RESET

Q

t

1.1

ns

PHL

8

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

OUTPUT BUFFER CHARACTERISTICS

The following table describes output-buffer Voltage vs. Current (V/I) characteristics that are sufficient to meet the requirements of registered

DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or

characterization. Compliance with these curves is not mandatory if it can be adequately demonstrated that alternate characteristics meet the

requirements of the registered DDR DIMM application.

PULL-DOWN

PULL-UP

VOLTAGE (V)

I (mA) MIN

0

I (mA) MAX

0

I (mA) MIN

0

I (mA) MAX

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

7

11

7

10

14

21

28

33

39

44

48

52

56

59

61

63

64

66

67

68

—

23

14

21

27

33

38

44

49

53

57

61

64

67

69

70

72

73

74

75

76

—

20

34

30

44

40

54

49

64

59

74

68

83

76

91

84

99

93

107

114

121

127

133

138

142

146

149

151

153

154

155

156

157

100

108

115

121

128

134

139

144

148

152

156

159

161

163

165

167

168

—

PARAMETER MEASUREMENT INFORMATION

TEST CIRCUIT

R

= 50 Ω

L

From Output

Under Test

Test Point

C

= 30 pF

L

see Note 1

SW00751

Figure 1. Load circuitry

NOTE:

1. C includes probe and jig capacitance.

L

9

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

AC WAVEFORMS

LVCMOS

RESET

LVCMOS RESET

Input

V

DD

V

/2

IH

DD

V

/2

DD

V

/2

DD

t

act

inact

V

IL

90%

I

10%

DD

t

PHL

SW00752

OH

Output

Waveform 1. Inputs active and inactive times (see Note 1)

V

TT

V

OL

t

W

SW00755

V

IH

Waveform 4. Propagation delay times

INPUT

V

REF

V

IL

Timing input

SW00753

V

I(PP)

ICR

Waveform 2. Pulse duration

t

su

t

h

TIMING

INPUT

V

ICR

I(PP)

V

IH

V

Input

REF

V

REF

V

IL

t

PHL

PLH

SW00756

V

OH

OL

Waveform 5. Setup and hold times

V

TT

OUTPUT

V

SW00754

Waveform 3. Propagation delay times

NOTES:

1. I tested with clock and data inputs held at V or GND, and I = 0 mA.

DD

O

2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, input slew rate = 1 V/ns ± 20%

O

(unless otherwise specified).

3. The outputs are measured one at a time with one transition per measurement.

4. V = V

= V /2

TT

REF

DD

5. V = V

+ 310 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.

IH DD

– 310 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.

IH

6. V = V

IL

7. t

and t are the same as t .

PHL pd

PLH

10

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm

SOT646-1

11

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls;

body 13.5 x 5.5 x 1.05 mm

SOT536-1

12

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

HVQFN56: plastic, heatsink very thin quad flat package; no leads; 56 terminals;

body 8 x 8 x 0.85 mm

SOT684-1

13

2002 Feb 19

Philips Semiconductors

Product data

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

SSTV16859

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 02-02

9397 750 09464

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

14

2002 Feb 19


型号：	935271266157
厂家：	NXP
描述：	IC POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56, 8 X 8 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-684-1, HVQFN-56, FF/Latch 输出元件逻辑集成电路触发器
文件：	总14页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935271266157 [NXP]

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