935273905112 [NXP]

8-BIT, FLASH, 7.3728MHz, MICROCONTROLLER, PDSO8, 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8;


型号：	935273905112
厂家：	NXP
描述：	8-BIT, FLASH, 7.3728MHz, MICROCONTROLLER, PDSO8, 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8 时钟光电二极管外围集成电路
文件：	总53页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

1 kB 3 V Flash with 128-byte RAM

Rev. 05 — 17 December 2004

Product data

1. General description

The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages,

based on a high performance processor architecture that executes instructions in two

to four clocks, six times the rate of standard 80C51 devices. Many system-level

functions have been incorporated into the P89LPC901/902/903 in order to reduce

component count, board space, and system cost.

2. Features

2.1 Principal features

■ 1 kB byte-erasable Flash code memory organized into 256-byte sectors and

16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile

data storage.

■ 128-byte RAM data memory.

■ Two 16-bit counter/timers. (P89LPC901 Timer 0 may be conﬁgured to toggle a

port output upon timer overﬂow or to become a PWM output.)

■ 23-bit system timer that can also be used as a Real-Time clock.

■ Two analog comparators (P89LPC902 and P89LPC903, single analog

comparator on P89LPC901).

■ Enhanced UART with fractional baudrate generator, break detect, framing error

detection, automatic address detection and versatile interrupt capabilities

(P89LPC903).

■ High-accuracy internal RC oscillator option allows operation without external

oscillator components. The RC oscillator (factory calibrated to ±1 %) option is

selectable and ﬁne tunable.

■ 2.4 V to 3.6 V V_DDoperating range with 5 V tolerant I/O pins (may be pulled up or

driven to 5.5 V). Industry-standard pinout with V_DD, V_SS, and reset at locations 1,

8, and 4.

■ Up to six I/O pins when using internal oscillator and reset options.

■ 8-pin SO-8 package.

2.2 Additional features

■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to

222 ns for all instructions except multiply and divide when executing at 18 MHz

(167 ns to 333 ns at 12 MHz). This is six times the performance of the standard

80C51 running at the same clock frequency. A lower clock frequency for the same

performance results in power savings and reduced EMI.

■ In-Application Programming (IAP-Lite) and byte erase allows code memory to be

used for non-volatile data storage.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

■ Serial Flash In-Circuit Programming (ICP) allows simple production coding with

commercial EPROM programmers. Flash security bits prevent reading of sensitive

application programs.

■ Watchdog timer with separate on-chip oscillator, requiring no external

components. The watchdog prescaler is selectable from 8 values.

■ Low voltage reset (Brownout detect) allows a graceful system shutdown when

power fails. May optionally be conﬁgured as an interrupt.

■ Idle and two different Power-down reduced power modes. Improved wake-up from

Power-down mode (a low interrupt input starts execution). Typical Power-down

current is 1 µA (total Power-down with voltage comparators disabled).

■ Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent

spurious and incomplete resets. A software reset function is also available.

■ Conﬁgurable on-chip oscillator with frequency range options selected by user

programmed Flash conﬁguration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz (P89LPC901).

■ Watchdog timer with separate on-chip oscillator, requiring no external

components. The watchdog prescaler is selectable from 8 values.

■ Programmable port output conﬁguration options: quasi-bidirectional, open drain,

push-pull, input-only.

■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value

of the pins match or do not match a programmable pattern.

■ LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the

entire chip.

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately

10 ns minimum ramp times.

■ Only power and ground connections are required to operate the

P89LPC901/902/903 when internal reset option is selected.

■ Four interrupt priority levels.

■ Two (P89LPC901), three (P89LPC903), or ﬁve (P89LPC902) keypad interrupt

inputs.

■ Second data pointer.

■ Schmitt trigger port inputs.

■ Emulation support.

9397 750 14465

Product data

Rev. 05 — 17 December 2004

2 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

SO8

Description

Version

P89LPC901FD

P89LPC902FD

P89LPC903FD

P89LPC901FN

P89LPC902FN

plastic small outline package; 8 leads;

body width 7.5 mm

SOT96-1

DIP8

plastic dual in-line package; 8 leads (300 mil) SOT97-1

3.1 Ordering options

Table 2:

Part options

Type number

P89LPC901xx

P89LPC902xx

P89LPC903xx

Temperature range

Frequency

−40 °C to +85 °C

0 MHz to 18 MHz

Internal RC or watchdog

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Product data

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

4. Block diagram

P89LPC901

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

1 kB

CODE FLASH

TIMER 0

TIMER 1

INTERNAL BUS

128-BYTE

DATA RAM

REAL-TIME CLOCK/

SYSTEM TIMER

PORT 3

CONFIGURABLE I/Os

ANALOG

COMPARATOR

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

CLOCK

CRYSTAL

RESONATOR

ON-CHIP

OSCILLATOR

CONFIGURABLE

OSCILLATOR

002aaa444

Fig 1. P89LPC901 block diagram.

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Product data

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4 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

P89LPC902

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

1 kB

CODE FLASH

TIMER 0

TIMER 1

INTERNAL

BUS

128-BYTE

DATA RAM

REAL-TIME CLOCK/

SYSTEM TIMER

PORT 1

INPUT

ANALOG

COMPARATORS

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

CLOCK

ON-CHIP

OSCILLATOR

002aaa445

Fig 2. P89LPC902 block diagram.

9397 750 14465

Product data

Rev. 05 — 17 December 2004

5 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

P89LPC903

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

1 kB

CODE FLASH

UART

INTERNAL

BUS

128-BYTE

DATA RAM

TIMER 0

TIMER 1

PORT 1

INPUT

REAL-TIME CLOCK/

SYSTEM TIMER

PORT 0

CONFIGURABLE I/Os

ANALOG

COMPARATORS

KEYPAD

INTERRUPT

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

CLOCK

ON-CHIP

OSCILLATOR

002aaa446

Fig 3. P89LPC903 block diagram.

9397 750 14465

Product data

Rev. 05 — 17 December 2004

6 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

5. Pinning information

5.1 Pinning

handbook, halfpage

XTAL1/P3.1

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P1.2/T0

CLKOUT/XTAL2/P3.0

RST/P1.5

002aaa438

Fig 4. P89LPC901 pinning (SO8).

handbook, halfpage

8 V

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

RST/P1.5

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P1.2/T0

002aaa469

002aaa439

002aaa470

Fig 5. P89LPC901 pinning (DIP8).

handbook, halfpage

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

RST/P1.5

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

Fig 6. P89LPC902 pinning (SO8).

handbook, halfpage

8 V

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

RST/P1.5

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

Fig 7. P89LPC902 pinning (DIP8).

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

handbook, halfpage

P0.2/CIN2A/KBI2

P1.1/RxD

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P1.0/TxD

RST/P1.5

002aaa440

Fig 8. P89LPC903 pinning (SO8).

5.2 Pin description

Table 3:

P89LPC901 pin description

Symbol

Type

Description

P0.0 to P0.6

I/O

Port 0: Port 0 is an I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The

operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.4 — Port 0 bit 4.

I/O

CIN1A — Comparator 1 positive input.

KBI4 — Keyboard input 4.

I/O

P0.5 — Port 0 bit 5.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

9397 750 14465

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 3:

P89LPC901 pin description…continued

Symbol

Type

Description

P1.0 to P1.5

Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During reset Port 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The

operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the

port conﬁguration selected. Each of the conﬁgurable port pins are programmed

independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.2 — Port 1 bit 2.

I/O

T0 — Timer/counter 0 external count input or overﬂow output.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during Power-on or if selected via UCFG1. When

functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. When using an oscillator frequency above 12 MHz, the

reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until V_DDhas reached its speciﬁed level.

When system power is removed V_DDwill fall below the minimum speciﬁed

operating voltage. When using an oscillator frequency above 12 MHz, in some

applications, an external brownout detect circuit may be required to hold the

device in reset when V_DDfalls below the minimum speciﬁed operating voltage.

Also used during a power-on sequence to force In-System Programming mode.

P3.0 to P3.1

I/O

Port 3: Port 3 is an I/O port with a user-conﬁgurable output types. During reset Port 3

latches are conﬁgured in the input only mode with the internal pull-up disabled. The

operation of port 3 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

P3.0 — Port 3 bit 0.

I/O

XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the FLASH conﬁguration).

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK to TRIM.6). It

can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source

for the real time clock/system timer.

I/O

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the FLASH conﬁguration). It can be a port pin if internal RC oscillator or

Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not

used to generate the clock for the real time clock/system timer.

V_SS

V_DD

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power-down modes.

9397 750 14465

Product data

Rev. 05 — 17 December 2004

9 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 4:

P89LPC902 pin description

Symbol

Type

Description

P0.0 to P0.6

I/O

Port 0: Port 0 is an I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The

operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.0 — Port 0 bit 0.

I/O

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

I/O

P0.2 — Port 0 bit 2.

CIN2A — Comparator 2 positive input.

KBI2 — Keyboard input 2.

I/O

P0.4 — Port 0 bit 4.

CIN1A — Comparator 1 positive input.

KBI4 — Keyboard input 4.

I/O

P0.5 — Port 0 bit 5.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

I/O

P0.6 — Port 0 bit 6.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

P1.0 to P1.5

Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During reset Port 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The

operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the

port conﬁguration selected. Each of the conﬁgurable port pins are programmed

independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during Power-on or if selected via UCFG1. When

functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force In-System

Programming mode.

V_SS

V_DD

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power-down modes.

9397 750 14465

Product data

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 5:

P89LPC903 pin description

Symbol

Type

Description

P0.0 to P0.6

I/O

Port 0: Port 0 is an I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The

operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.2 — Port 0 bit 2.

I/O

CIN2A — Comparator 2 positive input.

KBI2 — Keyboard input 2.

I/O

P0.4 — Port 0 bit 4.

CIN1A — Comparator 1 positive input.

KBI4 — Keyboard input 4.

I/O

P0.5 — Port 0 bit 5.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

P1.0 to P1.5

Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During reset Port 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The

operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the

port conﬁguration selected. Each of the conﬁgurable port pins are programmed

independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.0 — Port 1 bit 0.

I/O

TxD — Serial port transmitter data.

P1.1 — Port 1 bit 1.

I/O

RxD — Serial port receiver data.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during Power-on or if selected via UCFG1. When

functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force In-System

Programming mode.

V_SS

V_DD

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power-down modes.

9397 750 14465

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

6. Logic symbols

KBI4

KBI5

CIN1A

CMPREF

RST

CLKOUT

XTAL2

XTAL1

002aaa441

Fig 9. P89LPC901 logic symbol.

KBI4

KBI5

KBI6

KBI2

KBI0

CIN1A

CMPREF

CMP1

CIN2A

CMP2

RST

002aaa442

Fig 10. P89LPC902 logic symbol.

RST

RxD

TxD

KBI4

KBI5

KBI2

CIN1A

CMPREF

CIN2A

002aaa443

Fig 11. P89LPC903 logic symbol.

9397 750 14465

Product data

Rev. 05 — 17 December 2004

12 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 6 highlights the differences between these three devices. For a complete list of

device features, please see Section 2 “Features” on page 1.

Table 6:

Product comparison overview

Type number

External

CLKOUT output T0 PWM output CMP2 input

CMP1 and

UART

crystal pins

CMP2 outputs

TxD

Rxd

P89LPC901xx

P89LPC902xx

P89LPC903xx

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

7. Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Rev. 05 — 17 December 2004

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 7:

P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

E0H

ACC*

Accumulator

00000000

AUXR1

Auxiliary function register

A2H

CLKLP

ENT0

SRST

DPS

00^[1]000000x0

Bit address

F0H

B register

00000000

CMP1

DIVM

Comparator 1 control register ACH

CE1

CN1

CO1

CMF1 00^[1]xx000000

CPU clock divide-by-M

control

95H

00000000

DPTR

DPH

DPL

Data pointer (2 bytes)

Data pointer high

Data pointer low

83H

82H

E7H

E6H

E4H

00000000

01110000

FMADRH Program Flash address high

FMADRL Program Flash address low

FMCON

Program Flash Control

(Read)

BUSY

HVA

HVE

Program Flash Control

(Write)

FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

IEN0*

Program Flash data

Interrupt enable 0

E5H

A8H

00000000

EWDRT

EBO

ET1

ET0

Bit address

E8H

IEN1*

Interrupt enable 1

EKBI

00^[1]00x00000

Bit address

B8H

IP0*

Interrupt priority 0

PWDRT

PBO

PBOH

PT1

PT1H

PT0

PT0H

00^[1]x0000000

IP0H

Interrupt priority 0 high

B7H

PWDRT

Bit address

F8H

PCH

IP1*

Interrupt priority 1

PKBI

PKBIH

00^[1]00x00000

00^[1]xxxxxx00

IP1H

Interrupt priority 1 high

Keypad control register

F7H

KBCON

94H

PATN

_SEL

KBIF

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P89LPC901 Special function registers…continued

Table 7:

* indicates SFRs that are bit addressable.

Name Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

KBMASK Keypad interrupt mask

86H

00000000

KBPATN

Keypad pattern register

93H

Bit address

80H

11111111

[1]

P0*

Port 0

CMPREF CIN1A

/KB5

/KB4

Bit address

90H

[1]

P1*

Port 1

RST

Bit address

B0H

P3*

Port 3

XTAL1

XTAL2

P0M1

P0M2

P1M1

P1M2

P3M1

P3M2

PCON

PCONA

PCONB

Port 0 output mode 1

Port 0 output mode 2

Port 1 output mode 1

Port 1 output mode 2

Port 3 output mode 1

Port 3 output mode 2

Power control register

Power control register A

84H

(P0M1.5) (P0M1.4)

(P0M2.5) (P0M2.4)

11111111

00000000

85H

91H

(P1M1.5)

(P1M1.2)

FF^[1]11111111

00^[1]00000000

92H

(P1M2.5)

(P1M2.2)

B1H

(P3M1.1) (P3M1.0) 03^[1]xxxxxx11

(P3M2.1) (P3M2.0) 00^[1]xxxxxx00

B2H

87H

BOPD

VCPD

BOI

GF1

GF0

PMOD1 PMOD0 00

00000000

B5H RTCPD

00^[1]00000000

00^[1]xxxxxxxx

reserved for Power Control

B6H

Bit address

PSW*

Program status word

Port 0 digital input disable

D0H

RS1

RS0

00000000

xx00000x

PT0AD

F6H

DFH

D1H

PT0AD.5 PT0AD.4

[3]

RSTSRC Reset source register

RTCCON Real-time clock control

BOF

POF

R_WD

R_SF

ERTC

R_EX

RTCF

RTCS1

RTCS0

RTCEN 60^[1]011xxx00

[6]

RTCH

RTCL

Real-time clock register high

Real-time clock register low

Stack pointer

D2H

D3H

81H

8FH

00^[6]00000000

00000111

xxx0xxx0

TAMOD

Timer 0 auxiliary mode

T0M2

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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P89LPC901 Special function registers…continued

Table 7:

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

88H

TCON*

TH0

Timer 0 and 1 control

Timer 0 high

TF1

TR1

TF0

TR0

00000000

8CH

TH1

Timer 1 high

8DH

TL0

Timer 0 low

8AH

TL1

Timer 1 low

8BH

TMOD

TRIM

WDCON

WDL

Timer 0 and 1 mode

89H

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0M1

T0M0

[5] [6]

Internal oscillator trim register 96H

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[4] [6]

Watchdog control register

Watchdog load

A7H

C1H

C2H

C3H

PRE2

PRE1

WDRUN WDTOF WDCLK

11111111

WFEED1 Watchdog feed 1

WFEED2 Watchdog feed 2

[1] All ports are in input only (high impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

[3] The RSTSRC register reﬂects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 8:

P89LPC902 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

E0H

ACC*

Accumulator

00000000

AUXR1

Auxiliary function register

A2H

SRST

DPS

00^[1]000000x0

Bit address

F0H

B register

00000000

CMP1

CMP2

DIVM

Comparator 1 control register ACH

Comparator 2 control register ADH

CE1

CE2

CN1

CN2

OE1

OE2

CO1

CO2

CMF1 00^[1]xx000000

CMF2 00^[1]xx000000

CPU clock divide-by-M

control

95H

00000000

DPTR

DPH

DPL

Data pointer (2 bytes)

Data pointer high

Data pointer low

83H

82H

E7H

E6H

E4H

00000000

01110000

FMADRH Program Flash address high

FMADRL Program Flash address low

FMCON

Program Flash Control

(Read)

BUSY

HVA

HVE

Program Flash Control

(Write)

FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

IEN0*

Program Flash data

Interrupt enable 0

E5H

A8H

00000000

EWDRT

EBO

ET1

ET0

Bit address

E8H

IEN1*

Interrupt enable 1

EKBI

00^[1]00x00000

Bit address

B8H

IP0*

Interrupt priority 0

PWDRT

PBO

PBOH

PT1

PT1H

PT0

PT0H

00^[1]x0000000

IP0H

Interrupt priority 0 high

B7H

PWDRT

Bit address

F8H

IP1*

Interrupt priority 1

PKBI

PKBIH

00^[1]00x00000

IP1H

Interrupt priority 1 high

F7H

PCH

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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P89LPC902 Special function registers…continued

Table 8:

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

KBCON

Keypad control register

94H

86H

PATN

_SEL

KBIF

00^[1]xxxxxx00

KBMASK Keypad interrupt mask

[1]

00000000

11111111

KBPATN

Keypad pattern register

93H

Bit address

80H

P0*

Port 0

CMP1 CMPREF CIN1A

KB2

KB0

/KB6

/KB5

/KB4

Bit address

90H

P1*

Port 1

RST

Bit address

84H

P0M1

Port 0 output mode 1

Port 0 output mode 2

Port 1 output mode 1

Port 1 output mode 2

Power control register

Power control register A

(P0M1.6) (P0M1.5) (P0M1.4)

(P0M2.6) (P0M2.5) (P0M2.4)

(P0M1.2)

(P0M1.0) FF

(P0M2.0) 00

11111111

00000000

FF^[1]11111111

00^[1]00000000

P0M2

85H

(P0M2.2)

P1M1

91H

(P1M1.5)

(P1M2.5)

BOPD

VCPD

P1M2

92H

PCON

PCONA

PCONB

87H

BOI

GF1

GF0

PMOD1 PMOD0 00

00000000

B5H RTCPD

00^[1]00000000

00^[1]xxxxxxxx

reserved for Power Control

B6H

Bit address

PSW*

Program status word

Port 0 digital input disable

D0H

RS1

RS0

00000000

xx00000x

PT0AD

F6H

DFH

D1H

PT0AD.5 PT0AD.4

PT0AD.2

R_WD

[3]

RSTSRC Reset source register

RTCCON Real-time clock control

BOF

POF

R_SF

ERTC

R_EX

RTCF

RTCS1

RTCS0

RTCEN 60^[1]011xxx00

[6]

RTCH

RTCL

Real-time clock register high

Real-time clock register low

Stack pointer

D2H

D3H

81H

00^[6]00000000

00000111

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P89LPC902 Special function registers…continued

Table 8:

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

88H

TCON*

TH0

Timer 0 and 1 control

Timer 0 high

TF1

TR1

TF0

TR0

00000000

8CH

TH1

Timer 1 high

8DH

TL0

Timer 0 low

8AH

TL1

Timer 1 low

8BH

TMOD

TRIM

WDCON

WDL

Timer 0 and 1 mode

89H

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0M1

T0M0

[5] [6]

Internal oscillator trim register 96H

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[4] [6]

Watchdog control register

Watchdog load

A7H

C1H

C2H

C3H

PRE2

PRE1

WDRUN WDTOF WDCLK

11111111

WFEED1 Watchdog feed 1

WFEED2 Watchdog feed 2

[1] All ports are in input only (high impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

[3] The RSTSRC register reﬂects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 9:

P89LPC903 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

E0H

ACC*

Accumulator

00000000

AUXR1

Auxiliary function register

A2H

EBRR

SRST

DPS

00^[1]000000x0

Bit address

F0H

B register

00000000

BRGR0^[2]Baud rate generator rate low

BRGR1^[2]Baud rate generator rate high BFH

BRGCON Baud rate generator control BDH

BEH

SBRGS BRGEN 00^[6]xxxxxx00

CMP1

CMP2

DIVM

Comparator 1 control register ACH

Comparator 2 control register ADH

CE1

CE2

CN1

CN2

CO1

CO2

CMF1 00^[1]xx000000

CMF2 00^[1]xx000000

CPU clock divide-by-M

control

95H

00000000

DPTR

DPH

DPL

Data pointer (2 bytes)

Data pointer high

Data pointer low

83H

82H

E7H

E6H

E4H

00000000

01110000

FMADRH Program Flash address high

FMADRL Program Flash address low

FMCON

Program Flash Control

(Read)

BUSY

HVA

HVE

Program Flash Control

(Write)

FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

IEN0*

Program Flash data

Interrupt enable 0

E5H

A8H

00000000

EWDRT

EBO

ES/ESR

ET1

ET0

Bit address

E8H

IEN1*

Interrupt enable 1

EST

EKBI

00^[1]00x00000

Bit address

B8H

IP0*

Interrupt priority 0

PWDRT

PBO

PBOH

PS/PSR

PT1

PT1H

PT0

PT0H

00^[1]x0000000

IP0H

Interrupt priority 0 high

B7H

PWDRT

PSH

/PSRH

Bit address

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P89LPC903 Special function registers…continued

Table 9:

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

IP1*

Interrupt priority 1

F8H

F7H

94H

PST

PSTH

PCH

PKBI

00^[1]00x00000

00^[1]xxxxxx00

IP1H

Interrupt priority 1 high

Keypad control register

PKBIH

KBCON

PATN

_SEL

KBIF

KBMASK Keypad interrupt mask

86H

[1]

00000000

11111111

KBPATN

Keypad pattern register

93H

Bit address

80H

P0*

Port 0

CMPREF CIN1A

KB2

/KB5

/KB4

Bit address

90H

P1*

Port 1

RST

RxD

TxD

P0M1

P0M2

P1M1

P1M2

PCON

PCONA

PCONB

Port 0 output mode 1

Port 0 output mode 2

Port 1 output mode 1

Port 1 output mode 2

Power control register

Power control register A

84H

(P0M1.5) (P0M1.4)

(P0M2.5) (P0M2.4)

(P0M1.2)

11111111

00000000

85H

(P0M2.2)

91H

(P1M1.5)

(P1M2.5)

BOPD

VCPD

(P1M1.1) (P1M1.0) FF^[1]11111111

(P1M2.1) (P1M2.0) 00^[1]00000000

92H

87H SMOD1 SMOD0

B5H RTCPD

BOI

GF1

GF0

PMOD1 PMOD0 00

00000000

SPD

00^[1]00000000

00^[1]xxxxxxxx

reserved for Power Control

B6H

Bit address

RS0

PSW*

Program status word

Port 0 digital input disable

D0H

RS1

00000000

xx00000x

PT0AD

F6H

DFH

D1H

PT0AD.5 PT0AD.4

PT0AD.2

R_WD

[3]

RSTSRC Reset source register

RTCCON Real-time clock control

BOF

POF

R_BK

R_SF

ERTC

R_EX

RTCF

RTCS1

RTCS0

RTCEN 60^[1]011xxx00

[6]

RTCH

Real-time clock register high

Real-time clock register low

Serial port address register

Serial port address enable

D2H

D3H

A9H

B9H

00^[6]00000000

RTCL

SADDR

SADEN

00000000

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P89LPC903 Special function registers…continued

Table 9:

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

SBUF

Serial port data buffer register 99H

xxxxxxxx

Bit address

TB8

RB8

SCON*

SSTAT

Serial port control

98H SM0/FE

BAH DBMOD

SM1

SM2

CIDIS

REN

00000000

Serial port extended status

INTLO

DBISEL

STINT 00

Stack pointer

81H

00000111

Bit address

TCON*

TH0

Timer 0 and 1 control

Timer 0 high

88H

8CH

8DH

8AH

8BH

89H

TF1

TR1

TF0

TR0

00000000

TH1

Timer 1 high

TL0

Timer 0 low

TL1

Timer 1 low

TMOD

TRIM

WDCON

WDL

Timer 0 and 1 mode

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0M1

T0M0

[5] [6]

Internal oscillator trim register 96H

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[4] [6]

Watchdog control register

Watchdog load

A7H

C1H

C2H

C3H

PRE2

PRE1

WDRUN WDTOF WDCLK

11111111

WFEED1 Watchdog feed 1

WFEED2 Watchdog feed 2

[1] All ports are in input only (high impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

[3] The RSTSRC register reﬂects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

8. Functional description

Remark: Please refer to the P89LPC901/902/903 User’s Manual for a more detailed

functional description.

8.1 Enhanced CPU

The P89LPC901/902/903 uses an enhanced 80C51 CPU which runs at 6 times the

speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles,

and most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1 Clock deﬁnitions

The P89LPC901/902/903 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the

clock sources (see Figure 12, 13, and 14) and can also be optionally divided to a

slower frequency (see Section 8.7 “CPU CLOCK (CCLK) modiﬁcation: DIVM

Note: f_oscis deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two

or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK/2

8.2.2 CPU clock (OSCCLK)

The P89LPC901/902/903 provides several user-selectable oscillator options in

generating the CPU clock. This allows optimization for a range of needs from high

precision to lowest possible cost. These options are conﬁgured when the FLASH is

programmed and include an on-chip Watchdog oscillator and an on-chip RC

oscillator.

The P89LPC901, in addition, includes an option for an oscillator using an external

crystal or an external clock source. The crystal oscillator can be optimized for low,

medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

8.2.3 Low speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

8.2.4 Medium speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

9397 750 14465

Product data

Rev. 05 — 17 December 2004

24 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

8.2.5 High speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V_DDhas

reached its speciﬁed level. When system power is removed V_DDwill fall below

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V_DDfalls below the minimum

speciﬁed operating voltage. If CCLK is 8 MHz or slower, the CLKLP SFR bit

(AUXR1.7) can be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’

allowing highest performance access. This bit can then be set in software if CCLK is

running at 8 MHz or slower.

8.2.6 Clock output (P89LPC901)

The P89LPC901 supports a user selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,

external clock input on X1) and if the Real-Time clock is not using the crystal

oscillator as its clock source. This allows external devices to synchronize to the

P89LPC901. This output is enabled by the ENCLK bit in the TRIM register. The

frequency of this clock output is ¹⁄₂that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

The P89LPC901/902/903 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±2.5%.

End-user applications can write to the Trim register to adjust the on-chip RC oscillator

to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can

be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’ allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz

or slower.

8.4 Watchdog oscillator option

The Watchdog has a separate oscillator which has a frequency of 400 kHz. This

oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option (P89LPC901)

In this conﬁguration, the processor clock is derived from an external source driving

the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin

may be used as a standard port pin or a clock output. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V_DDhas

reached its speciﬁed level. When system power is removed V_DDwill fall below

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V_DDfalls below the minimum

speciﬁed operating voltage.

9397 750 14465

Product data

Rev. 05 — 17 December 2004

25 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

XTAL1

XTAL2

High freq.

Med. freq.

Low freq.

RTC

OSCCLK

CCLK

DIVM

CPU

WDT

OSCILLATOR

(7.3728 MHz)

WATCHDOG

OSCILLATOR

PCLK

(400 kHz)

TIMERS 0 & 1

002aaa447

Fig 12. Block diagram of oscillator control (P89LPC901).

RTC

OSCCLK

CCLK

OSCILLATOR

DIVM

CPU

WDT

(7.3728 MHz)

WATCHDOG

OSCILLATOR

PCLK

(400 kHz)

TIMERS 0 & 1

002aaa448

Fig 13. Block diagram of oscillator control (P89LPC902).

RTC

CPU

OSCCLK

CCLK

OSCILLATOR

DIVM

(7.3728 MHz)

WDT

WATCHDOG

OSCILLATOR

PCLK

(400 kHz)

TIMERS 0 & 1

002aaa449

BAUD RATE

GENERATOR

UART

Fig 14. Block diagram of oscillator control (P89LPC903).

9397 750 14465

Product data

Rev. 05 — 17 December 2004

26 of 53

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

8.6 CPU CLock (CCLK) wake-up delay

The P89LPC901/902/903 has an internal wake-up timer that delays the clock until it

stabilizes depending to the clock source used. If the clock source is any of the three

crystal selections (P89LPC901) the delay is 992 OSCCLK cycles plus 60 to 100 µs.

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

8.8 Low power select

The P89LPC901 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK

is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power

consumption further. On any reset, CLKLP is ‘0’ allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.9 Memory organization

The various P89LPC901/902/903 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect

addressing, using instruction other than MOVX and MOVC. All or part of the Stack

may be in this area.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC901/902/903 has 1 kB of on-chip Code memory.

8.10 Data RAM arrangement

The 128 bytes of on-chip RAM is organized as follows:

Table 10: On-chip data memory usages

Type

Data RAM

Size (Bytes)

DATA

Memory that can be addressed directly and indirectly 128

8.11 Interrupts

The P89LPC901/902/903 uses a four priority level interrupt structure. This allows

great ﬂexibility in controlling the handling of the many interrupt sources.

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The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect,

Watchdog/real-time clock, keyboard, and the comparator.

The P89LPC902 supports 6 interrupt sources: timers 0 and 1, brownout detect,

Watchdog/real-time clock, keyboard, and comparators 1 and 2.

The P89LPC903 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial

port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/real-time clock,

keyboard, and comparators 1 and 2.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt,

but not by another interrupt of the same or lower priority. The highest priority interrupt

service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an

internal polling sequence determines which request is serviced. This is called the

arbitration ranking. Note that the arbitration ranking is only used to resolve pending

requests of the same priority level.

8.11.1 External interrupt inputs

The P89LPC901/902/903 has a Keypad Interrupt function. This can be used as an

external interrupt input.

If enabled when the P89LPC901/902/903 is put into Power-down or Idle mode, the

interrupt will cause the processor to wake-up and resume operation. Refer to Section

8.14 “Power reduction modes” for details.

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BOF

EBO

RTCF

KBIF

EKBI

WAKE-UP

(IF IN POWER-DOWN)

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF

EA (IE0.7)

TF1

ET1

INTERRUPT

TO CPU

TF0

ET0

002aaa450

Fig 15. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC901).

BOF

EBO

RTCF

KBIF

EKBI

WAKE-UP

(IF IN POWER-DOWN)

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF

EA (IE0.7)

TF1

ET1

INTERRUPT

TO CPU

TF0

ET0

002aaa451

Fig 16. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC902).

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BOF

EBO

RTCF

KBIF

EKBI

WAKE-UP

(IF IN POWER-DOWN)

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF

EA (IE0.7)

TF1

ET1

TI & RI/RI

ES/ESR

INTERRUPT

TO CPU

EST

TF0

ET0

002aaa452

Fig 17. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC903).

8.12 I/O ports

The P89LPC901 has between 3 and 6 I/O pins: P0.4, P0.5, P1.2, P1.5, P3.0, and

P3.1 The exact number of I/O pins available depends on the clock and reset options

chosen, as shown in Table 11.

Table 11: Number of I/O pins available

Clock source

Reset option

Number of I/O pins

(8-pin package)

On-chip oscillator or Watchdog oscillator

No external reset (except during power-up)

External RST pin supported

External clock input

No external reset (except during power-up)

External RST pin supported^[1]

Low/medium/high speed oscillator

(external crystal or resonator)

No external reset (except during power-up)

External RST pin supported^[1]

[1] Required for operation above 12 MHz.

The P89LPC902 and P89LPC903 devices have either 5 or 6 I/O pins depending on

the reset pin option chosen.

8.12.1 Port conﬁgurations

All but one I/O port pin on the P89LPC901/902/903 may be conﬁgured by software to

one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51

port outputs), push-pull, open drain, and input-only. Two conﬁguration registers for

each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be conﬁgured.

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8.12.2 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the

need to reconﬁgure the port. This is possible because when the port outputs a logic

HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the

pin is driven LOW, it is driven strongly and able to sink a fairly large current. These

features are somewhat similar to an open-drain output except that there are three

pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC901/902/903 is a 3 V device, however, the pins are 5 V-tolerant (except

for XTAL1 and XTAL2). In quasi-bidirectional mode, if a user applies 5 V on the pin,

there will be a current ﬂowing from the pin to V_DD, causing extra power consumption.

Therefore, applying 5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

8.12.3 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the

pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be

used as a logic output, a port conﬁgured in this manner must have an external

pull-up, typically a resistor tied to V_DD

An open-drain port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

8.12.4 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt-triggered input

that also has a glitch suppression circuit.

8.12.5 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous

strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be

used when more source current is needed from a port output. A push-pull port pin

has a Schmitt-triggered input that also has a glitch suppression circuit.

8.12.6 Port 0 analog functions

The P89LPC901/902/903 incorporates an Analog Comparator. In order to give the

best analog function performance and to minimize power consumption, pins that are

being used for analog functions must have the digital outputs and digital inputs

disabled.

Digital outputs are disabled by putting the port output into the Input-Only (high

impedance) mode as described in Section 8.12.4 “Input-only conﬁguration”.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On

any reset, the PT0AD bits default to ‘0’s to enable digital functions.

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8.12.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different

from the LPC76x series of devices.

• After power-up all I/O pins, except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only.

Every output on the P89LPC901/902/903 has been designed to sink typical LED

drive current. However, there is a maximum total output current for all ports which

must not be exceeded. Please refer to Table 13 “DC electrical characteristics” for

detailed speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit

noise generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

8.13 Power monitoring functions

The P89LPC901/902/903 incorporates power monitoring functions designed to

prevent incorrect operation during initial power-up and power loss or reduction during

operation. This is accomplished with two hardware functions: Power-on Detect and

Brownout detect.

8.13.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a

certain level. The default operation is for a Brownout detection to cause a processor

reset, however, it may alternatively be conﬁgured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled, the operating voltage range for V_DDis 2.7 V to 3.6 V,

and the brownout condition occurs when V_DDfalls below the brownout trip voltage,

V_BO(see Table 13 “DC electrical characteristics”), and is negated when V_DDrises

above V_BO. If brownout detection is disabled, the operating voltage range for V_DDis

2.4 V to 3.6 V. If the P89LPC901/902/903 device is to operate with a power supply

that can be below 2.7 V, BOE should be left in the unprogrammed state so that the

device can operate at 2.4 V, otherwise continuous brownout reset may prevent the

device from operating.

For correct activation of Brownout detect, the V_DDrise and fall times must be

observed. Please see Table 13 “DC electrical characteristics” for speciﬁcations.

8.13.2 Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to

work as power comes up initially, before the power supply voltage reaches a level

where Brownout detect can work. The POF ﬂag in the RSTSRC register is set to

indicate an initial power-up condition. The POF ﬂag will remain set until cleared by

software.

8.14 Power reduction modes

The P89LPC901/902/903 supports three different power reduction modes. These

modes are Idle mode, Power-down mode, and total Power-down mode.

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8.14.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate

Idle mode.

8.14.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption.

The P89LPC901/902/903 exits Power-down mode via any reset, or certain interrupts.

In Power-down mode, the power supply voltage may be reduced to the RAM

keep-alive voltage V_RAM. This retains the RAM contents at the point where

Power-down mode was entered. SFR contents are not guaranteed after V_DDhas

been lowered to V_RAM, therefore it is highly recommended to wake up the processor

via reset in this case. V_DDmust be raised to within the operating range before the

Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during Power-down. These include: Brownout detect,

Watchdog Timer, Comparators (note that Comparators can be powered-down

separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is

disabled unless both the RC oscillator has been selected as the system clock and the

RTC is enabled.

8.14.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry

and the voltage comparators are also disabled to conserve additional power. The

internal RC oscillator is disabled unless both the RC oscillator has been selected as

the system clock and the RTC is enabled. If the internal RC oscillator is used to clock

the RTC during Power-down, there will be high power consumption. Please use an

external low frequency clock to achieve low power with the Real-Time Clock running

during Power-down.

8.15 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital

input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the

external reset input function on P1.5. When cleared, P1.5 may be used as an input

pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

will always function as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this input will function either as an external reset

input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will

temporarily override the selection deﬁned by RPE bit. Other sources of reset will not

override the RPE bit.

Remark: During a power cycle, V_DDmust fall below V_POR(see Table 13 “DC electrical

characteristics”) before power is reapplied, in order to ensure a power-on reset.

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Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1. This option

must be used for an oscillator frequency above 12 MHz.)

• Power-on detect

• Brownout detect

• Watchdog Timer

• Software reset

• UART break character detect reset (P80LPC903).

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can

read this register to determine the most recent reset source. These ﬂag bits can be

cleared in software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit

may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain

set.

8.16 Timers/counters 0 and 1

The P89LPC901/902/903 has two general purpose timers which are similar to the

standard 80C51 Timer 0 and Timer 1. These timers have four operating modes

(modes 0, 1, 2, and 3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is

different.

8.16.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured

as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.16.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

8.16.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload.

Mode 2 operation is the same for Timer 0 and Timer 1.

8.16.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When

Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.16.5 Mode 6 (P89LPC901)

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

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8.16.6 Timer overﬂow toggle output (P89LPC901)

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a

timer overﬂow occurs. The same device pins that are used for the T0 and T1 count

inputs are also used for the timer toggle outputs. The port outputs will be a logic 1

prior to the ﬁrst timer overﬂow when this mode is turned on.

8.17 Real-Time clock/system timer

The P89LPC901/902/903 has a simple Real-Time clock that allows a user to continue

running an accurate timer while the rest of the device is powered-down. The

Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a

23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down

counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF

ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK)

or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU

clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as

its clock source. Only power-on reset will reset the Real-Time clock and its

associated SFRs to the default state.

8.18 UART (P89LPC903)

The P89LPC903 has an enhanced UART that is compatible with the conventional

80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source.

The P89LPC903 does include an independent Baud Rate Generator. The baud rate

can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the

independent Baud Rate Generator. In addition to the baud rate generation,

enhancements over the standard 80C51 UART include Framing Error detection,

automatic address recognition, selectable double buffering and several interrupt

options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit

UART, and CPU clock/32 or CPU clock/16.

8.18.1 Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₁₆of the CPU clock

frequency.

8.18.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit

(logical ‘0’), 8 data bits (LSB ﬁrst), and a stop bit (logical ‘1’). When data is received,

the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is

variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator

(described in Section 8.18.5 “Baud rate generator and selection”).

8.18.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’),

8 data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logical ‘1’). When

data is transmitted, the 9^thdata bit (TB8 in SCON) can be assigned the value of ‘0’ or

‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When

data is received, the 9^thdata bit goes into RB8 in Special Function Register SCON,

while the stop bit is not saved. The baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of

the CPU clock frequency, as determined by the SMOD1 bit in PCON.

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8.18.4 Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit

(logical ‘0’), 8 data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit

(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.

The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or

the Baud Rate Generator (described in section Section 8.18.5 “Baud rate generator

and selection”).

8.18.5 Baud rate generator and selection

The P89LPC903 enhanced UART has an independent Baud Rate Generator. The

baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0

SFRs which together form a 16-bit baud rate divisor value that works in a similar

manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other

timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 18).

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses CCLK.

SMOD1 = 1

SBRGS = 0

SBRGS = 1

Timer 1 Overflow

(PCLK-based)

Baud Rate Modes 1 and 3

SMOD1 = 0

Baud Rate Generator

(CCLK-based)

002aaa419

Fig 18. Baud rate sources for UART (Modes 1, 3).

8.18.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0

(PCON.6) is ‘1’, framing errors can be made available in SCON.7, respectively. If

SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)

are set up when SMOD0 is ‘0’.

8.18.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the

device.

8.18.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to

be written to SBUF while the ﬁrst character is being transmitted. Double buffering

allows transmission of a string of characters with only one stop bit between any two

characters, as long as the next character is written between the start bit and the stop

bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART

is compatible with the conventional 80C51 UART. If enabled, the UART allows writing

to SnBUF while the previous data is being shifted out. Double buffering is only

allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be

disabled (DBMOD = ‘0’).

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8.18.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated

when the double buffer is ready to receive new data.

8.18.10 The 9^thbit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as

long as TB8 is updated some time before that bit is shifted out. TB8 must not be

changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8

will be double-buffered together with SBUF data.

8.19 Analog comparators

One analog comparator is provided on the P89LPC901. Two analog comparators are

provided on the P89LPC902 and P89LPC903 devices. Comparator operation is such

that the output is a logical one (which may be read in a register) when the positive

input is greater than the negative input (selectable from a pin or an internal reference

voltage). Otherwise the output is a zero. The comparator may be conﬁgured to cause

an interrupt when the output value changes.

The connections to the comparator are shown in Figure 19. Note: Not all possible

comparator conﬁgurations are available on all three devices. Please refer to the Logic

diagrams in Section 6 “Logic symbols” on page 12. The comparator functions to

_DD= 2.4 V.

When the comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10 microseconds. The comparator interrupt should not be

enabled during that time, and the comparator interrupt ﬂag must be cleared before

the interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COx, goes HIGH. If the

comparator output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFx.

This will cause an interrupt if the comparator interrupt is enabled. The user should

therefore disable the comparator interrupt prior to disabling the comparator.

Additionally, the user should clear the comparator ﬂag, CMFx, after disabling the

comparator.

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Comparator 1

OE1

(P0.4) CIN1A

CO1

Change Detect

CMP1 (P0.6)

(P0.5) CMPREF

REF

CMF1

CMF2

CN1

Interrupt

Change Detect

Comparator 2

(P0.2) CIN2A

CMP2 (P0.0)

CO2

OE2

002aaa453

CN2

Fig 19. Comparator input and output connections.

8.20 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to

as V_REF, is 1.23 V ±10%.

8.21 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag

is set whenever the comparator output changes state. The ﬂag may be polled by

software or may be used to generate an interrupt.

8.22 Comparator and power reduction modes

The comparators may remain enabled when Power-down or Idle mode is activated,

but the comparators are disabled automatically in Total Power-down mode.

If the comparator interrupt is enabled (except in Total Power-down mode), a change

of the comparator output state will generate an interrupt and wake up the processor. If

the comparator output to a pin is enabled, the pin should be conﬁgured in the

push-pull mode in order to obtain fast switching times while in Power-down mode.

The reason is that with the oscillator stopped, the temporary strong pull-up that

normally occurs during switching on a quasi-bidirectional port pin does not take

place.

The comparator consumes power in Power-down and Idle modes, as well as in the

normal operating mode. This fact should be taken into account when system power

consumption is an issue. To minimize power consumption, the user can disable the

comparator via PCONA.5 or put the device in Total Power-down mode.

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8.23 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can

be used for bus address recognition or keypad recognition. The user can conﬁgure

the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)

is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad

Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when

the condition is matched while the Keypad Interrupt function is active. An interrupt will

be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register

(KBCON) is used to deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x

series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then

any key connected to Port 0 which is enabled by the KBMASK register will cause the

hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt

may be used to wake up the CPU from Idle or Power-down modes. This feature is

particularly useful in handheld, battery powered systems that need to carefully

manage power consumption yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held

longer than six CCLKs.

8.24 Watchdog timer

The Watchdog timer causes a system reset when it underﬂows as a result of a failure

to feed the timer prior to the timer reaching its terminal count. It consists of a

programmable 12-bit prescaler, and an 8-bit down counter. The down counter is

decremented by a tap taken from the prescaler. The clock source for the prescaler is

either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer

can only be reset by a power-on reset. When the Watchdog feature is disabled, it can

be used as an interval timer and may generate an interrupt. Figure 20 shows the

Watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte

sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,

the watchdog is disabled. The Watchdog timer has a time-out period that ranges from

a few µs to a few seconds. Please refer to the P89LPC901/902/903 User’s Manual for

more details.

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WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

Watchdog

oscillator

8-BIT DOWN

COUNTER

PRESCALER

÷32

RESET

see note (1)

PCLK

SHADOW

CONTROL REGISTER

FOR WDCON

PRE2

PRE1

PRE0

–

WDRUN WDTOF WDCLK

WDCON (A7H)

002aaa423

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 20. Watchdog timer in Watchdog mode (WDTE = ‘1’).

8.25 Additional features

8.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor

completely, as if an external reset or Watchdog reset had occurred. Care should be

taken when writing to AUXR1 to avoid accidental software resets.

8.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects

one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so

that the DPS bit may be toggled (thereby switching Data Pointers) simply by

incrementing the AUXR1 register, without the possibility of inadvertently altering other

bits in the register.

8.26 Flash program memory

8.26.1 General description

The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and

programming. The Flash can be erased, read, and written as bytes. The Sector and

Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The

Chip Erase operation will erase the entire program memory. In-Circuit Programming

using standard commercial programmers is available. In addition, In-Application

Programming (IAP) and byte erase allows code memory to be used for non-volatile

data storage. On-chip erase and write timing generation contribute to a user-friendly

programming interface. The P89LPC901/902/903 Flash reliably stores memory

contents even after more than 100,000 erase and program cycles. The cell is

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designed to optimize the erase and programming mechanisms. The

P89LPC901/902/903 uses V_DDas the supply voltage to perform the Program/Erase

algorithms.

8.26.2 Features

• Programming and erase over the full operating voltage range.

• Byte-erase allowing code memory to be used for data storage.

• Read/Programming/Erase using ICP.

• Any ﬂash program/erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the Flash for each sector.

• More than 100,000 minimum erase/program cycles for each byte.

• 10-year minimum data retention.

8.26.3 Flash organization

The P89LPC901/902/903 program memory consists of four 256 byte sectors. Each

sector can be further divided into 16-byte pages. In addition to sector erase, page

erase, and byte erase, a 16-byte page register is included which allows from 1 to 16

bytes of a given page to be programmed at the same time, substantially reducing

overall programming time. In addition, erasing and reprogramming of

user-programmable conﬁguration bytes including UCFG1, the Boot Status Bit, and

the Boot Vector is supported.

8.26.4 Flash programming and erasing

Different methods of erasing or programming of the Flash are available. The Flash

may be programmed or erased in the end-user application (IAP) under control of the

application’s ﬁrmware. Another option is to use the In-Circuit Programming (ICP)

mechanism. This ICP system provides for programming through a serial clock- serial

data interface. Third, the Flash may be programmed or erased using a commercially

available EPROM programmer which supports this device. This device does not

provide for direct veriﬁcation of code memory contents. Instead this device provides a

32-bit CRC result on either a sector or the entire 1 KB of user code space.

8.26.5 In-circuit programming (ICP)

In-Circuit Programming is performed without removing the microcontroller from the

system. The In-Circuit Programming facility consists of internal hardware resources

to facilitate remote programming of the P89LPC901/902/903 through a two-wire

serial interface. The Philips In-Circuit Programming facility has made in-circuit

programming in an embedded application, using commercially available

programmers, possible with a minimum of additional expense in components and

circuit board area. The ICP function uses ﬁve pins. Only a small connector needs to

be available to interface your application to a commercial programmer in order to use

this feature. Additional details may be found in the P89LPC901/902/903 User’s

Manual.

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8.26.6 In-application programming

In-Application Programming is performed in the application under the control of the

microcontroller’s ﬁrmware. The IAP facility consists of internal hardware resources to

facilitate programming and erasing. The Philips In-Application Programming has

made in-application programming in an embedded application possible without

additional components. This is accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional

details may be found in the P89LPC901/902/903 User’s Manual.

8.26.7 Using ﬂash as data storage

The Flash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a

MOVC instruction is not allowed to read code memory contents of a secured sector).

Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.26.8 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC901/902/903 must be deﬁned at

power-up and therefore cannot be set by the program after start of execution. These

features are conﬁgured through the use of the Flash byte UCFG1. Please see the

P89LPC901/902/903 User’s Manual for additional details.

8.26.9 User sector security bytes

There are four User Sector Security Bytes, each corresponding to one sector. Please

see the P89LPC901/902/903 User’s Manual for additional details.

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9. Limiting values

Table 12: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

−55

−65

Max

Unit

°C

operating bias ambient temperature

storage temperature range

+125

+150

V_xtal

voltage on XTAL1, XTAL2 pin to V_SS

V_DD+ 0.5

as applicable

V_n

voltage on any other pin to V_SS

−0.5

+5.5

I_OH(I/O)

I_OL(I/O)

HIGH-level output current per I/O pin

LOW-level output current per I/O pin

I_{I/O(tot)(max)}maximum total I/O current

120

1.5

P_tot(pack)

total power dissipation per package

based on package heat

transfer, not device power

consumption

[1] The following applies to Limiting values:

a) Stresses above those listed under Table 12 may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any conditions other than those described in Table 13 “DC electrical characteristics”, Table 14 “AC

characteristics” and Table 15 “AC characteristics (P89LPC901)” of this speciﬁcation are not implied.

b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

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10. Static characteristics

Table 13: DC electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[2]

[3]

I_DD(oper)

power supply current,

operating (P89LPC901)

3.6 V; 12 MHz

3.6 V; 18 MHz

3.6 V; 12 MHz

3.6 V; 18 MHz

3.6 V; 7.373 MHz

I_DD(idle)

power supply current, Idle

mode (P89LPC901)

1.5

5.6

I_DD(oper)

power supply current,

operating (P89LPC902,

P89LPC903)

[3]

[2][3]

I_DD(idle)

I_DD(PD)

I_DD(TPD)

power supply current, Idle

mode (P89LPC902,

P89LPC903)

3.6 V; 7.373 MHz

3.6 V

µA

power supply current,

Power-down mode, voltage

comparators powered-down

power supply current, total

Power-down mode

3.6 V

(dV_DD/dt)_rV_DDrise rate

(dV_DD/dt)_fV_DDfall rate

mV/µs

0.2

mV/µs

V_POR

V_RAM

V_th(HL)

Power-on reset detect voltage

RAM keep-alive voltage

1.5

negative-going threshold

0.22V_DD

0.4V_DD

voltage (Schmitt trigger input)

V_th(LH)

positive-going threshold

0.6V_DD

0.7V_DD

voltage (Schmitt trigger input)

V_hys

V_OL

hysteresis voltage

0.2V_DD

0.6

0.3

0.2

LOW-level output voltage; all I_OL= 20 mA

ports, all modes except Hi-Z

1.0

0.5

0.3

I_OL= 10 mA

I_OL= 3.2 mA

V_OH

HIGH-level output voltage, all I_OH= −8 mA;

ports

_DD− 1.0

_DD− 0.7

_DD− 0.3

push-pull mode

_OH= −3.2 mA;

push-pull mode

_OH= −20 µA;

_DD− 0.4

_DD− 0.2

quasi-bidirectional

mode

[4]

[5]

C_ig

I_IL

input/output pin capacitance

logical 0 input current,

all ports

V_IN= 0.4 V

−80

µA

[6]

I_LI

input leakage current, all ports V_IN= V_ILor V_IH

±10

µA

[7][8]

I_TL

logical 1-to-0 transition

current, all ports

V_IN= 2.0 V at

V_DD= 3.6 V

−30

−450

R_RST

internal reset pull-up resistor

kΩ

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Table 13: DC electrical characteristics…continued

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_BO

brownout trip voltage with

BOV = ‘1’, BOPD = ‘0’

2.4 V < V_DD< 3.6 V

2.40

2.70

V_REF

bandgap reference voltage

1.11

1.23

1.34

TC_(VREF)

bandgap temperature

coefﬁcient

ppm/

°C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The I_DD(oper), I_PD(idle)speciﬁcations are measured using an external clock with the following functions disabled: comparators, brownout

detect, and Watchdog timer (P89LPC901).

[3] The I_DD(oper), I_PD(idle)speciﬁcations are measured with the following functions disabled: comparators, brownout detect, and Watchdog

timer (P89LPC902, P89LPC903).

[4] Pin capacitance is characterized but not tested.

[5] Measured with port in quasi-bidirectional mode.

[6] Measured with port in high-impedance mode.

[7] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups)

[8] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest

when V_INis approximately 2 V.

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11. Dynamic characteristics

Table 14: AC characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz

Unit

Min

Max

Min

Max

f_RCOSC

internal RC oscillator frequency

(nominal f = 7.3728 MHz) trimmed

to ± 1% at T_amb= 25 °C

7.189

7.557

7.189

7.557

MHz

f_WDOSC

internal Watchdog oscillator

320

520

320

520

kHz

frequency (nominal f = 400 kHz)

Crystal oscillator (P89LPC901)

f_osc

oscillator frequency

clock cycle

MHz

t_CLCL

see Figure 22

f_CLKP

CLKLP active frequency

MHz

Glitch ﬁlter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except

P1.5/RST

signal acceptance, any pin except

P1.5/RST

External clock (P89LPC901)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

HIGH time

LOW time

rise time

fall time

see Figure 22

_CLCL− t_CLCX

t_CLCL− t_CHCX33

Shift register (UART mode 0 - P89LPC903)

t_XLXL

serial port clock cycle time

see Figure 21

16 t_CLCL

13 t_CLCL

1333

1083

t_QVXH

output data set-up to clock rising

edge

t_XHQX

t_XHDX

t_DVXH

output data hold after clock rising see Figure 21

edge

t_CLCL+ 20

103

input data hold after clock rising

edge

see Figure 21

input data valid to clock rising edge see Figure 21

150

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

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Table 15: AC characteristics (P89LPC901)

V_DD= 3.0V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz

Unit

Min

Max

Min

Max

f_RCOSC

internal RC oscillator frequency

(nominal f = 7.3728 MHz) trimmed

to ± 1% at T_amb= 25 °C

7.189

7.557

7.189

7.557

MHz

f_WDOSC

internal Watchdog oscillator

320

520

320

520

kHz

frequency (nominal f = 400 kHz)

Crystal oscillator

[2]

f_osc

oscillator frequency

MHz

t_CLCL

clock cycle

see Figure 22

f_CLKP

CLKLP active frequency

MHz

Glitch ﬁlter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except

P1.5/RST

signal acceptance, any pin except

P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

HIGH time

see Figure 22

_CLCL− t_CLCX

LOW time

rise time

fall time

t_CLCL− t_CHCX22

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2] When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until V_DDhas reached its speciﬁed level. When system power is removed V_DDwill fall below the

minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout

detect circuit may be required to hold the device in reset when V_DDfalls below the minimum speciﬁed operating voltage.

XLXL

Clock

XHQX

QVXH

Output Data

Write to SBUF

Input Data

Clear RI

XHDX

Set TI

Valid

XHDV

Valid

Set RI

002aaa425

Fig 21. Shift register mode timing.

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- 0.5 V

0.45 V

0.2 V

+ 0.9

- 0.1 V

0.2 V

CHCX

CLCX

CHCL

CLCH

002aaa416

Fig 22. External clock timing.

12. Comparator electrical characteristics

Table 16: Comparator electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

V_IO

Parameter

Conditions

Min

Typ

Max

Unit

offset voltage comparator inputs

common mode range comparator inputs

common mode rejection ratio

response time

±20

V_CR

V_DD− 0.3

[1]

CMRR

−50

500

250

comparator enable to output valid

input leakage current, comparator

µs

I_IL

0 < V_IN< V_DD

±10

µA

[1] This parameter is characterized, but not tested in production.

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13. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

(2)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 23. SOT96-1 (SO8).

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DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-1

w M

(e )

pin 1 index

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

min.

max.

1.73

1.14

0.53

0.38

1.07

0.89

0.36

0.23

9.8

9.2

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

1.15

0.068 0.021 0.042 0.014

0.045 0.015 0.035 0.009

0.39

0.36

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.045

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT97-1

050G01

MO-001

SC-504-8

Fig 24. SOT97-1 (DIP8).

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14. Revision history

Table 17: Revision history

Rev Date

CPCN

Description

05 20041217

Product data (9397 750 14465)

Modiﬁcations:

• Added 18 MHz information.

04 20031121

03 20030929

02 20030731

01 20030602

Product data (9397 750 12293); ECN 853-2434 01-A14555 of 18 November 2003

Product data (9397 750 12031); ECN 853-2434 30348 of 11 September 2003

Product data (9397 750 11801); ECN 853-2434 30152 of 28 July 2003

Preliminary data (9397 750 11494)

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15. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Deﬁnitions

17. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

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Contents

General description. . . . . . . . . . . . . . . . . . . . . . . . . . . 1

8.16.6

8.17

8.18

Timer overﬂow toggle output (P89LPC901) . . . . . . . 35

Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 35

UART (P89LPC903) . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Baud rate generator and selection . . . . . . . . . . . . . . 36

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Transmit interrupts with double buffering

enabled (Modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . 37

The 9^thbit (bit 8) in double buffering (Modes 1, 2 and

3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 37

Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 38

Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 38

Comparator and power reduction modes . . . . . . . . . 38

Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 39

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 40

General description. . . . . . . . . . . . . . . . . . . . . . . . . . 40

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Flash organization . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Flash programming and erasing . . . . . . . . . . . . . . . . 41

In-circuit programming (ICP). . . . . . . . . . . . . . . . . . . 41

In-application programming . . . . . . . . . . . . . . . . . . . 42

Using ﬂash as data storage . . . . . . . . . . . . . . . . . . . 42

User conﬁguration bytes . . . . . . . . . . . . . . . . . . . . . . 42

User sector security bytes . . . . . . . . . . . . . . . . . . . . 42

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1

2.2

8.18.1

8.18.2

8.18.3

8.18.4

8.18.5

8.18.6

8.18.7

8.18.8

8.18.9

Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.1

Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1

5.2

Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Special function registers. . . . . . . . . . . . . . . . . . . . . 14

8.18.10

Functional description . . . . . . . . . . . . . . . . . . . . . . . 24

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clock deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 24

Low speed oscillator option (P89LPC901). . . . . . . . 24

Medium speed oscillator option (P89LPC901). . . . . 24

High speed oscillator option (P89LPC901) . . . . . . . 25

Clock output (P89LPC901) . . . . . . . . . . . . . . . . . . . 25

On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 25

Watchdog oscillator option. . . . . . . . . . . . . . . . . . . . 25

External clock input option (P89LPC901) . . . . . . . . 25

CPU CLock (CCLK) wake-up delay . . . . . . . . . . . . . 27

CPU CLOCK (CCLK) modiﬁcation: DIVM register. . 27

Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 27

Data RAM arrangement . . . . . . . . . . . . . . . . . . . . . . 27

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

External interrupt inputs. . . . . . . . . . . . . . . . . . . . . . 28

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Quasi-bidirectional output conﬁguration. . . . . . . . . . 31

Open-drain output conﬁguration. . . . . . . . . . . . . . . . 31

Input-only conﬁguration . . . . . . . . . . . . . . . . . . . . . . 31

Push-pull output conﬁguration . . . . . . . . . . . . . . . . . 31

Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 31

Additional port features . . . . . . . . . . . . . . . . . . . . . . 32

Power monitoring functions . . . . . . . . . . . . . . . . . . . 32

Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 32

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Total Power-down mode. . . . . . . . . . . . . . . . . . . . . . 33

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 34

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 6 (P89LPC901) . . . . . . . . . . . . . . . . . . . . . . . 34

8.1

8.2

8.19

8.20

8.21

8.22

8.23

8.24

8.25

8.25.1

8.25.2

8.26

8.26.1

8.26.2

8.26.3

8.26.4

8.26.5

8.26.6

8.26.7

8.26.8

8.26.9

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

8.11

8.11.1

8.12

8.12.1

8.12.2

8.12.3

8.12.4

8.12.5

8.12.6

8.12.7

8.13

8.13.1

8.13.2

8.14

8.14.1

8.14.2

8.14.3

8.15

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 44

Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 46

Comparator electrical characteristics . . . . . . . . . . . 48

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.16

8.16.1

8.16.2

8.16.3

8.16.4

8.16.5

Printed in the U.S.A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 17 December 2004

Document order number: 9397 750 14465

935273905112 [NXP]

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