935278461015 [NXP]
LIQUID CRYSTAL DISPLAY DRIVER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, SOT-357-1, MS-026, QFP-64;
| 型号： | 935278461015 |
| 厂家： | 
NXP |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, SOT-357-1, MS-026, QFP-64 驱动 |
| 文件： | 总40页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8576D
Universal LCD driver
for low multiplex rates
Product specification
2003 Jun 23
Supersedes data of 2003 Apr 01
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
CONTENTS
8
LIMITING VALUES
HANDLING
9
1
2
3
4
5
6
FEATURES
10
11
12
13
14
15
16
16.1
DC CHARACTERISTICS
AC CHARACTERISTICS
BONDING PAD INFORMATION
DEVICE PROTECTION
TRAY INFORMATION
PACKAGE OUTLINE
SOLDERING
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
6.4
Power-on reset
LCD bias generator
LCD voltage selector
LCD drive mode waveforms
Oscillator
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
6.5
16.2
16.3
16.4
16.5
6.6
Timing
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
Display register
Segment outputs
Backplane outputs
Display RAM
Suitability of surface mount IC packages for
wave and reflow soldering methods
17
18
19
20
DATA SHEET STATUS
DEFINITIONS
Data pointer
Subaddress counter
Output bank selector
Input bank selector
Blinker
DISCLAIMERS
PURCHASE OF PHILIPS I2C COMPONENTS
7
CHARACTERISTICS OF THE I2C-BUS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Bit transfer
Start and stop conditions
System configuration
Acknowledge
PCF8576D I2C-bus controller
Input filters
I2C-bus protocol
Command decoder
Display controller
Cascaded operation
2003 Jun 23
2
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
1
FEATURES
• Single-chip LCD controller/driver
• Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing
• Selectable display bias configuration: static, 1/2 and 1/3
• Compatible with 4, 8 or 16-bit microprocessors or
microcontrollers
• Internal LCD bias generation with voltage-follower
buffers
• May be cascaded for large LCD applications (up to
2560 elements possible)
• 40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements
• No external components
• 40 × 4-bit RAM for display data storage
• Compatible with chip-on-glass technology
• Manufactured in silicon gate CMOS process.
• Auto-incremented display data loading across device
subaddress boundaries
• Display memory bank switching in static and duplex
drive modes
2
GENERAL DESCRIPTION
The PCF8576D is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576D is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
• Versatile blinking modes
• Independent supplies possible for LCD and logic
voltages
• Wide power supply range: from 1.8 to 5.5 V
• Wide logic LCD supply range: from 2.5 V for
low-threshold LCDs and up to 6.5 V for guest-host LCDs
and high-threshold (automobile) twisted nematic LCDs
• Low power consumption
• 400 kHz I2C-bus interface
• TTL/CMOS compatible
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF8576DH
TQFP64
plastic thin quad flat package, 64 leads; body; 10 × 10 × 1.0 mm
SOT357-1
PCF8576DU
−
−
chips in tray
−
−
PCF8576DU/2
chip with bumps in tray
2003 Jun 23
3
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BP0 BP2 BP1 BP3
25 26 27 28
S0 to S39
29 to 32, 34 to 47,
49 to 64, 2 to 7
21
V
BACKPLANE
OUTPUTS
LCD
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD
VOLTAGE
SELECTOR
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROLLER
LCD BIAS
GENERATOR
20
V
SS
DISPLAY
RAM
40 × 4 BIT
PCF8576DH
13
CLK
BLINKER
TIMEBASE
CLOCK SELECT
AND TIMING
12
SYNC
15
COMMAND
DECODER
DATA POINTER AND
AUTO INCREMENT
WRITE DATA
CONTROL
POWER-ON
RESET
OSC
OSCILLATOR
14
11
10
V
DD
SCL
SDA
2
INPUT
FILTERS
SUB-ADDRESS
COUNTER
I C-BUS
CONTROLLER
1, 8, 9, 22 to 24, 33, 48
16 17 18
19
MDB075
SA0
n.c.
A0 A1 A2
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
5
PINNING
SYMBOL
PIN
PAD
DESCRIPTION
PCF8576DH
PCF8576DU
SDA
10
11
13
14
12
1, 58 and 59
I2C-bus serial data input/output
I2C-bus serial clock input
external clock input/output
supply voltage
SCL
CLK
VDD
2 and 3
5
6
4
SYNC
cascade synchronization
input/output
OSC
15
16 to 18
19
7
8 to 10
11
internal oscillator enable input
subaddress inputs
I2C-bus slave address input; bit 0
A0 to A2
SA0
VSS
20
12
logic ground
VLCD
21
13
LCD supply voltage
BP0, BP2, BP1, BP3
S0 to S39
25 to 28
14 to 17
18 to 57
LCD backplane outputs
LCD segment outputs
29 to 32, 34 to 47,
49 to 64, 2 to 7
n.c.
1, 8, 9, 22 to 24, 33 and 48
−
not connected
2003 Jun 23
5
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
n.c.
S34
S35
S36
S37
S38
S39
n.c.
n.c.
1
2
3
4
5
6
7
8
9
48 n.c.
47 S17
46 S16
45 S15
44 S14
43 S13
42 S12
41 S11
40 S10
39 S9
38 S8
37 S7
36 S6
35 S5
34 S4
33 n.c.
PCF8576DH
SDA 10
SCL 11
12
SYNC
CLK 13
V
14
DD
OSC 15
A0 16
MDB073
Fig.2 Pin configuration (TQFP64).
2003 Jun 23
6
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
6
FUNCTIONAL DESCRIPTION
The host microprocessor/microcontroller maintains the
2-line I2C-bus communication channel with the
PCF8576D. The internal oscillator is enabled by
connecting pin OSC to pin VSS. The appropriate biasing
voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required
to complete the system are to the power supplies (VDD
VSS and VLCD) and the LCD panel chosen for the
application.
The PCF8576D is a versatile peripheral device designed
to interface any microprocessor/microcontroller with a
wide variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments.
,
The display configurations possible with the PCF8576D
depend on the number of active backplane outputs
required. A selection of display configurations is shown in
Table 1; all of these configurations can be implemented in
the typical system shown in Fig.3.
Table 1 Selection of display configurations
14-SEGMENTS
ALPHANUMERIC
NUMBER OF
7-SEGMENTS NUMERIC
DOT MATRIX
INDICATOR
SYMBOLS
INDICATOR
SYMBOLS
BACKPLANES SEGMENTS
DIGITS
CHARACTERS
4
3
2
1
160
120
80
20
15
10
5
20
15
10
5
10
8
20
8
160 dots (4 × 40)
120 dots (3 × 40)
80 dots (2 × 40)
40 dots (1 × 40)
5
10
12
40
2
V
DD
t
r
R ≤
2C
B
V
V
DD
LCD
6
13
SDA
SCL
OSC
HOST
MICRO-
PROCESSOR/
MICRO-
1, 58, 59
40 segment drives
4 backplanes
LCD PANEL
2, 3
PCF8576D
(up to 160
elements)
CONTROLLER
7
8
9
10 11 12
MDB079
A0 A1 A2 SA0
V
SS
V
SS
The resistance of the power supply lines must be kept to a minimum.
For chip-on-glass applications, due to Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately
between the chip and the connector.
Fig.3 Typical system configuration.
2003 Jun 23
7
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
6.1
Power-on reset
1
Bias is calculated by the formula
------------
1 + a
At power-on the PCF8576D resets to the following starting
conditions:
For 1⁄2bias, a = 1; for 1⁄3bias, a = 2.
• All backplane outputs are set to VLCD
• All segment outputs are set to VLCD
• Drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected
• Blinking is switched off
The LCD on voltage Von is calculated by the formula
2
1
1
---
N
+ (N – 1)
------------
1 + a
V op
------------------------------------------------------------
N
• Input and output bank selectors are reset (as defined in
Table 4)
The LCD off voltage Voff is calculated by the formula
• The I2C-bus interface is initialized
a2 – (2a + N)
N (1 + a)2
V op
----------------------------------
• The data pointer and the subaddress counter are
cleared
where Vop is the resultant voltage at the LCD segment; N
is the LCD drive mode: 1 = static, 2 = 1 : 2, 3 = 1 : 3,
4 = 1 : 4.
• Display is disabled.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
Discrimination is the ratio of Von to Voff, and is determined
(a + 1)2 + (N – 1)
(a – 1)2 + (N – 1)
6.2
LCD bias generator
Von
by the formula
=
--------------------------------------------
---------
Voff
Fractional LCD biasing voltages are obtained from an
internal voltage divider comprising three resistors
connected in series between VLCD and VSS. The middle
resistor can be bypassed to provide a 1⁄2bias voltage level
for the 1 : 2 multiplex configuration. The LCD voltage can
be temperature compensated externally via the supply to
Using the above formula, the discrimination for an LCD
drive mode of 1 : 3 with 1⁄2bias is 3 = 1.732, and the
discrimination for an LCD drive mode of 1 : 4 with 1⁄2bias is
21
pin VLCD
.
= 1.528.
----------
3
6.3 LCD voltage selector
The advantage of these LCD drive modes is a reduction of
the LCD full-scale voltage VLCD as follows:
The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of VLCD and the resulting
Discrimination ratios (D), are given in Table 2.
1 : 3 multiplex (1⁄2bias):
VLCD
=
6 × Voff(rms) = 2.449 Voff(rms)
1 : 4 multiplex (1⁄2bias):
(4 × 3)
= 2.309 Voff(rms)
VLCD
=
---------------------
3
A practical value for VLCD is determined by equating
Voff(rms) with a defined LCD threshold voltage (Vth),
typically when the LCD exhibits approximately 10%
contrast. In the static drive mode a suitable choice is
VLCD > 3Vth.
These compare with VLCD = 3 Voff(rms) when 1⁄3bias is
used.
Multiplex drive modes of 1 : 3 and 1 : 4 with 1⁄2bias are
possible but the discrimination and hence the contrast
ratios are smaller.
2003 Jun 23
8
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
Table 2 Preferred LCD drive modes: summary of characteristics
NUMBER OF
Voff(rms)
V on(rms)
V on(rms)
LCD BIAS
CONFIGURATION
D =
--------------------
Vlcd
--------------------
Vlcd
--------------------
Voff(rms)
LCD DRIVE MODE
static
BACKPLANES LEVELS
1
2
2
3
4
2
3
4
4
4
static
0
1
∞
1
1 : 2 multiplex
1 : 2 multiplex
1 : 3 multiplex
1 : 4 multiplex
⁄
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
2
1
⁄
3
1
⁄
3
1
⁄
3
6.4
LCD drive mode waveforms
6.4.1
STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment
drive (Sn) waveforms for this mode are shown in Fig.4.
T
frame
LCD segments
V
LCD
BP0
V
SS
state 1
(on)
state 2
(off)
V
LCD
S
n
V
SS
V
LCD
S
+ 1
n
V
SS
(a) Waveforms at driver.
V
LCD
0 V
state 1
−V
LCD
V
LCD
state 2
0 V
−V
LCD
Vstate1(t) = VS (t) – VBP0(t)
(b) Resultant waveforms
at LCD segment.
n
MGL745
Von(rms) = VLCD
Vstate2(t) = VS (t) – VBP0(t)
n + 1
Voff(rms) = 0 V
Fig.4 Static drive mode waveforms.
9
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
6.4.2
1 : 2 MULTIPLEX DRIVE MODE
The 1 : 2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD
bias voltages of 1⁄2bias or 1⁄3bias as shown in Figs 5 and 6.
T
frame
V
LCD
/2
LCD segments
V
V
BP0
BP1
LCD
SS
state 1
V
LCD
/2
state 2
V
V
LCD
SS
V
LCD
S
n
V
SS
V
LCD
S
+ 1
n
V
SS
(a) Waveforms at driver.
V
LCD
V
/2
LCD
0 V
state 1
−V
/2
LCD
−V
LCD
V
LCD
/2
V
LCD
0 V
state 2
−V
/2
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
MGL746
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.791VLCD
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.354VLCD
Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2bias.
2003 Jun 23
10
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
T
frame
V
LCD
2V
LCD segments
/3
LCD
BP0
V
V
/3
LCD
SS
state 1
V
LCD
state 2
2V
V
/3
LCD
/3
BP1
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
+ 1
n
/3
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
/3
/3
LCD
/3
V
LCD
state 1
0 V
−V
LCD
−2V
/3
LCD
−V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
/3
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
MGL747
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.745VLCD
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.333VLCD
Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3bias.
2003 Jun 23
11
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
6.4.3
1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies (see Fig.7).
T
frame
V
LCD
LCD segments
2V
V
/3
LCD
/3
BP0
BP1
BP2
LCD
V
SS
state 1
state 2
V
LCD
2V
V
/3
LCD
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
+ 1
+ 2
n
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
/3
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
V
/3
/3
LCD
/3
LCD
state 1
0 V
−V
LCD
−2V
/3
LCD
−V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
MGL748
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.638VLCD
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.333VLCD
Fig.7 Waveforms for the 1 : 3 multiplex drive mode.
12
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
6.4.4
1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies (see Fig.8).
T
frame
V
LCD segments
LCD
2V
V
/3
LCD
BP0
BP1
BP2
BP3
/3
LCD
V
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
/3
LCD
V
SS
V
LCD
2V
/3
LCD
V
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
n
/3
LCD
V
SS
V
LCD
2V
/3
LCD
S
+ 1
n
V
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
S
+ 2
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
+ 3
n
/3
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
V
/3
/3
LCD
/3
LCD
state 1
0 V
−V
LCD
−2V
/3
LCD
−V
Vstate1(t) = VS (t) – VBP0(t)
LCD
n
V
LCD
Von(rms) = 0.577VLCD
2V
/3
LCD
Vstate2(t) = VS (t) – VBP1(t)
V
/3
LCD
0 V
−V
n
state 2
Voff(rms) = 0.333VLCD
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
MGL749
Fig.8 Waveforms for the 1 : 4 multiplex drive mode.
13
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
6.5
Oscillator
6.9
Backplane outputs
6.5.1
INTERNAL CLOCK
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required, the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode,
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode, BP0
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
The internal logic of the PCF8576D and its LCD drive
signals are timed either by its internal oscillator or by an
external clock. The internal oscillator is enabled by
connecting pin OSC to pin VSS. If the internal oscillator is
used, the output from pin CLK can be used as the clock
signal for several PCF8576Ds in the system that are
connected in cascade. After power-up, pin SDA must be
HIGH to guarantee that the clock starts.
6.5.2
Pin CLK is enabled as an external clock input by
connecting pin OSC to VDD
EXTERNAL CLOCK
.
The LCD frame signal frequency is determined by the
clock frequency (fCLK).
6.10 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the
on-state of the corresponding LCD segment; similarly, a
logic 0 indicates the off-state. There is a one-to-one
correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.9). In multiplexed LCD
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6
Timing
The PCF8576D timing controls the internal data flow of the
device. This includes the transfer of display data from the
display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each
PCF8576D in the system is maintained by the
synchronization signal at pin SYNC. The timing also
generates the LCD frame signal whose frequency is
derived from the clock frequency. The frame signal
frequency is a fixed division integer of the clock frequency
(nominally 64 kHz) from either the internal or an external
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8576D, the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode. The data is
stored as it arrives and does not wait for an acknowledge
cycle as with the commands. Depending on the current
multiplex drive mode, data is stored singularly, in pairs,
triplets or quadruplets. For example, in the 1 : 2 mode, the
RAM data is stored every second bit. To illustrate the filling
order, an example of a 7-segment numeric display
clock.
fCLK
----------
24
Frame frequency =
6.7
Display register
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and each column of the
display RAM.
showing all drive modes is given in Fig.10; the RAM filling
organization depicted applies equally to other LCD types.
With reference to Fig.10, in the static drive mode, the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 mode, the eight
transmitted data bits are placed in bits 0 and 1 of four
successive display RAM addresses. In the 1 : 3 mode,
these bits are placed in bits 0, 1 and 2 of three successive
addresses, with bit 2 of the third address left unchanged.
This last bit may, if necessary, be controlled by an
additional transfer to this address but care should be taken
to avoid overriding adjacent data because full bytes are
always transmitted.
6.8
Segment outputs
The LCD drive section includes 40 segment outputs
S0 to S39 which should be connected directly to the LCD.
The segment output signals are generated in accordance
with the multiplexed backplane signals and with data
residing in the display latch. When less than 40 segment
outputs are required, the unused segment outputs should
be left open-circuit.
2003 Jun 23
14
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
In the 1 : 4 mode, the eight transmitted data bits are
placed in bits 0, 1, 2 and 3 of two successive display RAM
addresses.
arriving data byte is stored at the display RAM address
indicated by the data pointer in accordance with the filling
order shown in Fig.10. After each byte is stored, the
contents of the data pointer are automatically incremented
by a value dependent on the selected LCD drive mode:
eight (static drive mode), four (1 : 2 mode), three
(1 : 3 mode) or two (1 : 4 mode). If an I2C-bus data access
is terminated early then the state of the data pointer will be
unknown. The data pointer should be re-written prior to
further RAM accesses.
6.11 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
display RAM addresses (rows) / segment outputs (S)
0
1
2
3
4
35 36 37 38 39
0
1
2
3
display RAM bits
(columns) /
backplane outputs
(BP)
MBE525
Fig.9 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
6.12 Subaddress counter
6.13 Output bank selector
The storage of display data is determined by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to A0, A1
and A2. The subaddress counter value is defined by the
DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place. The
subaddress counter is also incremented when the data
pointer overflows.
The output bank selector selects one of the four bits per
display RAM address for transfer to the display latch. The
actual bit chosen depends on the selected LCD drive
mode and on the instant in the multiplex sequence. In 1 : 4
mode, all RAM addresses of bit 0 are selected, these are
followed by the contents of bit 1, bit 2 and then bit 3.
Similarly in 1 : 3 mode, bits 0, 1 and 2 are selected
sequentially. In 1 : 2 mode, bits 0 and 1 are selected and,
in static mode, bit 0 is selected. Signal SYNC will reset
these sequences to the following starting points; bit 3 for
1 : 4 mode, bit 2 for 1 : 3 mode, bit 1 for 1 : 2 mode and
bit 0 for static mode.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576D occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 mode).
The PCF8576D includes a RAM bank switching feature in
the static and 1 : 2 drive modes. In the static drive mode,
the BANK SELECT command may request the contents of
bit 2 to be selected for display instead of the contents of
bit 0. In 1 : 2 mode, the contents of bits 2 and 3 may be
selected instead of bits 0 and 1. This allows display
information to be prepared in an alternative bank and then
selected for display when it is assembled.
The hardware subaddress should not be changed whilst
the device is being accessed on the I2C-bus interface.
2003 Jun 23
15
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
6.14 Input bank selector
An additional feature allows an arbitrary selection of LCD
segments to be blinked in the static and 1 : 2 drive modes.
This is implemented without any communication
overheads by the output bank selector which alternates
the displayed data between the data in the display RAM
bank and the data in an alternative RAM bank at the blink
frequency. This mode can also be implemented by the
BLINK command.
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. The BANK SELECT command can be used
to load display data in bit 2 in static drive mode or in
bits 2 and 3 in 1 : 2 mode. The input bank selector
functions are independent of the output bank selector.
6.15 Blinker
In the 1 : 3 and 1 : 4 drive modes, where no alternative
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
The PCF8576D has a very versatile display blinking
capability. The whole display can blink at a frequency
selected by the BLINK command. Each blink frequency is
a multiple integer value of the clock frequency; the ratio
between the clock frequency and blink frequency depends
on the blink mode selected, as shown in Table 3.
The entire display can be blinked at a frequency other than
the nominal blink frequency by sequentially resetting and
setting the display enable bit E at the required rate using
the MODE SET command.
Table 3 Blinking frequencies
NORMAL OPERATING MODE
RATIO
BLINK MODE
NOMINAL BLINK FREQUENCY
Off
−
blinking off
2 Hz
2 Hz
fCLK
----------
768
1 Hz
1 Hz
f CLK
------------
1536
0.5 Hz
0.5 Hz
f CLK
------------
3072
Note
1. Blink modes 0.5, 1 and 2 Hz, and nominal blink frequencies 0.5, 1 and 2 Hz correspond to an oscillator frequency
(fCLK) of 1536 Hz at pin CLK. The oscillator frequency range is given in Chapter 11.
2003 Jun 23
16
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drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
a
S
2
n
n
1
n
2
n
3
n
4
n
5
n
6
n 7
n
n
b
BP0
f
S
1
7
S
3
MSB
LSB
DP
n
n
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
bit/
BP
g
4
S
S
S
n
n
x
x
x
x
x
x
c
b
a
f
g e d
static
e
S
5
6
c
n
d
DP
S
n
BP0
S
n
a
n
n
n
n
1
1
1
n
2
n 3
b
b
b
1 : 2
f
S
1
n
MSB
LSB
DP
0
1
2
3
a
b
x
x
f
e
c
x
x
d
bit/
BP
g
g
x
x
DP
x
x
a
b
f
g
e c d
BP1
S
S
e
2
3
multiplex
n
n
c
c
c
d
d
d
DP
BP0
BP1
S
1
a
n
n
n 2
S
S
2
f
1 : 3
n
n
MSB
LSB
e
0
1
2
3
b
DP
c
a
d
g
x
f
bit/
BP
g
e
x
x
BP2
b DP
c
a
d
g
f
e
multiplex
x
DP
S
n
a
n
BP2
BP3
BP0
BP1
f
1 : 4
0
1
2
3
a
c
f
bit/
BP
MSB
LSB
d
g
e
g
d
b
DP
e
multiplex
a
c
b
DP
f
e
g
S
1
DP
n
MGL751
x = data bit unchanged.
Fig.10 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
CHARACTERISTICS OF THE I2C-BUS
acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end of
data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave.
In this event the transmitter must leave the data line HIGH
to enable the master to generate a STOP condition (see
Fig.14).
7
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
In chip-on-glass applications where the track resistance
from the SDA pad to the system SDA line can be
significant, a potential divider is generated by the bus
pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is therefore necessary to minimize the track
resistance from the SDA pad to the system SDA line to
guarantee a valid LOW-level during the acknowledge
cycle.
7.5
PCF8576D I2C-bus controller
The PCF8576D acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8576D
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
7.1
Bit transfer
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally tied to VSS which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
same hardware subaddress.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal (see Fig.11).
7.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P), (see Fig.12).
7.6
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.3
System configuration
7.7
I2C-bus protocol
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’, (see Fig.13).
Two I2C-bus slave addresses (01110000 and 01110010)
are reserved for the PCF8576D. The least significant bit of
the slave address that a PCF8576D will respond to is
defined by the level tied to its SA0 input. The PCF8576D
is a write-only device and will not respond to a read
access. Having two reserved slave addresses allows the
following on the same I2C-bus:
7.4
Acknowledge
The number of data bytes that can be transferred from
transmitter to receiver between the START and STOP
conditions is unlimited. Each byte of eight bits is followed
by an acknowledge bit. The acknowledge bit is a
HIGH-level signal on the bus that is asserted by the
transmitter during which time the master generates an
extra acknowledge related clock pulse. An addressed
slave receiver must generate an acknowledge after
receiving each byte. Also a master receiver must generate
an acknowledge after receiving each byte that has been
clocked out of the slave transmitter. The acknowledging
device must pull-down the SDA line during the
• Up to 16 PCF8576Ds for very large LCD applications
• The use of two types of LCD multiplex drive.
The I2C-bus protocol is shown in Fig.15. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of two possible
PCF8576D slave addresses available. All PCF8576Ds
whose SA0 inputs correspond to bit 0 of the slave address
respond by asserting an acknowledge in parallel. This
I2C-bus transfer is ignored by all PCF8576Ds whose SA0
inputs are set to the alternative level.
2003 Jun 23
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Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
After an acknowledgement, one or more command bytes
follow that define the status of each addressed
PCF8576D.
A1 and A2. After the last display byte, the I2C-bus master
asserts a STOP condition (P). Alternately a START may
be asserted to RESTART an I2C-bus access.
The last command byte sent is identified by resetting its
most significant bit, continuation bit C, (see Fig.16). The
command bytes are also acknowledged by all addressed
PCF8576Ds on the bus.
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. All available commands carry a
continuation bit C in their most significant bit position as
shown in Fig.16. When this bit is set, it indicates that the
next byte of the transfer to arrive will also represent a
command. If this bit is reset, it indicates that the command
byte is the last in the transfer. Further bytes will be
regarded as display data.
After the last command byte, one or more display data
bytes may follow. Display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data directed to the intended PCF8576D device.
The five commands available to the PCF8576D are
defined in Table 4.
An acknowledgement after each byte is asserted only by
the PCF8576Ds that are addressed via address lines A0,
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.11 Bit transfer.
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
MBC622
Fig.12 Definition of START and STOP conditions.
2003 Jun 23
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Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.13 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.14 Acknowledgement on the I2C-bus.
acknowledge
by A0, A1 and A2
selected
PCF8576D only
acknowledge by
all addressed
PCF8576Ds
k
R/W
0
slave address
S
A
0
0
1
1
1
0
0
A
C
COMMAND
A
DISPLAY DATA
A
P
S
1 byte
n ≥ 1 byte(s)
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
MDB078
Fig.15 I2C-bus protocol.
20
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
MSB
LSB
C
REST OF OPCODE
MSA833
C = 0 = last command.
C = 1 = commands continue.
Fig.16 Format of command byte.
Table 4 Definition of PCF8576D commands
COMMAND
OPCODE
OPTIONS
M1 M0 Table 5
DESCRIPTION
(1)
MODE SET
C
1
0
E
B
Defines LCD drive mode.
Table 6
Table 7
Defines LCD bias configuration.
Defines display status; the possibility to
disable the display allows implementation
of blinking under external control.
LOAD DATA
POINTER
C
C
C
0
1
1
P5 P4 P3 P2 P1 P0 Table 8
Six bits of immediate data, bits P5 to P0,
are transferred to the data pointer to
define one of forty display RAM
addresses.
DEVICE
SELECT
1
1
0
1
0
1
A2 A1 A0 Table 9
Three bits of immediate data, bits A0 to
A2, are transferred to the subaddress
counter to define one of eight hardware
subaddresses.
BANK
SELECT
0
I
O
Table 10
Table 11
Defines input bank selection (storage of
arriving display data).
Defines output bank selection (retrieval of
LCD display data); the BANK SELECT
command has no effect in 1 : 3 and 1 : 4
multiplex drive modes.
BLINK
C
1
1
1
0
A
BF1 BF0 Table 12
Table 13
Defines the blink frequency.
Selects the blink mode; normal operation
with frequency set by BF1, BF0 or blinking
by alternating display RAM banks;
alternating RAM bank blinking does not
apply in 1 : 3 and 1 : 4 multiplex drive
modes.
Note
1. Not used.
2003 Jun 23
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Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
Table 5 Mode set option 1
Table 12 Blink option 1
BLINK FREQUENCY
LCD DRIVE MODE
BITS
BITS
DRIVE
BF1
BF0
BACKPLANE
MODE
M1
M0
Off
0
0
1
1
0
1
0
1
Static
1 : 2
1 : 3
1 : 4
BP0
0
1
1
0
1
0
1
0
2 Hz
1 Hz
0.5 Hz
BP0, BP1
BP0, BP1, BP2
BP0, BP1, BP2, BP3
Table 13 Blink option 2
Table 6 Mode set option 2
BLINK MODE
BIT A
LCD BIAS
BIT B
Normal blinking
0
1
1⁄3bias
1⁄2bias
0
1
Alternate RAM bank blinking
Note
1. Normal blinking is assumed when LCD multiplex drive
modes 1 : 3 or 1 : 4 are selected.
Table 7 Mode set option 3
DISPLAY STATUS
BIT E
7.9
Display controller
Disabled (blank)
Enabled
0
1
The display controller executes the commands identified
by the command decoder. It contains the device’s status
registers and co-ordinates their effects. The display
controller is also responsible for loading display data into
the display RAM in the correct filling order.
Table 8 Load data pointer option 1
DESCRIPTION
BITS
6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0
7.10 Cascaded operation
Table 9 Device select option 1
In large display configurations, up to 16 PCF8576Ds can
be differentiated on the same I2C-bus by using the 3-bit
hardware subaddresses (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0). PCF8576Ds
connected in cascade are synchronized to allow the
backplane signals from only one device in the cascade to
be shared. This arrangement is cost-effective in large LCD
applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other cascaded PCF8576Ds
contribute additional segment outputs but their backplane
outputs are left open-circuit (see Fig.17).
DESCRIPTION
BITS
3 bit binary value of 0 to 7
A2
A1
A0
Table 10 Bank select option 1 (input)
MODE
BIT I
STATIC
RAM bit 0
RAM bit 2
1 : 2
RAM bits 0 and 1
RAM bits 2 and 3
0
1
Table 11 Bank select option 2 (output)
MODE
BIT O
STATIC
RAM bit 0
1 : 2
RAM bits 0 and 1
RAM bits 2 and 3
0
1
RAM bit 2
2003 Jun 23
22
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
All PCF8576Ds connected in cascade are correctly
synchronized by the SYNC signal. This synchronization is
guaranteed after the Power-on reset. The only time that
SYNC is likely to be needed is if synchronization is lost
accidentally, for example, by noise in adverse electrical
environments, or if the LCD multiplex drive mode is
changed in an application using several cascaded
PCF8576Ds, as the drive mode cannot be changed on all
of the cascaded devices simultaneously. SYNC can be
either an input or an output signal; a SYNC output is
implemented as an open-drain driver with an internal
pull-up resistor. A PCF8576D asserts SYNC at the start of
its last active backplane signal, and monitors the SYNC
line at all other times. If cascade synchronization is lost, it
will be restored by the first PCF8576D to assert SYNC.
The timing relationship between the backplane waveforms
and the SYNC signal for each LCD drive mode is shown in
Fig.18.
Table 14 SYNC contact resistance
MAXIMUM CONTACT
RESISTANCE
NUMBER OF DEVICES
2
6000 Ω
3 to 5
2200 Ω
1200 Ω
700 Ω
6 to 10
10 to 16
The contact resistance between the SYNC input/output on
each cascaded device must be controlled. If the resistance
is too high, the device will not be able to synchronize
properly; this is particularly applicable to chip-on-glass
applications. The maximum SYNC contact resistance
allowed for the number of devices in cascade is given in
Table 14.
V
V
LCD
DD
6
13
SDA
1, 58, 59
40 segment drives
SCL
SYNC
CLK
2, 3
4
LCD PANEL
PCF8576DU
(up to 2560
elements)
5
7
OSC
BP0 to BP3
8
9
10 11 12
(open-circuit)
A0 A1 A2 SA0 V
SS
V
V
LCD
DD
t
r
R ≤
V
V
2C
DD
LCD
B
6
13
SDA
HOST
MICRO-
PROCESSOR/
MICRO-
1, 58, 59
40 segment drives
SCL
SYNC
CLK
2, 3
4
PCF8576DU
CONTROLLER
4 backplanes
BP0 to BP3
5
7
OSC
MDB077
8
9
10 11 12
A0 A1 A2 SA0 V
SS
V
SS
Fig.17 Cascaded PCF8576D configuration.
23
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
1
T
= f
frame
frame
BP0
SYNC
(a) static drive mode.
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1 : 2 multiplex drive mode.
BP2
SYNC
(c) 1 : 3 multiplex drive mode.
BP3
SYNC
MGL755
(d) 1 : 4 multiplex drive mode.
Fig.18 Synchronization of the cascade for the various PCF8576D drive modes.
2003 Jun 23
24
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER
VDD
MIN.
−0.5
MAX.
+6.5
+7.5
UNIT
supply voltage
V
V
V
V
V
VLCD
Vi1
Vi2
VO
II
LCD supply voltage
VSS − 0.5
VSS − 0.5
VSS − 0.5
VSS − 0.5
input voltage CLK, SYNC, SA0, OSC, A0 to A2
input voltage SCL and SDA
output voltage S0 to S39, BP0 to BP3
DC input current
V
DD + 0.5
+6.5
V
DD + 0.5
−10
−10
−50
−50
−50
−
+10
+10
+50
+50
+50
400
100
+150
mA
mA
mA
mA
mA
mW
mW
°C
IO
DC output current
IDD
ISS
ILCD
Ptot
PO
Tstg
VDD current
VSS current
VLCD current
total power dissipation
power dissipation per output
storage temperature
−
−65
9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
2003 Jun 23
25
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
10 DC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
VLCD
IDD
supply voltage
1.8
−
−
8
5.5
V
V
LCD supply voltage
supply current
note 1
2.5
−
6.5
20
60
note 2; fCLK = 1536 Hz
note 2; fCLK = 1536 Hz
µA
µA
ILCD
LCD supply current
−
24
Logic
VIL
LOW-level input voltage
CLK, SYNC, OSC, A0 to A2 and SA0
VSS
−
−
0.3VDD
VDD
V
V
VIH
HIGH-level input voltage
0.7VDD
CLK, SYNC, OSC, A0 to A2 and SA0
VIL2
VIH2
IOL1
IOH1
IOL2
IL1
LOW-level input voltage SCL, SDA
HIGH-level input voltage SCL, SDA
VSS
−
−
−
−
−
−
0.3VDD
V
note 3
0.7VDD
VDD
−
V
LOW-level output current CLK, SYNC VOL = 0.4 V; VDD = 5 V
1
mA
mA
mA
µA
HIGH-level output current CLK
LOW-level output current SDA
VOH = 4.6 V; VDD = 5 V
VOL = 0.4 V; VDD = 5 V
VI = VDD or VSS
−1
3
−
−
leakage current
−1
+1
CLK, SCL, SDA, A0 to A2 and SA0
IL2
leakage current OSC
power-on reset voltage level
input capacitance
VI = VDD
note 4
−1
1.0
−
−
+1
1.6
7
µA
V
VPOR
CI
1.3
−
pF
LCD outputs
VBP
VS
DC voltage tolerance BP0 to BP3
−100
−100
−
−
+100
+100
−
mV
mV
kΩ
kΩ
DC voltage tolerance S0 to S39
output resistance BP0 to BP3
output resistance S0 to S39
−
RBP
RS
note 5; VLCD = 5 V
note 5; VLCD = 5 V
1.5
6.0
−
−
Notes
1. VLCD > 3 V for 1⁄3bias.
2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
3. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven according to the Vi2 limiting values
given in Chapter 8. Also see Fig.23.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.
2003 Jun 23
26
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
11 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
oscillator frequency
CONDITIONS
note 1
MIN.
397
TYP. MAX. UNIT
fCLK
1536
3046
Hz
µs
µs
ns
µs
µs
tCLKH
tCLKL
input CLK HIGH time
input CLK LOW time
60
60
−
−
−
−
−
tPD(SYNC) SYNC propagation delay
30
−
−
tSYNCL
SYNC LOW time
1
−
tPD(LCD)
driver delays with test loads
VLCD = 5 V; note 2
−
−
30
Timing characteristics: I2C-bus; note 3
fSCL
SCL clock frequency
−
−
−
−
−
−
−
−
−
−
−
−
−
−
400
−
kHz
µs
µs
µs
µs
µs
µs
µs
pF
ns
ns
µs
ns
tBUF
bus free time between a STOP and START
START condition hold time
set-up time for a repeated START condition
SCL LOW time
1.3
0.6
0.6
1.3
0.6
−
tHD;STA
tSU;STA
tLOW
tHIGH
tr
−
−
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
0.3
0.3
400
−
tf
−
CB
capacitive bus line load
data set-up time
−
tSU;DAT
tHD;DAT
tSU;STO
tSW
100
0
data hold time
−
set-up time for STOP condition
tolerable spike width on bus
0.6
−
−
50
Notes
1. Typical output duty factor: 50% measured at the CLK output pin.
2. Not tested in production.
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD
.
6.8 Ω
SYNC
CLK
V
DD
(2%)
3.3 kΩ
1.5 kΩ
SDA,
SCL
0.5V
V
DD
DD
(2%)
(2%)
1 nF
BP0 to BP3, and
S0 to S39
V
SS
MCE439
Fig.19 Test loads.
27
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
1/f
CLK
t
t
CLKL
CLKH
0.7V
0.3V
DD
CLK
DD
0.7V
0.3V
DD
SYNC
DD
t
t
PD(SYNC)
PD(SYNC)
t
SYNCL
0.5 V
BP0 to BP3,
and S0 to S39
(V
= 5 V)
DD
0.5 V
t
PD(LCD)
MCE424
Fig.20 Driver timing waveforms.
SDA
t
t
t
f
BUF
LOW
SCL
t
t
t
SU;DAT
t
HD;STA
r
t
HD;DAT
HIGH
SDA
t
SU;STA
MGA728
t
SU;STO
Fig.21 I2C-bus timing waveforms.
28
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
12 BONDING PAD INFORMATION
COORDINATES
SYMBOL
S12
PAD
Table 15 Bonding pad locations
x
y
All x/y coordinates represent the position of the centre of
each pad (in µm) with respect to the centre (x/y = 0) of the
chip (see Fig.22).
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
−318.78
−402.03
−485.28
−568.53
−651.78
−735.03
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−1005.5
−735.03
−663.03
−591.03
−519.03
−447.03
−375.03
−196.38
−106.38
876.6
876.6
876.6
876.6
876.6
876.6
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
SDA
SDA
COORDINATES
SYMBOL
SDA
PAD
x
y
1
−34.38
109.53
181.53
365.58
469.08
577.08
740.88
835.83
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
1005.48
347.22
263.97
180.72
97.47
−876.6
−876.6
−876.6
−876.6
−876.6
−876.6
−876.6
−876.6
−630.9
−513.9
−396.9
−221.4
10.71
SCL
SCL
SYNC
CLK
VDD
OSC
A0
2
625.59
541.62
458.19
374.76
291.33
207.9
3
4
5
6
7
8
124.47
41.04
A1
9
A2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
−42.39
−125.8
−209.3
−292.7
−376.1
−459.5
−543
SA0
VSS
VLCD
BP0
BP2
BP1
BP3
S0
156.51
232.74
308.97
385.2
−625.6
−876.6
−876.6
−876.6
−876.6
−876.6
−876.6
−876.6
−876.6
493.2
S1
565.2
S2
637.2
S3
709.2
S4
876.6
S5
876.6
S6
876.6
S7
876.6
S8
14.22
876.6
Alignment marks
S9
−69.03
−152.28
−235.53
876.6
C1
C2
930.42
−870.3
−870.3
S10
S11
876.6
−829.98
876.6
2003 Jun 23
29
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
35 34 33 32 31 30 29 28 27 26 25 24 23 22
21
20
19
18
17
16
15
14
S3
S2
S1
S0
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
S18
S19
S20
S21
S22
S23
S24
BP3
BP1
BP2
BP0
V
S25
S26
S27
S28
S29
S30
S31
S32
S33
13
x
LCD
2.01
mm
0
0
y
V
12
11
SS
SA0
PCF8576DU
10
9
A2
A1
C2
C1
4
8
1
2
3
5
6
7
52 53 54 55 56 57
58 59
MDB074
2.26 mm
Chip dimensions: approximately 2.26 × 2.01 mm.
Bump dimensions (except pad 1): 52 × 80 × 17.5 (height) µm.
Bump dimensions (pad 1): 52 × 76 × 17.5 (height) µm.
Alignment marks: diameter = 72 µm.
Fig.22 Bonding pad locations.
30
2003 Jun 23
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
13 DEVICE PROTECTION
V
V
V
DD
DD
SA0
V
V
SS
SS
DD
CLK
OSC
SCL
V
V
SS
DD
V
SS
V
V
SS
SDA
DD
SYNC
V
V
V
SS
SS
DD
A0, A1 A2
V
V
SS
LCD
BP0, BP1,
BP2, BP3
V
V
SS
V
LCD
LCD
S0 to S39
V
V
SS
SS
MDB076
Fig.23 Device protection diagram.
2003 Jun 23
31
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
14 TRAY INFORMATION
x
G
A
C
H
y
1,1
1,2
2,1
x,1
D
B
F
x,y
1,y
E
MCE404
For dimensions, see Table 16.
Fig.24 Tray details.
Table 16 Tray dimensions (see Fig.24)
SYMBOL
DESCRIPTION
VALUE
handbook, halfpage
A
B
C
D
E
F
G
H
x
pocket pitch, in x direction
pocket pitch, in y direction
pocket width, in x direction
pocket width, in y direction
tray width, in x direction
5.59 mm
6.35 mm
3.16 mm
3.16 mm
50.8 mm
50.8 mm
5.83 mm
6.35 mm
8
PC8576DU
tray width, in y direction
cut corner to pocket 1,1 centre
cut corner to pocket 1,1 centre
number of pockets in x direction
number of pockets in y direction
y
7
MDB080
The orientation of the IC in a pocket is indicated by the
position of the IC type name on the die surface with
respect to the chamfer on the upper left corner of the tray.
Fig.25 Tray alignment.
2003 Jun 23
32
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
15 PACKAGE OUTLINE
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
SOT357-1
y
X
A
48
33
Z
49
32
E
e
H
E
E
(A )
3
A
2
A
A
1
w M
p
θ
pin 1 index
b
L
p
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.05
0.05 0.95
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.2
mm
0.25
0.5
1
0.2 0.08 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
02-03-14
SOT357-1
137E10
MS-026
2003 Jun 23
33
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
16 SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
16.1 Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all the BGA packages
16.4 Manual soldering
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
16.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2003 Jun 23
34
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
suitable
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Jun 23
35
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
17 DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18 DEFINITIONS
19 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jun 23
36
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
Bare die
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for
a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems
after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify
their application in which the die is used.
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 Jun 23
37
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
NOTES
2003 Jun 23
38
Philips Semiconductors
Product specification
Universal LCD driver
for low multiplex rates
PCF8576D
NOTES
2003 Jun 23
39
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/02/pp40
Date of release: 2003 Jun 23
Document order number: 9397 750 11483
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