935283492112_技术文档

PCA8574/74A

Remote 8-bit I/O expander for I²C-bus with interrupt

Rev. 02 — 14 May 2007

Product data sheet

1. General description

The PCA8574/74A provide general purpose remote I/O expansion for most

microcontroller families via the two-line bidirectional I²C-bus (serial clock (SCL), serial

data (SDA)).

The devices consist of an 8-bit quasi-bidirectional port and an I²C-bus interface. The

PCA8574/74A have low current consumption and include latched outputs with 25 mA high

current drive capability for directly driving LEDs.

The PCA8574/74A also possess an interrupt line (INT) that can be connected to the

interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote

I/O can inform the microcontroller if there is incoming data on its ports without having to

communicate via the I²C-bus.

The internal Power-On Reset (POR) initializes the I/Os as inputs.

2. Features

I 400 kHz I²C-bus interface

I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

I 8-bit remote I/O pins that default to inputs at power-up

I Latched outputs with 25 mA sink capability for directly driving LEDs

I Total package sink capability of 200 mA

I Active LOW open-drain interrupt output

I 8 programmable slave addresses using 3 address pins

I Readable device ID (manufacturer, device type, and revision)

I Low standby current (10 µA max.)

I −40 °C to +85 °C operation

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

I Packages offered: DIP16, SO16, TSSOP16, SSOP20

3. Applications

I LED signs and displays

I Servers

I Industrial control

I Medical equipment

I PLCs

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

I Cellular telephones

I Gaming machines

I Instrumentation and test measurement

4. Ordering information

Table 1.

Ordering information

Type number Topside

mark

Package

Name

Description

Version

PCA8574D

PCA8574AD

PCA8574N

PCA8574AN

PCA8574PW

PCA8574D

PCA8574AD

PCA8574N

PCA8574AN

PCA8574

SO16

plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

DIP16

plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

SOT403-1

SOT266-1

TSSOP16

SSOP20

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

PCA8574APW PA8574A

PCA8574TS

PCA8574ATS

PCA8574

plastic shrink small outline package; 20 leads;

body width 4.4 mm

PCA8574A

5. Block diagram

PCA8574

PCA8574A

INTERRUPT

LOGIC

LP FILTER

INT

AD0

AD1

AD2

SCL

SDA

2

SHIFT

REGISTER

I/O

PORT

INPUT

FILTER

I C-BUS

8 BITS

P0 to P7

CONTROL

write pulse

read pulse

POWER-ON

RESET

V

DD

V

SS

002aac677

Fig 1. Block diagram of PCA8574/74A

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

2 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

V

DD

I

OH

OL

write pulse

100 µA

I

trt(pu)

D

Q

data from Shift Register

FF

S

P0 to P7

I

CI

power-on reset

V

SS

D

Q

FF

S

CI

read pulse

to interrupt logic

data to Shift Register

002aac109

Fig 2. Simpliﬁed schematic diagram of P0 to P7

6. Pinning information

6.1 Pinning

PCA8574N

PCA8574AN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AD0

AD1

AD2

P0

V

DD

SDA

SCL

INT

P7

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AD0

V

DD

AD1

AD2

P0

SDA

SCL

INT

P7

P1

PCA8574D

PCA8574AD

P2

P6

P1

P2

P6

P3

P5

P3

P5

V

SS

P4

V

SS

P4

002aac679

002aac678

Fig 3. Pin conﬁguration for DIP16

Fig 4. Pin conﬁguration for SO16

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

3 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

1

2

20

19

18

17

16

15

14

13

12

11

INT

SCL

n.c.

P7

P6

n.c.

P5

P4

3

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AD0

AD1

AD2

P0

V

DD

4

SDA

SCL

INT

P7

5

V

DD

PCA8574TS

PCA8574ATS

6

AD0

AD1

n.c.

AD2

P0

V

SS

PCA8574PW

PCA8574APW

7

P3

n.c.

P2

P1

8

P2

P6

9

P3

P5

10

V

SS

P4

002aac680

002aac941

Fig 5. Pin conﬁguration for TSSOP16

Fig 6. Pin conﬁguration for SSOP20

6.2 Pin description

Table 2.

Symbol

AD0

AD1

AD2

P0

Pin description for DIP16, SO16, TSSOP16

1

Description

address input 0

address input 1

address input 2

2

3

4

quasi-bidirectional I/O 0

quasi-bidirectional I/O 1

quasi-bidirectional I/O 2

quasi-bidirectional I/O 3

supply ground

P1

5

P2

6

P3

7

V_SS

P4

8

9

quasi-bidirectional I/O 4

quasi-bidirectional I/O 5

quasi-bidirectional I/O 6

quasi-bidirectional I/O 7

interrupt output (active LOW)

serial clock line

P5

10

11

12

13

14

15

16

P6

P7

INT

SCL

SDA

V_DD

serial data line

supply voltage

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

4 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Table 3.

Pin description for SSOP20

Symbol

INT

SCL

n.c.

SDA

V_DD

AD0

AD1

n.c.

AD2

P0

1

Description

interrupt output (active LOW)

serial clock line

2

3

not connected

4

serial data line

5

supply voltage

6

address input 0

7

address input 1

8

not connected

9

address input 2

10

11

12

13

14

15

16

17

18

19

20

quasi-bidirectional I/O 0

quasi-bidirectional I/O 1

quasi-bidirectional I/O 2

not connected

P1

P2

n.c.

P3

quasi-bidirectional I/O 3

supply ground

V_SS

P4

quasi-bidirectional I/O 4

quasi-bidirectional I/O 5

not connected

P5

n.c.

P6

quasi-bidirectional I/O 6

quasi-bidirectional I/O 7

P7

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

5 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

7. Functional description

Refer to Figure 1 “Block diagram of PCA8574/74A”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA8574/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of

8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on

AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in

Table 4 “PCA8574 address map” and Table 5 “PCA8574A address map”.

Remark: When using the PCA8574A, the General Call address (0000 0000b) and the

Device ID address (1111 100Xb) are reserved and cannot be used as device address.

Failure to follow this requirement will cause the PCA8574A not to acknowledge.

slave address

A6 A5 A4 A3 A2 A1 A0 R/W

programmable

002aab636

Fig 7. PCA8574/74A address

The last bit of the ﬁrst byte deﬁnes the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation.

When AD2, AD1 and AD0 are held to V_DDor V_SS, the same address as the PCF8574 or

PCF8574A is applied.

7.1.1 Address maps

Table 4.

A6

PCA8574 address map

A5

1

A4

0

A3

0

A2

0

A1

0

A0

0

Address

20h

0

1

0

1

21h

1

0

1

0

22h

1

0

1

23h

1

0

1

0

24h

1

0

1

0

1

25h

1

0

1

0

26h

1

0

1

27h

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

6 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Table 5.

PCA8574A address map

A6

0

A5

1

A4

1

A3

1

A2

0

A1

0

A0

0

Address

38h

0

1

0

1

39h

0

1

0

1

0

3Ah

0

1

0

1

3Bh

0

1

0

3Ch

3Dh

3Eh

0

1

0

1

0

1

0

1

3Fh

8. I/O programming

8.1 Quasi-bidirectional I/O architecture

The PCA8574/74A’s 8 ports (see Figure 2) are entirely independent and can be used

either as input or output ports. Input data is transferred from the ports to the

microcontroller in the Read mode (see Figure 9). Output data is transmitted to the ports in

the Write mode (see Figure 8).

This quasi-bidirectional I/O can be used as an input or output without the use of a control

signal for data directions. At power-on the I/Os are HIGH. In this mode only a current

source (I_OH) to V_DDis active. An additional strong pull-up to V_DD(I_trt(pu)) allows fast rising

edges into heavily loaded outputs. These devices turn on when an output is written HIGH,

and are switched off by the negative edge of SCL. The I/Os should be HIGH before being

used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as

inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the

write mode.

Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large

current (I_OL) will ﬂow to V_SS

.

8.2 Writing to the port (Output mode)

To write, the master (microcontroller) ﬁrst addresses the slave device. By setting the last

bit of the byte containing the slave address to logic 0 the write mode is entered. The

PCA8574/74A acknowledges and the master sends the data byte for P7 to P0 and is

acknowledged by the PCA8574/74A. The 8-bit data is presented on the port lines after it

has been acknowledged by the PCA8574/74A.

The number of data bytes that can be sent successively is not limited. The previous data

is overwritten every time a data byte has been sent.

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

7 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

SCL

1

2

3

4

5

6

7

8

9

slave address

A6 A5 A4 A3 A2 A1 A0

data 1

P4 P3 P2 P1 P0

data 2

SDA

S

0

A

P7 P6

1

A

P7

0

P5 P4 P3 P2 P1 P0

A

P5

START condition

write to port

R/W

P5

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

t

v(Q)

data output from port

P5 output voltage

DATA 1 VALID

DATA 2 VALID

I

trt(pu)

P5 pull-up output current

INT

I

OH

t

d(rst)

002aac120

Fig 8. Write mode (output)

8.3 Reading from a port (Input mode)

All ports programmed as input should be set to logic 1. To read, the master

(microcontroller) ﬁrst addresses the slave device after it receives the interrupt. By setting

the last bit of the byte containing the slave address to logic 1 the Read mode is entered.

The data bytes that follow on the SDA are the values on the ports.

If the data on the input port changes faster than the master can read, this data may be

lost.

no acknowledge

from master

slave address

data from port

DATA 1

data from port

DATA 4

SDA

S

A6 A5 A4 A3 A2 A1 A0

1

A

1

P

START condition

R/W acknowledge

from slave

acknowledge

from master

STOP

condition

read from

port

DATA 2

data into

port

DATA 3

DATA 4

t

su(D)

h(D)

INT

t

d(rst)

v(Q)

d(rst)

002aac121

A LOW-to-HIGH transition of SDA while SCL is HIGH is deﬁned as the STOP condition (P). Transfer of data can be stopped

at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode).

Input data is lost.

Fig 9. Read input port register

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

8 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

8.4 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the

PCA8574/74A in a reset condition until V_DDhas reached V_POR. At that point, the reset

condition is released and the PCA8574/74A registers and I²C-bus/SMBus state machine

will initialize to their default states. Thereafter V_DDmust be lowered below 0.2 V to reset

the device.

8.5 Interrupt output (INT)

The PCA8574/74A provides an open-drain interrupt (INT) which can be fed to a

corresponding input of the microcontroller (see Figure 8, Figure 9, and Figure 10). This

gives these chips a kind of master function which can initiate an action elsewhere in the

system.

An interrupt is generated by any rising or falling edge of the port inputs. After time t_v(D)the

signal INT is valid.

The interrupt disappears when data on the port is changed to the original setting or data is

read from or written to the device which has generated the interrupt.

In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the

write to port pulse. On the falling edge of the write to port pulse the interrupt is deﬁnitely

deactivated (HIGH).

The interrupt is reset in the read mode on the rising edge of the read from port pulse.

During the resetting of the interrupt itself, any changes on the I/Os may not generate an

interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as

an INT.

V

DD

device 1

device 2

device 8

PCA8574

MICROCOMPUTER

INT

002aac682

Fig 10. Application of multiple PCA8574s with interrupt

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

9 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

9. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 11).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 11. Bit transfer

9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 12.)

SDA

SCL

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 12. Deﬁnition of START and STOP conditions

9.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 13).

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

10 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

2

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

TRANSMITTER/

RECEIVER

MULTIPLEXER

SLAVE

002aaa966

Fig 13. System conﬁguration

9.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 14. Acknowledgement on the I²C-bus

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

11 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

10. Application design-in information

10.1 Bidirectional I/O expander applications

In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and P2 to

P7 are outputs. When used in this conﬁguration, during a write, the input (P0 and P1)

must be written as HIGH so the external devices fully control the input ports. The desired

HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). During a

read, the logic levels of the external devices driving the input ports (P0 and P1) and the

previous written logic level to the output ports (P2 to P7) will be read.

The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of

the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the

microprocessor that there is incoming data or a change of data on its ports without having

to communicate via the I²C-bus.

V

DD

V

DD

V

DD

SDA

SCL

INT

P0

P1

P2

P3

P4

P5

P6

P7

temperature sensor

battery status

CORE

PROCESSOR

control for latch

control for switch

control for audio

control for camera

control for MP3

AD0

AD1

AD2

002aac123

Fig 15. Bidirectional I/O expander application

10.2 High current-drive load applications

The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring

additional drive, two port pins in the same octal may be connected together to sink up to

50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one

octal) can be connected together to drive 200 mA.

V

DD

V

DD

SDA

SCL

INT

P0

P1

P2

P3

P4

P5

P6

P7

CORE

PROCESSOR

LOAD

AD0

AD1

AD2

002aac124

Fig 16. High current-drive load application

Rev. 02 — 14 May 2007

PCA8574_PCA8574A_2

Product data sheet

12 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

11. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

+6

Unit

V

V_DD

I_DD

I_SS

supply voltage

−0.5

supply current

-

±100

±400

5.5

mA

V

ground supply current

input voltage

V_I

V

_SS− 0.5

I_I

input current

-

±20

±50

400

100

+150

+85

mA

mW

°C

[1]

I_O

output current

-

P_tot

P/out

T_stg

T_amb

total power dissipation

power dissipation per output

storage temperature

ambient temperature

-

−65

−40

operating

°C

[1] Total package (maximum) output current is 400 mA.

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

13 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

12. Static characteristics

Table 7.

Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Supplies

Conditions

Min

Typ

Max

Unit

V_DD

I_DD

supply voltage

supply current

2.3

-

5.5

V

Operating mode; no load;

200

500

µA

V_I= V_DDor V_SS; f_SCL= 400 kHz;

AD0, AD1, AD2 = static H or L

I_stb

standby current

Standby mode; no load;

V_I= V_DDor V_SS; f_SCL= 0 kHz

-

4.5

1.8

10

µA

[1]

V_POR

power-on reset voltage

2.0

V

Input SCL; input/output SDA

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

−0.5

0.7V_DD

20

-

+0.3V_DD

V

-

5.5

-

V

V_OL= 0.4 V; V_DD= 2.3 V

V_OL= 0.4 V; V_DD= 3.0 V

V_OL= 0.4 V; V_DD= 4.5 V

V_I= V_DDor V_SS

35

44

57

-

mA

µA

pF

25

-

30

-

I_L

leakage current

−1

+1

10

C_i

input capacitance

V_I= V_SS

-

5

I/Os; P0 to P7

[2]

I_OL

LOW-level output current

V_OL= 0.5 V; V_DD= 2.3 V

V_OL= 0.5 V; V_DD= 3.0 V

V_OL= 0.5 V; V_DD= 4.5 V

V_OH= V_SS

12

17

25

-

26

-

mA

µA

33

-

40

-

I_OL(tot)

I_OH

I_trt(pu)

C_i

total LOW-level output current

HIGH-level output current

-

200

−300

-

−30

−0.5

-

−138

−1.0

2.1

transient boosted pull-up current V_OH= V_SS; see Figure 8

input capacitance

mA

pF

[3]

10

C_o

output capacitance

-

pF

Interrupt INT (see Figure 8 and Figure 9)

I_OL

C_o

LOW-level output current

output capacitance

V_OL= 0.4 V

3.0

-

mA

pF

3

5

Inputs AD0, AD1, AD2

V_IL

V_IH

I_LI

LOW-level input voltage

−0.5

0.7V_DD

−1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

µA

pF

C_i

-

3.5

[1] The power-on reset circuit resets the I²C-bus logic with V_DD< V_PORand sets all I/Os to logic 1 (with current source to V_DD).

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.

[3] The value is not tested, but veriﬁed on sampling basis.

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

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PCA8574/74A

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Remote 8-bit I/O expander for I²C-bus with interrupt

13. Dynamic characteristics

Table 8.

Dynamic characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed. Limits are for Fast-mode I²C-bus.

Symbol Parameter

f_SCLSCL clock frequency

t_BUF

Conditions

Min

0

Typ

Max

400

-

Unit

kHz

µs

-

bus free time between a STOP and START

condition

1.3

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_VD;ACK

t_VD;DAT

t_SU;DAT

t_LOW

hold time (repeated) START condition

set-up time for a repeated START condition

set-up time for STOP condition

data hold time

data valid acknowledge time^[1]

data valid time^[2]

0.6

-

µs

ns

µs

ns

µs

ns

0.6

-

0.6

-

0

-

0.1

0.9

50

-

data set-up time

100

-

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

1.3

-

t_HIGH

t_f

0.6

-

[3][4]

[5]

20 + 0.1C_b

-

300

50

t_r

t_SP

pulse width of spikes that must be suppressed

by the input ﬁlter^[6]

Port timing; C_L≤ 100 pF (see Figure 8 and Figure 9)

t_v(Q)

t_su(D)

t_h(D)

data output valid time

data input set-up time

data input hold time

-

4

-

µs

0

4

-

Interrupt timing; C_L≤ 100 pF (see Figure 8 and Figure 9)

t_v(D)

data input valid time

reset delay time

-

4

µs

t_d(rst)

[1] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undeﬁned region SCL’s falling edge.

[4] The maximum t_ffor the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time for the SDA output stage t_fis speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed t_f.

[5] C_b= total capacitance of one bus line in pF.

[6] Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

15 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

START

condition

(S)

bit 7

MSB

(A7)

STOP

bit 0 acknowledge

condition

bit 6

(A6)

protocol

(R/W)

(A)

(P)

t

HIGH

SU;STA

LOW

1

/f

SCL

SDA

t

BUF

f

t

r

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

002aab175

HD;STA

SU;DAT

Rise and fall times refer to V_ILand V_IH

.

Fig 17. I²C-bus timing diagram

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

16 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

14. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

16

9

M

H

pin 1 index

E

1

8

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

Z

A

2

(1)

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

E

max.

min.

max.

1.40

1.14

0.53

0.38

0.32

0.23

21.8

21.4

6.48

6.20

3.9

3.4

8.25

7.80

9.5

8.3

4.7

0.51

3.7

2.54

0.1

7.62

0.3

0.254

0.01

2.2

0.021

0.015

0.013

0.009

0.86

0.84

0.32

0.31

0.055

0.045

0.26

0.24

0.15

0.13

0.37

0.33

inches

0.19

0.02

0.15

0.087

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT38-1

050G09

MO-001

SC-503-16

Fig 18. Package outline SOT38-1 (DIP16)

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

17 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

SO16: plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

D

E

A

X

c

H

v

M

A

E

y

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

detail X

e

w

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

10.5

10.1

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25

0.01

0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.41

0.014 0.009 0.40

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT162-1

075E03

MS-013

Fig 19. Package outline SOT162-1 (SO16)

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

18 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 20. Package outline SOT403-1 (TSSOP16)

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

19 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm

SOT266-1

D

E

A

X

c

y

H

v

M

A

E

Z

11

20

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

10^o

0^o

0.15

0

1.4

1.2

0.32

0.20

0.13

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.45

0.65

0.45

0.48

0.18

mm

1.5

0.65

1

0.2

0.25

0.13

0.1

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT266-1

MO-152

Fig 21. Package outline SOT266-1 (SSOP20)

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

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Remote 8-bit I/O expander for I²C-bus with interrupt

15. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

16. Soldering

16.1 Introduction

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

16.2 Through-hole mount packages

16.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

16.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

16.3 Surface mount packages

16.3.1 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 22) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

21 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 9 and 10

Table 9.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 22.

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 22. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

22 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

16.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

16.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

16.4 Package related soldering information

Table 11. Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting

Package^[1]

Soldering method

Wave

Reﬂow^[2]

Dipping

Through-hole mount

CPGA, HCPGA

suitable

−

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable^[3]

−

suitable

Through-hole-surface

mount

PMFP^[4]

not suitable

−

PCA8574_PCA8574A_2

Product data sheet

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PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Table 11. Suitability of IC packages for wave, reﬂow and dipping soldering methods …continued

Mounting

Package^[1]

Soldering method

Wave

Reﬂow^[2]

Dipping

Surface mount

BGA, HTSSON..T^[5], LBGA,

LFBGA, SQFP, SSOP..T^[5], TFBGA,

VFBGA, XSON

not suitable

suitable

−

DHVQFN, HBCC, HBGA, HLQFP, not suitable^[6]

HSO, HSOP, HSQFP, HSSON,

HTQFP, HTSSOP, HVQFN,

suitable

−

HVSON, SMS

PLCC^[7], SO, SOJ

suitable

−

LQFP, QFP, TQFP

not recommended^[7][8]

not recommended^[9]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[10], WQCCN..L^[10]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP

Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with

respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of

the moisture in them (the so called popcorn effect).

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

[4] Hot bar soldering or manual soldering is suitable for PMFP packages.

[5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no account be processed

through more than one soldering cycle or subjected to infrared reﬂow soldering with peak temperature exceeding 217 °C ± 10 °C

measured in the atmosphere of the reﬂow oven. The package body peak temperature must be kept as low as possible.

[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate

between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the

heatsink surface.

[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint

must incorporate solder thieves downstream and at the side corners.

[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is deﬁnitely not suitable for

packages with a pitch (e) equal to or smaller than 0.65 mm.

[9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is deﬁnitely

not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on ﬂex foil.

However, the image sensor package can be mounted by the client on a ﬂex foil by using a hot bar soldering process. The appropriate

soldering proﬁle can be provided on request.

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

24 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

17. Abbreviations

Table 12. Abbreviations

Acronym

CDM

CMOS

ESD

Description

Charged Device Model

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

General Purpose Input/Output

Human Body Model

GPIO

HBM

LED

Light Emitting Diode

IC

Integrated Circuit

I²C-bus

Inter-Integrated Circuit bus

Identiﬁcation

ID

LSB

Least Signiﬁcant Bit

MM

Machine Model

MSB

PLC

Most Signiﬁcant Bit

Programmable Logic Controller

Pulse Width Modulation

Redundant Array of Independent Disks

System Management Bus

PWM

RAID

SMBus

18. Revision history

Table 13. Revision history

Document ID

Release date

20070514

Data sheet status

Change notice

Supersedes

PCA8574_PCA8574A_2

Modiﬁcations:

Product data sheet

-

PCA8574_PCA8574A_1

• Section 2 “Features”, last bullet item: changed “TSSOP20” to “TSSOP16”

• Table 1 “Ordering information”: changed package from TSSOP20 (SOT360-1) to

TSSOP16 (SOT403-1)

• Section 6.1 “Pinning”: deleted pin conﬁguration for TSSOP20; added pin conﬁguration for

TSSOP16

• Table 2 title changed (added TSSOP16)

• Table 3 title changed (deleted TSSOP20)

• Section 14 “Package outline”: changed package from TSSOP20 (SOT360-1) to

TSSOP16 (SOT403-1)

PCA8574_PCA8574A_1

20070117

Product data sheet

-

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

25 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

19.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

19.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

26 of 27

PCA8574/74A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

21. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

19

Legal information . . . . . . . . . . . . . . . . . . . . . . 26

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26

19.1

19.2

19.3

19.4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 26

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.1.1

Functional description . . . . . . . . . . . . . . . . . . . 6

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6

Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8

I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7

Quasi-bidirectional I/O architecture . . . . . . . . . 7

Writing to the port (Output mode). . . . . . . . . . . 7

Reading from a port (Input mode) . . . . . . . . . . 8

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

Interrupt output (INT) . . . . . . . . . . . . . . . . . . . . 9

8.1

8.2

8.3

8.4

8.5

9

Characteristics of the I²C-bus. . . . . . . . . . . . . 10

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

START and STOP conditions . . . . . . . . . . . . . 10

System conﬁguration . . . . . . . . . . . . . . . . . . . 10

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11

9.1

9.1.1

9.2

9.3

10

10.1

10.2

Application design-in information . . . . . . . . . 12

Bidirectional I/O expander applications . . . . . 12

High current-drive load applications . . . . . . . . 12

11

12

13

14

15

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13

Static characteristics. . . . . . . . . . . . . . . . . . . . 14

Dynamic characteristics . . . . . . . . . . . . . . . . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

Handling information. . . . . . . . . . . . . . . . . . . . 21

16

16.1

16.2

16.2.1

16.2.2

16.3

16.3.1

16.3.2

16.3.3

16.4

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Through-hole mount packages. . . . . . . . . . . . 21

Soldering by dipping or by solder wave . . . . . 21

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 21

Surface mount packages . . . . . . . . . . . . . . . . 21

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 21

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23

Package related soldering information . . . . . . 23

17

18

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 May 2007

Document identifier: PCA8574_PCA8574A_2


型号：	935283492112
厂家：	NXP
描述：	8 I/O, PIA-GENERAL PURPOSE, PDIP16, 0.300 INCH, PLASTIC, MO-001, SOT38-1, DIP-16 光电二极管外围集成电路
文件：	总27页 (文件大小：160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935283492112 [NXP]

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