935283683115 [NXP]
Bus Driver, HC/UH Series, 2-Func, 4-Bit, Inverted Output, CMOS, PQCC20;
| 型号： | 935283683115 |
| 厂家： | 
NXP |
| 描述： | Bus Driver, HC/UH Series, 2-Func, 4-Bit, Inverted Output, CMOS, PQCC20 驱动 逻辑集成电路 |
| 文件： | 总18页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
Rev. 03 — 2 August 2007
Product data sheet
1. General description
The 74HC240; 74HCT240 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL).
The 74HC240; 74HCT240 is a dual octal inverting buffer/line driver with 3-state outputs.
The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on
nOE causes the outputs to assume a high impedance OFF-state.
The 74HC240; 74HCT240 is similar to the 74HC244; 74HCT244 but has inverting
outputs.
2. Features
■ Inverting 3-state outputs
■ Multiple package options
■ Complies with JEDEC standard no. 7 A
■ ESD protection:
◆ HBM JESD22-A114-D exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC240
74HC240N
74HC240D
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
plastic small outline package; 20 leads;
body width 7.5 mm
74HC240DB
74HC240PW
74HC240BQ
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
TSSOP20
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
DHVQFN20 plastic dual-in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
SOT764-1
SOT146-1
74HCT240
74HCT240N
−40 °C to +125 °C
DIP20
plastic dual in-line package; 20 leads (300 mil)
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
Table 1.
Ordering information …continued
Type number
Package
Temperature range Name
Description
Version
74HCT240D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HCT240DB
74HCT240PW
74HCT240BQ
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
DHVQFN20 plastic dual-in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
SOT764-1
4. Functional diagram
1A0
2
1Y0
1Y1
1Y2
18
16
14
1A1
1A2
4
6
1A3
8
1
1Y3 12
1
2
EN
1OE
18
16
14
12
4
6
8
2
1Y0 18
2Y0
1A0
2A0
2Y0
2Y1
2Y2
2Y3
17
3
5
7
9
3
17 2A0
15 2A1
4
1A1
2A1
1Y1 16
15
5
2Y1
19
11
EN
2A2
13
6
14
7
1Y2
2Y2
1A2
2A2
13
9
2A3
11
19
8
12
9
1Y3
2Y3
1A3
2A3
13
15
17
7
5
3
11
2OE
1OE
2OE
1
19
mgu779
mgu780
mgu778
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Functional diagram
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
2 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
5. Pinning information
5.1 Pinning
74HC240
74HCT240
terminal 1
index area
74HC240
74HCT240
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
1
2
20
19
18
17
16
15
14
13
12
11
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND
V
CC
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
2A3
3
4
5
6
(1)
GND
7
8
9
001aag234
10
001aag233
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input
Fig 4. Pin configuration DIP20, SO20, (T)SSOP20
Fig 5. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE
1A0
Pin description
Pin
1
Description
output enable input (active LOW)
data input
2
2Y0
3
bus output
1A1
4
data input
2Y1
5
bus output
1A2
6
data input
2Y2
7
bus output
1A3
8
data input
2Y3
9
bus output
GND
2A3
10
11
12
13
14
15
16
ground (0 V)
data input
1Y3
bus output
2A2
data input
1Y2
bus output
2A1
data input
1Y1
bus output
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
3 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
Table 2.
Symbol
2A0
Pin description …continued
Pin
17
18
19
20
Description
data input
1Y0
bus output
2OE
output enable input (active LOW)
supply voltage
VCC
6. Functional description
Table 3.
Function table[1]
Input
nOE
L
Output
nAn
L
nYn
H
L
H
L
H
X
Z
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
−0.5
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
-
±20
±20
±35
70
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−70
−65
-
storage temperature
total power dissipation
DIP20 package
+150
[1]
-
-
750
500
mW
mW
SO20, SSOP20, TSSOP20
and DHVQFN20 packages
[1] For DIP20 packages: above 70 °C, Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C, Ptot derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C, Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C, Ptot derates linearly with 4.5 mW/K.
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
4 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
8. Recommended operating conditions
Table 5.
Symbol
74HC240
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
2.0
5.0
6.0
V
VI
input voltage
0
-
VCC
VCC
625
139
83
V
VO
output voltage
0
-
V
∆t/∆V
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
-
-
ns/V
ns/V
ns/V
°C
-
1.67
VCC = 6.0 V
-
-
-
Tamb
74HCT240
VCC
ambient temperature
−40
+125
supply voltage
4.5
0
5.0
5.5
V
VI
input voltage
-
VCC
VCC
139
+125
V
VO
output voltage
0
-
V
∆t/∆V
Tamb
input transition rise and fall rate VCC = 4.5 V
ambient temperature
-
1.67
-
ns/V
°C
−40
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC240
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5 1.2
3.15 2.4
4.2 3.2
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
VCC = 6.0 V
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.8
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6.0 V
1.9 2.0
4.4 4.5
5.9 6.0
3.98 4.32
5.48 5.81
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
3.84
5.34
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
5 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1.0
V
V
II
input leakage VI = VCC or GND;
-
±0.1
µA
current
VCC = 6.0 V
IOZ
OFF-state
per input pin; VI = VIH or VIL;
-
-
±0.5
-
±5.0
-
±10
µA
output current VO = VCC or GND;
other inputs at VCC or GND;
CC = 6.0 V; IO = 0 A
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
8.0
-
-
-
80
-
-
-
160
-
µA
V
input
3.5
pF
capacitance
74HCT240
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0 1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
-
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4 4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = −6 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 6.0 mA
0.16 0.26
0.33
±1.0
V
II
input leakage VI = VCC or GND;
-
±0.1
±1.0
µA
current
VCC = 5.5 V
IOZ
OFF-state
per input pin; VI = VIH or VIL;
-
-
±0.5
-
±5.0
-
±10
µA
µA
output current VO = VCC or GND;
other inputs at VCC or GND;
CC = 5.5 V; IO = 0 A
V
ICC
supply current VI = VCC or GND;
CC = 5.5 V; IO = 0 A
-
-
8.0
-
80
-
160
V
∆ICC
additional
per input pin;
supply current VI = VCC − 2.1 V;
other inputs at VCC or GND;
CC = 4.5 V to 5.5 V;
IO = 0 A
V
nAn or inputs
nOE input
-
-
-
150 540
-
-
-
675
315
-
-
-
-
735
343
-
µA
µA
pF
70
252
-
CI
input
3.5
capacitance
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
6 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for load circuit see Figure 8.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Min
Typ
Max
74HC240
[1]
tpd
propagation delay nAn to nYn;
see Figure 6
VCC = 2.0 V
-
-
-
-
30
11
9
100
20
-
125
25
-
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
nOE to nYn; see Figure 7
VCC = 2.0 V
9
17
21
26
[2]
[3]
[4]
[5]
ten
tdis
tt
enable time
disable time
transition time
-
-
-
39
14
11
150
30
190
38
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
33
38
nOE to nYn or see Figure 7
VCC = 2.0 V
-
-
-
41
15
12
150
30
190
38
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
33
38
see Figure 6
VCC = 2.0 V
-
-
-
-
14
5
60
12
10
-
75
15
13
-
90
18
15
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
4
CPD
power dissipation per transceiver;
capacitance VI = GND to VCC
30
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
7 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
Table 7.
Dynamic characteristics …continued
GND = 0 V; for load circuit see Figure 8.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Min
Typ
Max
74HCT240
[1]
tpd
propagation delay nAn to nYn;
see Figure 6
VCC = 4.5 V
-
-
-
11
9
20
-
25
-
30
-
ns
ns
ns
VCC = 5.0 V; CL = 15 pF
[2]
[3]
ten
enable time
disable time
transition time
nOE to nYn; VCC = 4.5 V; see
Figure 7
13
30
38
45
tdis
nOE to nYn; VCC = 4.5 V; see
Figure 7
-
13
25
31
38
ns
[4]
[5]
tt
VCC = 4.5 V; see Figure 6
-
-
5
12
-
15
-
18
-
ns
CPD
power dissipation per transceiver;
capacitance VI = GND to VCC − 1.5 V
30
pF
[1] tpd is the same as tPHL and tPLH
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPHZ and tPLZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC2 × fo) = sum of outputs.
11. Waveforms
V
I
nAn input
GND
V
V
M
t
M
t
PHL
PLH
V
OH
V
M
V
M
nYn output
V
OL
mgu781
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Input (nAn) to output (nYn) propagation delays and output transition times
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
8 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
nYn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nYn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae014
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. 3-state enable and disable times
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC240
0.5 × VCC
1.3 V
0.5 × VCC
1.3 V
0.1 × VCC
0.1 × VCC
0.9 × VCC
0.9 × VCC
74HCT240
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
9 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
PULSE
GENERATOR
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Load circuitry for measuring switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC240
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT240
open
GND
VCC
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
10 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
12. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 9. Package outline SOT146-1 (DIP20)
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
11 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 10. Package outline SOT163-1 (SO20)
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
12 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 11. Package outline SOT339-1 (SSOP20)
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
13 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 12. Package outline SOT360-1 (TSSOP20)
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
14 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 13. Package outline SOT764-1 (DHVQFN20)
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
15 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74HC_HCT240_3
Modifications:
Release date
20070802
Data sheet status
Change notice Supersedes
Product data sheet
-
74HC_HCT240_CNV_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74HC240BQ and 74HCT240BQ (DHVQFN20 package)
74HC_HCT240_CNV_2
19970828
Product specification
-
-
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
16 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
15.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
17 of 18
74HC240; 74HCT240
NXP Semiconductors
Octal buffer/line driver; 3-state; inverting
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 August 2007
Document identifier: 74HC_HCT240_3
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 216
-
VISHAY
©2020 ICPDF网 联系我们和版权申明