935285102000_技术文档

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash

with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC

Rev. 7.1 — 16 October 2013

Product data sheet

1. General description

The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S

CPU with real-time emulation that combines the microcontroller with up to 512 kB of

embedded high-speed flash memory. A 128-bit wide memory interface and a unique

accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical performance in interrupt service routines and DSP algorithms, this increases

performance up to 30 % over Thumb mode. For critical code size applications, the

alternative 16-bit Thumb mode reduces code by more than 30 % with minimal

performance penalty.

The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications.

They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed

device with 4 kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels

(LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three

I²C-bus interfaces, and an I²S-bus interface. This blend of serial communications

interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of up to 32 kB, 16 kB

SRAM for Ethernet, 8 kB SRAM for USB and general purpose use, together with 2 kB

battery powered SRAM make these devices very well suited for communication gateways

and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one

PWM unit, a CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up

to 12 edge or level sensitive external interrupt pins make these microcontrollers

particularly suitable for industrial control and medical systems.

2. Features and benefits

 ARM7TDMI-S processor, running at up to 72 MHz

 Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on the ARM

local bus for high performance CPU access.

 8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access.

 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

 8 kB SRAM for general purpose DMA use also accessible by the USB.

 Dual Advanced High-performance Bus (AHB) system that provides for simultaneous

Ethernet DMA, USB DMA, and program execution from on-chip flash with no

contention between those functions. A bus bridge allows the Ethernet DMA to access

the other AHB subsystem.

 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

 General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP

serial interfaces, the I²S port, and the Secure Digital/MultiMediaCard (SD/MMC) card

port, as well as for memory-to-memory transfers.

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

 Serial interfaces:

 Ethernet MAC with associated DMA controller. These functions reside on an

independent AHB.

 USB 2.0 full-speed device with on-chip PHY and associated DMA controller

(LPC2364/66/68 only).

 Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

 CAN controller with two channels (LPC2364/66/68 only).

 SPI controller.

 Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA

controller.

 Three I²C-bus interfaces (one with open-drain and two with standard port pins).

 I²S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

 Other peripherals:

 SD/MMC memory card interface (LPC2367/68 only).

 70 general purpose I/O pins with configurable pull-up/down resistors.

 10-bit ADC with input multiplexing among 6 pins.

 10-bit DAC.

 Four general purpose timers/counters with a total of 8 capture inputs and 10

compare outputs. Each timer block has an external count input.

 One PWM/timer block with support for three-phase motor control. The PWM has

two external count inputs.

 Real-Time Clock (RTC) with separate power pin, clock source can be the RTC

oscillator or the APB clock.

 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

 WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

 Standard ARM test/debug interface for compatibility with existing tools.

 Emulation trace module supports real-time trace.

 Single 3.3 V power supply (3.0 V to 3.6 V).

 Four reduced power modes: idle, sleep, power-down, and deep power-down.

 Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0

and Port 2 can be used as edge sensitive interrupt sources.

 Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt).

 Two independent power domains allow fine tuning of power consumption based on

needed features.

 Each peripheral has its own clock divider for further power saving.

 Brownout detect with separate thresholds for interrupt and forced reset.

 On-chip power-on reset.

 On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.

 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

the system clock. When used as the CPU clock, does not allow CAN and USB to run.

LPC2364_65_66_67_68

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.1 — 16 October 2013

2 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

 On-chip PLL allows CPU operation up to the maximum CPU rate without the need for

a high frequency crystal. May be run from the main oscillator, the internal RC oscillator,

or the RTC oscillator.

 Boundary scan for simplified board testing is available in LPC2364FET100 and

LPC2368FET100 (TFBGA package).

 Versatile pin function selections allow more possibilities for using on-chip peripheral

functions.

3. Applications

 Industrial control

 Medical systems

 Protocol converter

 Communications

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2364FBD100

LQFP100

plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm

SOT407-1

LPC2364HBD100 LQFP100

LPC2364FET100

LPC2365FBD100

LPC2366FBD100

LPC2367FBD100

LPC2368FBD100

LPC2368FET100

TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LQFP100

plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm

SOT407-1

TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC2364_65_66_67_68

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.1 — 16 October 2013

3 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

5. Block diagram

XTAL1

XTAL2

TMS TDI

trace signals

V

DDA

TRST TCK TDO

RESET

V

DD(3V3)

EXTIN0

LPC2364/65/66/67/68

VREF

128/256/

512 kB

FLASH

SYSTEM

FUNCTIONS

V , V

SSA SS

P0, P1, P2,

P3, P4

PLL

8/32 kB

SRAM

TEST/DEBUG

INTERFACE

V

DD(DCDC)(3V3)

system

clock

INTERNAL RC

OSCILLATOR

HIGH-SPEED

GPI/O

70 PINS

TOTAL

INTERNAL

CONTROLLERS

ARM7TDMI-S

SRAM FLASH

VECTORED

INTERRUPT

CONTROLLER

AHB1

AHB2

AHB

BRIDGE

AHB

BRIDGE

V

BUS

USB WITH

4 kB RAM

AND DMA

MASTER AHB TO SLAVE

PORT AHB BRIDGE PORT

8 kB

SRAM

USB_D+, USB_D−

USB_CONNECT

USB_UP_LED

ETHERNET

MAC WITH

DMA

16 kB

SRAM

RMII(8)

(2)

AHB TO

GP DMA

CONTROLLER

APB BRIDGE

EINT3 to EINT0

P0, P2

I2SRX_CLK

I2STX_CLK

I2SRX_WS

I2STX_WS

I2SRX_SDA

EXTERNAL INTERRUPTS

2

2 × CAP0/CAP1/

CAP2/CAP3

4 × MAT2,

2 × MAT0/MAT1/

MAT3

I S INTERFACE

CAPTURE/COMPARE

TIMER0/TIMER1/

TIMER2/TIMER3

I2STX_SDA

SCK, SCK0

MOSI, MOSI0

MISO, MISO0

SSEL, SSEL0

SPI, SSP0 INTERFACE

6 × PWM1

2 × PCAP1

PWM1

SCK1

LEGACY GPI/O

52 PINS TOTAL

MOSI1

MISO1

SSEL1

P0, P1

SSP1 INTERFACE

SD/MMC CARD

6 × AD0

AOUT

VBAT

A/D CONVERTER

D/A CONVERTER

2 kB BATTERY RAM

MCICLK, MCIPWR

(1)

MCICMD,

MCIDAT[3:0]

INTERFACE

TXD0, TXD2, TXD3

RXD0, RXD2, RXD3

UART0, UART2, UART3

UART1

TXD1

RXD1

DTR1, RTS1

power domain 2

REAL-

TIME

CLOCK

RTCX1

RTCX2

RTC

OSCILLATOR

DSR1, CTS1, DCD1,

RI1

RD1, RD2

TD1, TD2

(2)

WATCHDOG TIMER

CAN1, CAN2

SCL0, SCL1, SCL2

SDA0, SDA1, SDA2

2

SYSTEM CONTROL

I C0, I C1, I C2

002aac566

(1) LPC2367/68 only.

(2) LPC2364/66/68 only.

Fig 1. LPC2364/65/66/67/68 block diagram

LPC2364_65_66_67_68

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Product data sheet

Rev. 7.1 — 16 October 2013

5 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

6. Pinning information

6.1 Pinning

1

75

LPC2364FBD100

LPC2365FBD100

LPC2366FBD100

LPC2367FBD100

LPC2368FBD100

25

51

002aac576

Fig 2. LPC2364/65/66/67/68 pinning

ball A1

index area

LPC2364FET100/LPC2368FET100

1

2

3

4

5

6

7

8

9 10

A

B

C

D

E

F

G

H

J

K

002aad225

Transparent top view

Fig 3. LPC2364/68 pinning TFBGA100 package

LPC2364_65_66_67_68

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Product data sheet

Rev. 7.1 — 16 October 2013

6 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3.

Pin allocation table

Pin Symbol

Row A

Pin Symbol

1

5

TDO

2

6

P0[3]/RXD0

P1[16]/ENET_MDC

3

7

V_DD(3V3)

4

8

P1[4]/ENET_TX_EN

P1[10]/ENET_RXD1

V_{DD(DCDC)(3V3)}

P0[4]/I2SRX_CLK/

RD2/CAP2[0]

9

P0[7]/I2STX_CLK/

SCK1/MAT2[1]

10 P0[9]/I2STX_SDA/

MOSI1/MAT2[3]

11

-

12

-

Row B

1

5

TMS

2

6

RTCK

3

7

V_SS

4

8

P1[1]/ENET_TXD1

P1[9]/ENET_RXD0

P1[17]/

ENET_MDIO

P0[6]/I2SRX_SDA/

SSEL1/MAT2[0]

9

P2[0]/PWM1[1]/

TXD1/TRACECLK

10 P2[1]/PWM1[2]/

RXD1/PIPESTAT0

11

-

12

-

Row C

1

5

TCK

2

6

TRST

3

7

TDI

4

8

P0[2]/TXD0

P1[8]/ENET_CRS

P1[15]/

ENET_REF_CLK

P4[28]/MAT2[0]/

TXD3

P0[8]/I2STX_WS/

MISO1/MAT2[2]

9

V_SS

10 V_DD(3V3)

11

-

12

-

Row D

1

5

9

P0[24]/AD0[1]/

I2SRX_WS/CAP3[1]

2

6

P0[25]/AD0[2]/

I2SRX_SDA/TXD3

3

P0[26]/AD0[3]/

AOUT/RXD3

4

DBGEN

P1[0]/ENET_TXD0

P1[14]/ENET_RX_ER

7

P0[5]/I2SRX_WS/

TD2/CAP2[1]

8

P2[2]/PWM1[3]/

CTS1/PIPESTAT1

P2[4]/PWM1[5]/

DSR1/TRACESYNC

10 P2[5]/PWM1[6]/

DTR1/TRACEPKT0

11

-

12

-

Row E

1

5

V_SSA

2

6

V_DDA

3

7

VREF

4

8

V_{DD(DCDC)(3V3)}

P0[23]/AD0[0]/

I2SRX_CLK/CAP3[0]

P4[29]/MAT2[1]/

RXD3

P2[3]/PWM1[4]/

DCD1/PIPESTAT2

P2[6]/PCAP1[0]/RI1/

TRACEPKT1

9

P2[7]/RD2/

RTS1/TRACEPKT2

10 P2[8]/TD2/

TXD2/TRACEPKT3

11

-

12

-

Row F

1

5

9

V_SS

2

6

RTCX1

3

RESET

4

P1[31]/SCK1/

AD0[5]

P1[21]/PWM1[3]/

SSEL0

P0[18]/DCD1/

MOSI0/MOSI

7

P2[9]/USB_CONNECT/

RXD2/EXTIN0

8

P0[16]/RXD1/

SSEL0/SSEL

P0[17]/CTS1/

MISO0/MISO

10 P0[15]/TXD1/

SCK0/SCK

11

-

12

-

Row G

1

5

RTCX2

2

6

VBAT

3

7

XTAL2

V_SS

4

8

P0[30]/USB_D

P1[25]/MAT1[1]

P1[29]/PCAP1[1]/

MAT0[1]

P0[21]/RI1/

MCIPWR/RD1

9

P0[20]/DTR1/

MCICMD/SCL1

10 P0[19]/DSR1/

MCICLK/SDA1

11

-

12

-

Row H

LPC2364_65_66_67_68

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Product data sheet

Rev. 7.1 — 16 October 2013

7 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3.

Pin allocation table …continued

Pin Symbol

1

5

9

P1[30]/V_BUS

AD0[4]

/

2

XTAL1

3

P3[25]/MAT0[0]/

PWM1[2]

4

P1[18]/USB_UP_LED/

PWM1[1]/CAP1[0]

P1[24]/PWM1[5]/

MOSI0

6

V_{DD(DCDC)(3V3)}

7

P0[10]/TXD2/

SDA2/MAT3[0]

8

P2[11]/EINT1/

MCIDAT1/I2STX_CLK

V_DD(3V3)

10 P0[22]/RTS1/

MCIDAT0/TD1

11

-

12

-

LPC2364_65_66_67_68

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Product data sheet

Rev. 7.1 — 16 October 2013

8 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3.

Pin allocation table …continued

Pin Symbol

Row J

Pin Symbol

1

5

P0[28]/SCL0

2

6

P0[27]/SDA0

V_SS

3

7

P0[29]/USB_D+

4

8

P1[19]/CAP1[1]

P1[22]/MAT1[0]

P1[28]/PCAP1[0]/

MAT0[0]

P0[1]/TD1/RXD3/SCL1

9

P2[13]/EINT3/

10 P2[10]/EINT0

11

-

12

-

MCIDAT3/I2STX_SDA

Row K

1

5

9

P3[26]/MAT0[1]/

PWM1[3]

2

6

V_DD(3V3)

3

V_SS

4

P1[20]/PWM1[2]/

SCK0

P1[23]/PWM1[4]/

MISO0

P1[26]/PWM1[6]/

CAP0[0]

7

P1[27]/CAP0[1]

-

8

P0[0]/RD1/TXD3/SDA1

P0[11]/RXD2/

SCL2/MAT3[1]

10 P2[12]/EINT2/

MCIDAT2/I2STX_WS

11

12

-

LPC2364_65_66_67_68

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Product data sheet

Rev. 7.1 — 16 October 2013

9 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

6.2 Pin description

Table 4.

Symbol

Pin description

Ball

Type Description

P0[0] to P0[31]

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each

bit. The operation of Port 0 pins depends upon the pin function selected via

the pin connect block. Pins 12, 13, 14, and 31 of this port are not available.

P0[0]/RD1/TXD3/ 46^[1]

SDA1

K8^[1]

I/O

I

P0[0] — General purpose digital input/output pin.

RD1 — CAN1 receiver input. (LPC2364/66/68 only)

TXD3 — Transmitter output for UART3.

O

I/O

O

SDA1 — I²C1 data input/output (this is not an open-drain pin).

P0[1] — General purpose digital input/output pin.

TD1 — CAN1 transmitter output. (LPC2364/66/68 only)

RXD3 — Receiver input for UART3.

P0[1]/TD1/RXD3/ 47^[1]

SCL1

J8^[1]

I

I/O

O

SCL1 — I²C1 clock input/output (this is not an open-drain pin).

P0[2] — General purpose digital input/output pin.

TXD0 — Transmitter output for UART0.

P0[2]/TXD0

P0[3]/RXD0

98^[1]

99^[1]

81^[1]

C4^[1]

A2^[1]

A8^[1]

I/O

I

P0[3] — General purpose digital input/output pin.

RXD0 — Receiver input for UART0.

P0[4]/

I2SRX_CLK/

RD2/CAP2[0]

I/O

P0[4] — General purpose digital input/output pin.

I2SRX_CLK — Receive Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S-bus specification.

I

RD2 — CAN2 receiver input. (LPC2364/66/68 only)

CAP2[0] — Capture input for Timer 2, channel 0.

P0[5] — General purpose digital input/output pin.

I

P0[5]/

I2SRX_WS/

TD2/CAP2[1]

80^[1]

79^[1]

78^[1]

77^[1]

D7^[1]

B8^[1]

A9^[1]

C8^[1]

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and received

by the slave. Corresponds to the signal WS in the I²S-bus specification.

O

TD2 — CAN2 transmitter output. (LPC2364/66/68 only)

CAP2[1] — Capture input for Timer 2, channel 1.

P0[6] — General purpose digital input/output pin.

I

P0[6]/

I2SRX_SDA/

SSEL1/MAT2[0]

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I²S-bus specification.

I/O

O

SSEL1 — Slave Select for SSP1.

MAT2[0] — Match output for Timer 2, channel 0.

P0[7] — General purpose digital input/output pin.

P0[7]/

I2STX_CLK/

SCK1/MAT2[1]

I/O

I2STX_CLK — Transmit Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S-bus specification.

I/O

O

SCK1 — Serial Clock for SSP1.

MAT2[1] — Match output for Timer 2, channel 1.

P0[8] — General purpose digital input/output pin.

P0[8]/

I/O

I2STX_WS/

MISO1/MAT2[2]

I2STX_WS — Transmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I²S-bus

specification.

I/O

O

MISO1 — Master In Slave Out for SSP1.

MAT2[2] — Match output for Timer 2, channel 2.

LPC2364_65_66_67_68

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Product data sheet

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10 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 4.

Symbol

Pin description …continued

Ball

Type Description

P0[9]/

I2STX_SDA/

MOSI1/MAT2[3]

76^[1]

A10^[1]

I/O

P0[9] — General purpose digital input/output pin.

I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I²S-bus specification.

I/O

O

MOSI1 — Master Out Slave In for SSP1.

MAT2[3] — Match output for Timer 2, channel 3.

P0[10] — General purpose digital input/output pin.

TXD2 — Transmitter output for UART2.

P0[10]/TXD2/

SDA2/MAT3[0]

48^[1]

49^[1]

62^[1]

63^[1]

61^[1]

60^[1]

59^[1]

58^[1]

H7^[1]

K9^[1]

F10^[1]

F8^[1]

F9^[1]

F6^[1]

G10^[1]

G9^[1]

I/O

O

I/O

O

SDA2 — I²C2 data input/output (this is not an open-drain pin).

MAT3[0] — Match output for Timer 3, channel 0.

P0[11] — General purpose digital input/output pin.

RXD2 — Receiver input for UART2.

P0[11]/RXD2/

SCL2/MAT3[1]

I/O

I

I/O

O

SCL2 — I²C2 clock input/output (this is not an open-drain pin).

MAT3[1] — Match output for Timer 3, channel 1.

P0[15] — General purpose digital input/output pin.

TXD1 — Transmitter output for UART1.

P0[15]/TXD1/

SCK0/SCK

I/O

O

I/O

I

SCK0 — Serial clock for SSP0.

SCK — Serial clock for SPI.

P0[16]/RXD1/

SSEL0/SSEL

P0[16] — General purpose digital input/output pin.

RXD1 — Receiver input for UART1.

I/O

I

SSEL0 — Slave Select for SSP0.

SSEL — Slave Select for SPI.

P0[17]/CTS1/

MISO0/MISO

P0[17] — General purpose digital input/output pin.

CTS1 — Clear to Send input for UART1.

I/O

I

MISO0 — Master In Slave Out for SSP0.

MISO — Master In Slave Out for SPI.

P0[18]/DCD1/

MOSI0/MOSI

P0[18] — General purpose digital input/output pin.

DCD1 — Data Carrier Detect input for UART1.

MOSI0 — Master Out Slave In for SSP0.

I/O

I

MOSI — Master Out Slave In for SPI.

P0[19]/DSR1/

MCICLK/SDA1

P0[19] — General purpose digital input/output pin.

DSR1 — Data Set Ready input for UART1.

MCICLK — Clock output line for SD/MMC interface. (LPC2367/68 only)

SDA1 — I²C1 data input/output (this is not an open-drain pin).

P0[20] — General purpose digital input/output pin.

DTR1 — Data Terminal Ready output for UART1.

MCICMD — Command line for SD/MMC interface. (LPC2367/68 only)

SCL1 — I²C1 clock input/output (this is not an open-drain pin).

O

I/O

O

P0[20]/DTR1/

MCICMD/SCL1

I

I/O

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Product data sheet

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LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 4.

Symbol

Pin description …continued

Ball

Type Description

P0[21]/RI1/

MCIPWR/RD1

57^[1]

G8^[1]

I/O

I

P0[21] — General purpose digital input/output pin.

RI1 — Ring Indicator input for UART1.

O

MCIPWR — Power Supply Enable for external SD/MMC power supply.

(LPC2367/68 only)

I

RD1 — CAN1 receiver input. (LPC2364/66/68 only)

P0[22] — General purpose digital input/output pin.

RTS1 — Request to Send output for UART1.

P0[22]/RTS1/

MCIDAT0/TD1

56^[1]

H10^[1]

I/O

O

MCIDAT0 — Data line for SD/MMC interface. (LPC2367/68 only)

TD1 — CAN1 transmitter output. (LPC2364/66/68 only)

P0[23] — General purpose digital input/output pin.

AD0[0] — A/D converter 0, input 0.

O

P0[23]/AD0[0]/

I2SRX_CLK/

CAP3[0]

9^[2]

E5^[2]

I/O

I

I/O

I2SRX_CLK — Receive Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S-bus specification.

I

CAP3[0] — Capture input for Timer 3, channel 0.

P0[24] — General purpose digital input/output pin.

AD0[1] — A/D converter 0, input 1.

P0[24]/AD0[1]/

I2SRX_WS/

CAP3[1]

8^[2]

7^[2]

6^[3]

D1^[2]

D2^[2]

D3^[3]

I/O

I

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and received

by the slave. Corresponds to the signal WS in the I²S-bus specification.

I

CAP3[1] — Capture input for Timer 3, channel 1.

P0[25] — General purpose digital input/output pin.

AD0[2] — A/D converter 0, input 2.

P0[25]/AD0[2]/

I2SRX_SDA/

TXD3

I/O

I

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I²S-bus specification.

O

TXD3 — Transmitter output for UART3.

P0[26]/AD0[3]/

AOUT/RXD3

I/O

I

P0[26] — General purpose digital input/output pin.

AD0[3] — A/D converter 0, input 3.

O

AOUT — D/A converter output.

I

RXD3 — Receiver input for UART3.

P0[27]/SDA0

P0[28]/SCL0

25^[4]

24^[4]

J2^[4]

J1^[4]

I/O

P0[27] — General purpose digital input/output pin. Output is open-drain.

SDA0 — I²C0 data input/output. Open-drain output (for I²C-bus

compliance).

I/O

P0[28] — General purpose digital input/output pin. Output is open-drain.

SCL0 — I²C0 clock input/output. Open-drain output (for I²C-bus

compliance).

P0[29]/USB_D+

P0[30]/USB_D

P1[0] to P1[31]

29^[5]

30^[5]

J3^[5]

I/O

P0[29] — General purpose digital input/output pin.

USB_D+ — USB bidirectional D+ line. (LPC2364/66/68 only)

P0[30] — General purpose digital input/output pin.

G4^[5]

USB_D — USB bidirectional D line. (LPC2364/66/68 only)

Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each

bit. The operation of Port 1 pins depends upon the pin function selected via

the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not

available.

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Product data sheet

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LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 4.

Symbol

Pin description …continued

Ball

Type Description

P1[0]/

ENET_TXD0

95^[1]

D5^[1]

I/O

O

P1[0] — General purpose digital input/output pin.

ENET_TXD0 — Ethernet transmit data 0.

P1[1]/

ENET_TXD1

94^[1]

93^[1]

92^[1]

91^[1]

90^[1]

89^[1]

88^[1]

87^[1]

86^[1]

32^[1]

B4^[1]

A4^[1]

C5^[1]

B5^[1]

A5^[1]

D6^[1]

C6^[1]

A6^[1]

B6^[1]

H4^[1]

I/O

O

P1[1] — General purpose digital input/output pin.

ENET_TXD1 — Ethernet transmit data 1.

P1[4]/

ENET_TX_EN

I/O

O

P1[4] — General purpose digital input/output pin.

ENET_TX_EN — Ethernet transmit data enable.

P1[8] — General purpose digital input/output pin.

ENET_CRS — Ethernet carrier sense.

P1[8]/

ENET_CRS

I/O

I

P1[9]/

ENET_RXD0

I/O

I

P1[9] — General purpose digital input/output pin.

ENET_RXD0 — Ethernet receive data.

P1[10]/

ENET_RXD1

I/O

I

P1[10] — General purpose digital input/output pin.

ENET_RXD1 — Ethernet receive data.

P1[14]/

ENET_RX_ER

I/O

I

P1[14] — General purpose digital input/output pin.

ENET_RX_ER — Ethernet receive error.

P1[15]/

ENET_REF_CLK

I/O

I

P1[15] — General purpose digital input/output pin.

ENET_REF_CLK — Ethernet reference clock.

P1[16] — General purpose digital input/output pin.

ENET_MDC — Ethernet MIIM clock.

P1[16]/

ENET_MDC

I/O

O

P1[17]/

ENET_MDIO

I/O

O

P1[17] — General purpose digital input/output pin.

ENET_MDIO — Ethernet MIIM data input and output.

P1[18] — General purpose digital input/output pin.

P1[18]/

USB_UP_LED/

PWM1[1]/

CAP1[0]

USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is

configured (non-control endpoints enabled), or when host is enabled and

has detected a device on the bus. It is HIGH when the device is not

configured, or when host is enabled and has not detected a device on the

bus, or during global suspend. It transitions between LOW and HIGH

(flashes) when host is enabled and detects activity on the bus.

(LPC2364/66/68 only)

O

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

CAP1[0] — Capture input for Timer 1, channel 0.

P1[19] — General purpose digital input/output pin.

CAP1[1] — Capture input for Timer 1, channel 1.

P1[20] — General purpose digital input/output pin.

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

SCK0 — Serial clock for SSP0.

I

P1[19]/CAP1[1]

33^[1]

J4^[1]

K4^[1]

I/O

I

P1[20]/PWM1[2]/ 34^[1]

SCK0

I/O

O

I/O

O

P1[21]/PWM1[3]/ 35^[1]

SSEL0

F5^[1]

P1[21] — General purpose digital input/output pin.

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

SSEL0 — Slave Select for SSP0.

I/O

O

P1[22]/MAT1[0]

36^[1]

J5^[1]

P1[22] — General purpose digital input/output pin.

MAT1[0] — Match output for Timer 1, channel 0.

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Product data sheet

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LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 4.

Symbol

Pin description …continued

Ball

Type Description

P1[23]/PWM1[4]/ 37^[1]

MISO0

K5^[1]

I/O

O

P1[23] — General purpose digital input/output pin.

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I/O

O

MISO0 — Master In Slave Out for SSP0.

P1[24]/PWM1[5]/ 38^[1]

MOSI0

H5^[1]

P1[24] — General purpose digital input/output pin.

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

MOSI0 — Master Out Slave in for SSP0.

I/O

O

P1[25]/MAT1[1]

39^[1]

G5^[1]

K6^[1]

P1[25] — General purpose digital input/output pin.

MAT1[1] — Match output for Timer 1, channel 1.

P1[26] — General purpose digital input/output pin.

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

CAP0[0] — Capture input for Timer 0, channel 0.

P1[27] — General purpose digital input/output pin.

CAP0[1] — Capture input for Timer 0, channel 1.

P1[28] — General purpose digital input/output pin.

PCAP1[0] — Capture input for PWM1, channel 0.

MAT0[0] — Match output for Timer 0, channel 0.

P1[29] — General purpose digital input/output pin.

PCAP1[1] — Capture input for PWM1, channel 1.

MAT0[1] — Match output for Timer 0, channel 0.

P1[30] — General purpose digital input/output pin.

V_BUS— Monitors the presence of USB bus power. (LPC2364/66/68 only)

Note: This signal must be HIGH for USB reset to occur.

AD0[4] — A/D converter 0, input 4.

P1[26]/PWM1[6]/ 40^[1]

CAP0[0]

I/O

O

I

P1[27]/CAP0[1]

43^[1]

44^[1]

K7^[1]

J7^[1]

I/O

I

P1[28]/

I/O

I

PCAP1[0]/

MAT0[0]

O

P1[29]/

45^[1]

G6^[1]

H1^[2]

I/O

I

PCAP1[1]/

MAT0[1]

O

P1[30]/V_BUS

AD0[4]

/

21^[2]

I/O

I

P1[31]/SCK1/

AD0[5]

20^[2]

F4^[2]

I/O

I

P1[31] — General purpose digital input/output pin.

SCK1 — Serial Clock for SSP1.

AD0[5] — A/D converter 0, input 5.

P2[0] to P2[31]

I/O

Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each

bit. The operation of Port 2 pins depends upon the pin function selected via

the pin connect block. Pins 14 through 31 of this port are not available.

P2[0]/PWM1[1]/

TXD1/

TRACECLK

75^[1]

74^[1]

73^[1]

B9^[1]

B10^[1]

D8^[1]

I/O

O

I/O

O

I

P2[0] — General purpose digital input/output pin.

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

TXD1 — Transmitter output for UART1.

TRACECLK — Trace Clock.

P2[1]/PWM1[2]/

RXD1/

PIPESTAT0

P2[1] — General purpose digital input/output pin.

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

RXD1 — Receiver input for UART1.

O

I/O

O

I

PIPESTAT0 — Pipeline Status, bit 0.

P2[2]/PWM1[3]/

CTS1/

PIPESTAT1

P2[2] — General purpose digital input/output pin.

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

CTS1 — Clear to Send input for UART1.

PIPESTAT1 — Pipeline Status, bit 1.

O

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Product data sheet

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LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 4.

Symbol

Pin description …continued

Ball

Type Description

P2[3]/PWM1[4]/

DCD1/

PIPESTAT2

70^[1]

E7^[1]

I/O

O

I

P2[3] — General purpose digital input/output pin.

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

DCD1 — Data Carrier Detect input for UART1.

PIPESTAT2 — Pipeline Status, bit 2.

O

I/O

O

I

P2[4]/PWM1[5]/

DSR1/

TRACESYNC

69^[1]

D9^[1]

D10^[1]

E8^[1]

E9^[1]

E10^[1]

F7^[1]

P2[4] — General purpose digital input/output pin.

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

DSR1 — Data Set Ready input for UART1.

TRACESYNC — Trace Synchronization.

O

I/O

O

I/O

I

P2[5]/PWM1[6]/

DTR1/

TRACEPKT0

68^[1]

P2[5] — General purpose digital input/output pin.

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

DTR1 — Data Terminal Ready output for UART1.

TRACEPKT0 — Trace Packet, bit 0.

P2[6]/PCAP1[0]/ 67^[1]

RI1/

TRACEPKT1

P2[6] — General purpose digital input/output pin.

PCAP1[0] — Capture input for PWM1, channel 0.

RI1 — Ring Indicator input for UART1.

I

O

I/O

I

TRACEPKT1 — Trace Packet, bit 1.

P2[7]/RD2/

RTS1/

TRACEPKT2

66^[1]

65^[1]

64^[1]

P2[7] — General purpose digital input/output pin.

RD2 — CAN2 receiver input. (LPC2364/66/68 only)

RTS1 — Request to Send output for UART1.

TRACEPKT2 — Trace Packet, bit 2.

O

I/O

O

I/O

O

P2[8]/TD2/

TXD2/

TRACEPKT3

P2[8] — General purpose digital input/output pin.

TD2 — CAN2 transmitter output. (LPC2364/66/68 only)

TXD2 — Transmitter output for UART2.

TRACEPKT3 — Trace Packet, bit 3.

P2[9]/

USB_CONNECT/

RXD2/EXTIN0

P2[9] — General purpose digital input/output pin.

USB_CONNECT — Signal used to switch an external 1.5 k resistor under

software control. Used with the SoftConnect USB feature. (LPC2364/66/68

only)

I

RXD2 — Receiver input for UART2.

I

EXTIN0 — External Trigger Input.

P2[10]/EINT0

53^[6]

J10^[6]

I/O

P2[10] — General purpose digital input/output pin.

Note: LOW on this pin while RESET is LOW forces on-chip bootloader to

take over control of the part after a reset.

I

EINT0 — External interrupt 0 input.

P2[11]/EINT1/

MCIDAT1/

I2STX_CLK

52^[6]

H8^[6]

I/O

I

P2[11] — General purpose digital input/output pin.

EINT1 — External interrupt 1 input.

O

I/O

MCIDAT1 — Data line for SD/MMC interface. (LPC2367/68 only)

I2STX_CLK — Transmit Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S-bus specification.

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Product data sheet

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LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 4.

Symbol

Pin description …continued

Ball

Type Description

P2[12]/EINT2/

MCIDAT2/

I2STX_WS

51^[6]

K10^[6]

I/O

I

P2[12] — General purpose digital input/output pin.

EINT2 — External interrupt 2 input.

O

MCIDAT2 — Data line for SD/MMC interface. (LPC2367/68 only)

I/O

I2STX_WS — Transmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I²S-bus

specification.

P2[13]/EINT3/

MCIDAT3/

I2STX_SDA

50^[6]

J9^[6]

I/O

I

P2[13] — General purpose digital input/output pin.

EINT3 — External interrupt 3 input.

O

MCIDAT3 — Data line for SD/MMC interface. (LPC2367/68 only)

I/O

I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I²S-bus specification.

P3[0] to P3[31]

I/O

Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each

bit. The operation of Port 3 pins depends upon the pin function selected via

the pin connect block. Pins 0 through 24, and 27 through 31 of this port are

not available.

P3[25]/MAT0[0]/ 27^[1]

PWM1[2]

H3^[1]

K1^[1]

I/O

O

P3[25] — General purpose digital input/output pin.

MAT0[0] — Match output for Timer 0, channel 0.

PWM1[2] — Pulse Width Modulator 1, output 2.

P3[26] — General purpose digital input/output pin.

MAT0[1] — Match output for Timer 0, channel 1.

PWM1[3] — Pulse Width Modulator 1, output 3.

O

P3[26]/MAT0[1]/ 26^[1]

PWM1[3]

I/O

O

P4[0] to P4[31]

I/O

Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each

bit. The operation of Port 4 pins depends upon the pin function selected via

the pin connect block. Pins 0 through 27, 30, and 31 of this port are not

available.

P4[28]/MAT2[0]/ 82^[1]

TXD3

C7^[1]

I/O

O

I/O

O

I

P4[28] — General purpose digital input/output pin.

MAT2[0] — Match output for Timer 2, channel 0.

TXD3 — Transmitter output for UART3.

P4[29]/MAT2[1]/ 85^[1]

RXD3

E6^[1]

P4[29] — General purpose digital input/output pin.

MAT2[1] — Match output for Timer 2, channel 1.

RXD3 — Receiver input for UART3.

DBGEN

-

D4^[1][8]

I

DBGEN — JTAG interface control signal. Also used for boundary scanning.

Note: This pin is available in LPC2364FET100 and LPC2368FET100

devices only (TFBGA package).

TDO

TDI

1^[1][7]

2^[1][8]

3^[1][8]

4^[1][8]

5^[1][7]

A1^[1][7]

C3^[1][8]

B1^[1][8]

C2^[1][8]

C1^[1][7]

O

I

TDO — Test Data out for JTAG interface.

TDI — Test Data in for JTAG interface.

TMS — Test Mode Select for JTAG interface.

TRST — Test Reset for JTAG interface.

TMS

TRST

TCK

I

TCK — Test Clock for JTAG interface. This clock must be slower than ¹⁄₆of

the CPU clock (CCLK) for the JTAG interface to operate

RTCK

100^[1][8]B2^[1][8]

I/O

RTCK — JTAG interface control signal.

Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to

operate as trace port after reset.

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Product data sheet

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LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 4.

Symbol

RSTOUT

Pin description …continued

Ball

Type Description

O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates

LPC2364/65/66/67/68 being in Reset state.

14

-

Note: This pin is available in LPC2364FBD100, LPC2365FBD100,

LPC2366FBD100, LPC2367FBD100, and LPC2368FBD100 devices only

(LQFP100 package).

RESET

17^[9]

F3^[9]

I

External reset input: A LOW on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

RTCX1

RTCX2

V_SS

22^[10][11]H2^[10][11]

23^[10][11]G3^[10][11]

16^[10][12]F2^[10][12]

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator amplifier.

O

I

Input to the RTC oscillator circuit.

18^[10]

G1^[10]

O

I

Output from the RTC oscillator circuit.

ground: 0 V reference.

15, 31,

41, 55,

72, 97,

83^[13]

B3, B7,

C9, F1,

G7, J6,

K3 ^[13]

V_SSA

11^[14]

E1^[14]

I

analog ground: 0 V reference. This should nominally be the same voltage

as V_SS, but should be isolated to minimize noise and error.

V_DD(3V3)

28, 54,

71,

96^[15]

A3,C10, I

H9,

K2^[15]

3.3 V supply voltage: This is the power supply voltage for the I/O ports.

V_{DD(DCDC)(3V3)}

V_DDA

13, 42,

84^[16]

A7, E4,

H6^[16]

I

3.3 V DC-to-DC converter supply voltage: This is the supply voltage for

the on-chip DC-to-DC converter only.

10^[17]

12^[17]

19^[17]

E2^[17]

E3^[17]

G2^[17]

analog 3.3 V pad supply voltage: This should be nominally the same

voltage as V_DD(3V3)but should be isolated to minimize noise and error. This

voltage is used to power the ADC and DAC.

VREF

VBAT

I

ADC reference: This should be nominally the same voltage as V_DD(3V3)but

should be isolated to minimize noise and error. Level on this pin is used as

a reference for ADC and DAC.

RTC pin power supply: 3.3 V on this pin supplies the power to the RTC

peripheral.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,

digital section of the pad is disabled.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4] Open-drain 5 V tolerant digital I/O pad, compatible with I²C-bus 400 kHz specification. This pad requires an external pull-up to provide

output functionality. When power is switched off, this pin connected to the I²C-bus is floating and does not disturb the I²C lines.

Open-drain configuration applies to all functions on this pin.

[5] Pad provides digital I/O and USB functions (LPC2364/66/68 only). It is designed in accordance with the USB specification, revision 2.0

(Full-speed and Low-speed mode only).

[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7] This pin has no built-in pull-up and no built-in pull-down resistor.

[8] This pin has a built-in pull-up resistor.

[9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[10] Pad provides special analog functionality.

[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

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Product data sheet

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LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

[12] If the RTC is not used, these pins can be left floating.

[13] Pad provides special analog functionality.

[14] Pad provides special analog functionality.

[15] Pad provides special analog functionality.

[16] Pad provides special analog functionality.

[17] Pad provides special analog functionality.

7. Functional description

7.1 Architectural overview

The LPC2364/65/66/67/68 microcontroller consists of an ARM7TDMI-S CPU with

emulation support, the ARM7 local bus for closely coupled, high-speed access to the

majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals,

and the AMBA APB for connection to other on-chip peripheral functions. The

microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte

order.

The LPC2364/65/66/67/68 implements two AHB in order to allow the Ethernet block to

operate without interference caused by other system activity. The primary AHB, referred

to as AHB1, includes the VIC and GPDMA controller.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,

and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2

are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB

ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the

AHB address space. Lower speed peripheral functions are connected to the APB. The

AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a

2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is

allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers

high performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed complex

instruction set computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

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The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set

• A 16-bit Thumb set

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

7.2 On-chip flash programming memory

The LPC2364/65/66/67/68 incorporate a 128 kB, 256 kB, and 512 kB flash memory

system respectively. This memory may be used for both code and data storage.

Programming of the flash memory may be accomplished in several ways. It may be

programmed In System via the serial port (UART0). The application program may also

erase and/or program the flash while the application is running, allowing a great degree of

flexibility for data storage field and firmware upgrades.

The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to

allow it to operate at SRAM speeds of 72 MHz. LPC2364HBD flash operates up to

72 MHz from 40 C to +85 C, up to 60 MHz from 85 C to 125 C.

7.3 On-chip SRAM

The LPC2364/65/66/67/68 include SRAM memory of 8 kB or 32 kB, reserved for the ARM

processor exclusive use. This RAM may be used for code and/or data storage and may

be accessed as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and an 8 kB SRAM

used by the GPDMA controller or the USB device can be used both for data and code

storage. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is

battery powered and retains the content in the absence of the main power supply.

7.4 Memory map

The LPC2364/65/66/67/68 memory map incorporates several distinct regions as shown in

Figure 4.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either

flash memory (default), boot ROM, or SRAM (see Section 7.25.6).

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4.0 GB

0xFFFF FFFF

AHB PERIPHERALS

0xF000 0000

0xE000 0000

3.75 GB

APB PERIPHERALS

3.5 GB

3.0 GB

0xC000 0000

RESERVED ADDRESS SPACE

2.0 GB

0x8000 0000

BOOT ROM AND BOOT FLASH

(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)

RESERVED ADDRESS SPACE

ETHERNET RAM (16 kB)

0x7FE0 3FFF

0x7FE0 0000

0x7FD0 1FFF

0x7FD0 0000

GENERAL PURPOSE OR USB RAM (8 KB)

RESERVED ADDRESS SPACE

0x4000 8000

0x4000 7FFF

32 kB LOCAL ON-CHIP STATIC RAM (LPC2365/66/67/68)

8 kB LOCAL ON-CHIP STATIC RAM (LPC2364)

0x4000 2000

0x4000 1FFF

1.0 GB

0x4000 0000

RESERVED FOR ON-CHIP MEMORY

0x0008 0000

0x0007 FFFF

0x0004 0000

0x0003 FFFF

0x0002 0000

0x0001 FFFF

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2367/68)

TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2365/66)

TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2364)

0.0 GB

0x0000 0000

002aac577

Fig 4. LPC2364/65/66/67/68 memory map

7.5 Interrupt controller

The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast

Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be

programmed as FIQ or vectored IRQ types. The programmable assignment scheme

means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

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FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs

the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ

latency is achieved when only one request is classified as FIQ, because then the FIQ

service routine can simply start dealing with that device. But if more than one request is

assigned to the FIQ class, the FIQ service routine can read a word from the VIC that

identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a

programmable interrupt priority. When more than one interrupt is assigned the same

priority and occur simultaneously, the one connected to the lowest numbered VIC channel

will be serviced first.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the

ARM processor. The IRQ service routine can start by reading a register from the VIC and

jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be

programmed to generate an interrupt on a rising edge, a falling edge, or both. Such

interrupt request coming from Port 0 and/or Port 2 will be combined with the EINT3

interrupt requests.

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected

LPC2364/65/66/67/68 peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receive. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the AHB master.

7.7.1 Features

• Two DMA channels. Each channel can support a unidirectional transfer.

• The GPDMA can transfer data between the 8 kB SRAM and peripherals such as the

SD/MMC, two SSP, and I²S interfaces.

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• Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If

requests from two channels become active at the same time the channel with the

highest priority is serviced first.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the

DMA control registers over the AHB slave interface.

• One AHB master for transferring data. This interface transfers data when a DMA

request goes active.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the

peripheral.

• Internal four-word FIFO per channel.

• Supports 8-bit, 16-bit, and 32-bit wide transactions.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.8 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

LPC2364/65/66/67/68 use accelerated GPIO functions:

• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

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Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can

be programmed to generate an interrupt on a rising edge, a falling edge, or both. The

edge detection is asynchronous, so it may operate when clocks are not present such as

during Power-down mode. Each enabled interrupt can be used to wake up the chip from

Power-down mode.

7.8.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy Port 0 and

Port 1 registers appearing at the original addresses on the APB.

7.9 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, flow control, control frames, hardware acceleration for transmit retry, receive

packet filtering and wake-up on LAN activity. Automatic frame transmission and reception

with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access

the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic

in the LPC2364/65/66/67/68 takes place on a different AHB subsystem, effectively

separating Ethernet activity from the rest of the system. The Ethernet DMA can also

access the USB SRAM if it is not being used by the USB block.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII

(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial

bus.

7.9.1 Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.

– Flexible transmit and receive frame options.

– Virtual Local Area Network (VLAN) frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

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– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

• Physical interface:

– Attachment of external PHY chip through standard RMII interface.

– PHY register access is available via the MIIM interface.

7.10 USB interface (LPC2364/66/68 only)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and a number (127 maximum) of peripherals. The host controller allocates the USB

bandwidth to attached devices through a token based protocol. The bus supports hot

plugging, unplugging, and dynamic configuration of the devices. All transactions are

initiated by the host controller.

7.10.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of register interface, serial interface engine, endpoint buffer memory, and the

DMA controller. The serial interface engine decodes the USB data stream and writes data

to the appropriate end point buffer memory. The status of a completed USB transfer or

error condition is indicated via status registers. An interrupt is also generated if enabled.

The DMA controller when enabled transfers data between the endpoint buffer and the

USB RAM.

7.10.2 Features

• Fully compliant with USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB USB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

• While USB is in the Suspend mode, LPC2364/65/66/67/68 can enter one of the

reduced power modes and wake up on a USB activity.

• Supports DMA transfers with the DMA RAM of 8 kB on all non-control endpoints.

• Allows dynamic switching between CPU-controlled and DMA modes.

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• Double buffer implementation for Bulk and Isochronous endpoints.

7.11 CAN controller and acceptance filters (LPC2364/66/68 only)

The Controller Area Network (CAN) is a serial communications protocol which efficiently

supports distributed real-time control with a very high level of security. Its domain of

application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a gateway, switch, or router among a number of CAN buses in

industrial or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN

Library block, but the 8-bit registers of those devices have been combined in 32-bit words

to allow simultaneous access in the ARM environment. The main operational difference is

that the recognition of received Identifiers, known in CAN terminology as Acceptance

Filtering, has been removed from the CAN controllers and centralized in a global

Acceptance Filter.

7.11.1 Features

• Two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN

buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identifiers.

• FullCAN messages can generate interrupts.

7.12 10-bit ADC

The LPC2364/65/66/67/68 contain one ADC. It is a single 10-bit successive

approximation ADC with six channels.

7.12.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 6 pins.

• Power-down mode.

• Measurement range 0 V to V_i(VREF)

.

• 10-bit conversion time  2.44 s.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or Timer Match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

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7.13 10-bit DAC

The DAC allows the LPC2364/65/66/67/68 to generate a variable analog output. The

maximum output value of the DAC is V_i(VREF)

.

7.13.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

7.14 UARTs

The LPC2364/65/66/67/68 each contain four UARTs. In addition to standard transmit and

receive data lines, UART1 also provides a full modem control handshake interface.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.14.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

• UART3 includes an IrDA mode to support infrared communication.

7.15 SPI serial I/O controller

The LPC2364/65/66/67/68 each contain one SPI controller. SPI is a full duplex serial

interface designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the

slave, and the slave always sends 8 bits to 16 bits of data to the master.

7.15.1 Features

• Compliant with SPI specification

• Synchronous, serial, full duplex communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

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7.16 SSP serial I/O controller

The LPC2364/65/66/67/68 each contain two SSP controllers. The SSP controller is

capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple

masters and slaves on the bus. Only a single master and a single slave can communicate

on the bus during a given data transfer. The SSP supports full duplex transfers, with

frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave

to the master. In practice, often only one of these data flows carries meaningful data.

7.16.1 Features

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.17 SD/MMC card interface (LPC2367/68 only)

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD

memory cards. The SD card interface conforms to the SD Multimedia Card Specification

Version 2.11.

7.17.1 Features

• The MCI interface provides all functions specific to the SD/MMC memory card. These

include the clock generation unit, power management control, and command and data

transfer.

• Conforms to Multimedia Card Specification v2.11.

• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

• Can be used as a multimedia card bus or a secure digital memory card bus host. The

SD/MMC can be connected to several multimedia cards or a single secure digital

memory card.

• DMA supported through the GPDMA controller.

7.18 I²C-bus serial I/O controllers

The LPC2364/65/66/67/68 each contain three I²C-bus controllers.

The I²C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I²C-bus implemented in LPC2364/65/66/67/68 supports bit rates up to 400 kbit/s

(Fast I²C-bus).

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7.18.1 Features

• I²C0 is a standard I²C compliant bus interface with open-drain pins.

• I²C1 and I²C2 use standard I/O pins and do not support powering off of individual

devices connected to the same bus lines.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

7.19 I²S-bus serial I/O controllers

The I²S-bus provides a standard communication interface for digital audio applications.

The I²S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I²S connection has one master, which is always the

master, and one slave. The I²S interface on the LPC2364/65/66/67/68 provides a

separate transmit and receive channel, each of which can operate as either a master or a

slave.

7.19.1 Features

• The interface has separate input/output channels each of which can operate in master

or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,

48) kHz.

• Configurable word select period in master mode (separately for I²S input and output).

• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

to the GPDMA block.

• Controls include reset, stop and mute options separately for I²S input and I²S output.

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7.20 General purpose 32-bit timers/external event counters

The LPC2364/65/66/67/68 include four 32-bit Timer/Counters. The Timer/Counter is

designed to count cycles of the system derived clock or an externally-supplied clock. It

can optionally generate interrupts or perform other actions at specified timer values,

based on four match registers. The Timer/Counter also includes two capture inputs to trap

the timer value when an input signal transitions, optionally generating an interrupt.

7.20.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

• Counter or Timer operation.

• Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.21 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2364/65/66/67/68. The Timer is designed

to count cycles of the system derived clock and optionally switch pins, generate interrupts

or perform other actions when specified timer values occur, based on seven match

registers. The PWM function is in addition to these features, and is based on match

register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

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Three match registers can be used to provide a PWM output with both edges controlled.

Again, the PWMMR0 match register controls the PWM cycle rate. The other match

registers control the two PWM edge positions. Additional double edge controlled PWM

outputs require only two match registers each, since the repetition rate is the same for all

PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

7.21.1 Features

• LPC2364/65/66/67/68 has one PWM block with Counter or Timer operation (may use

the peripheral clock or one of the capture inputs as the clock source).

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the

output is a constant low. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

7.22 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.22.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

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• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2³² 4) in

multiples of T_cy(WDCLK) 4.

• The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the

Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of

potential timing choices of Watchdog operation under different power reduction

conditions. It also provides the ability to run the WDT from an entirely internal source

that is not dependent on an external crystal and its associated components and

wiring, for increased reliability.

7.23 RTC and battery RAM

The RTC is a set of counters for measuring time when system power is on, and optionally

when it is off. It uses little power in Power-down and Deep power-down modes. On the

LPC2364/65/66/67/68, the RTC can be clocked by a separate 32.768 kHz oscillator, or by

a programmable prescale divider based on the APB clock. Also, the RTC is powered by its

own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V

supply used by the rest of the device.

The VBAT pin supplies power only to the RTC and the battery RAM. These two functions

require a minimum of power to operate, which can be supplied by an external battery.

7.23.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

• Dedicated 32 kHz oscillator or programmable prescaler from APB clock.

• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

• Periodic interrupts can be generated from increments of any field of the time registers,

and selected fractional second values.

• 2 kB data SRAM powered by VBAT.

• RTC and battery RAM power supply is isolated from the rest of the chip.

7.24 Clocking and power control

7.24.1 Crystal oscillators

The LPC2364/65/66/67/68 includes three independent oscillators. These are the Main

Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used

for more than one purpose as required in a particular application. Any of the three clock

sources can be chosen by software to drive the PLL and ultimately the CPU.

Following reset, the LPC2364/65/66/67/68 will operate from the Internal RC oscillator until

switched by software. This allows systems to operate without any external crystal and the

bootloader code to operate at a known frequency.

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7.24.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is

trimmed to 1 % accuracy.

Upon power-up or any chip reset, the LPC2364/65/66/67/68 uses the IRC as the clock

source. Software may later switch to one of the other available clock sources.

7.24.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using the

PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can

be boosted to a higher frequency, up to the maximum CPU operating frequency, by the

PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock

frequency is referred to as CCLK elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The

clock frequency for each peripheral can be selected individually and is referred to as

PCLK. Refer to Section 7.24.2 for additional information.

7.24.1.3 RTC oscillator

The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the

RTC oscillator can be used to drive the PLL and the CPU.

7.24.2 PLL

The PLL accepts an input clock frequency in the range of 32 kHz to 50 MHz. The input

frequency is multiplied up to a high frequency, then divided down to provide the actual

clock used by the CPU and the USB block. The USB block is available in LPC2364/66/68

only.

The PLL input, in the range of 32 kHz to 50 MHz, may initially be divided down by a value

‘N’, which may be in the range of 1 to 256. This input division provides a wide range of

output frequencies from the same input frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the

range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to

550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a

phase-frequency detector to compare the divided CCO output to the multiplier input. The

error value is used to adjust the CCO frequency.

The PLL is turned off and bypassed following a chip Reset and by entering Power-down

mode. PLL is enabled by software only. The program must configure and activate the PLL,

wait for the PLL to Lock, then connect to the PLL as a clock source.

7.24.3 Wake-up timer

The LPC2364/65/66/67/68 begins operation at power-up and when awakened from

Power-down and Deep power-down modes by using the 4 MHz IRC oscillator as the clock

source. This allows chip operation to resume quickly. If the main oscillator or the PLL is

needed by the application, software will need to enable these features and wait for them

to stabilize before they are used as a clock source.

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When the main oscillator is initially activated, the wake-up timer allows software to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down and Deep-power down

modes, any wake-up of the processor from Power-down mode makes use of the wake-up

Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some event caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufficient amplitude to drive the clock logic. The amount of time depends on many factors,

including the rate of V_DD(3V3)ramp (in the case of power on), the type of crystal and its

electrical characteristics (if a quartz crystal is used), as well as any other external circuitry

(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.24.4 Power control

The LPC2364/65/66/67/68 supports a variety of power control features. There are four

special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode,

and Deep power-down mode. The CPU clock rate may also be controlled as needed by

changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider

value. This allows a trade-off of power versus processing speed based on application

requirements. In addition, Peripheral Power Control allows shutting down the clocks to

individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all

dynamic power use in any peripherals that are not required for the application. Each of the

peripherals has its own clock divider which provides even better power control.

The LPC2364/65/66/67/68 also implements a separate power domain in order to allow

turning off power to the bulk of the device while maintaining operation of the RTC and a

small SRAM, referred to as the battery RAM.

7.24.4.1 Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.24.4.2 Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The

processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Sleep mode and the logic levels of chip pins remain static. The

output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The

32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The CCLK and

USB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset or

certain specific interrupts that are able to function without clocks. Since all dynamic

operation of the chip is suspended, Sleep mode reduces chip power consumption to a

very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.

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On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the

code execution and peripherals activities will resume after 4 cycles expire. If the main

external oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconfigure the PLL and clock dividers accordingly.

7.24.4.3 Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRC

oscillator and the flash memory. This saves more power, but requires waiting for

resumption of flash operation before execution of code or data access in the flash memory

can be accomplished.

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. In the meantime, the

flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up

time. When it times out, access to the flash will be allowed. The customers need to

reconfigure the PLL and clock dividers accordingly.

7.24.4.4 Deep power-down mode

Deep power-down mode is similar to the Power-down mode, but now the on-chip

regulator that supplies power to the internal logic is also shut off. This produces the lowest

possible power consumption without removing power from the entire chip. Since the Deep

power-down mode shuts down the on-chip logic power supply, there is no register or

memory retention, and resumption of operation involves the same activities as a full chip

reset.

If power is supplied to the LPC2364/65/66/67/68 during Deep power-down mode,

wake-up can be caused by the RTC Alarm interrupt or by external Reset.

While in Deep power-down mode, external device power may be removed. In this case,

the LPC2364/65/66/67/68 will start up when external power is restored.

Essential data may be retained through Deep power-down mode (or through complete

powering off of the chip) by storing data in the Battery RAM, as long as the external power

to the VBAT pin is maintained.

7.24.4.5 Power domains

The LPC2364/65/66/67/68 provides two independent power domains that allow the bulk

of the device to have power removed while maintaining operation of the RTC and the

battery RAM.

On the LPC2364/65/66/67/68, I/O pads are powered by the 3.3 V (V_DD(3V3)) pins, while

the V_{DD(DCDC)(3V3)}pin powers the on-chip DC-to-DC converter which in turn provides

power to the CPU and most of the peripherals.

Depending on the LPC2364/65/66/67/68 application, a design can use two power options

to manage power consumption.

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The first option assumes that power consumption is not a concern and the design ties the

_DD(3V3)and V_{DD(DCDC)(3V3)}pins together. This approach requires only one 3.3 V power

V

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (V_DD(3V3)) and

a dedicated 3.3 V supply for the CPU (V_{DD(DCDC)(3V3)}). Having the on-chip DC-to-DC

converter powered independently from the I/O pad ring enables shutting down of the I/O

pad power supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC and the battery RAM. These two functions

require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC

can supply an alarm output that may be used by external hardware to restore chip power

and resume operation.

7.25 System control

7.25.1 Reset

Reset has four sources on the LPC2364/65/66/67/68: the RESET pin, the Watchdog

reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating

voltage attains a usable level, starts the Wake-up timer (see description in Section 7.24.3

“Wake-up timer”), causing reset to remain asserted until the external Reset is

de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash

controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.25.2 Brownout detection

The LPC2364/65/66/67/68 includes 2-stage monitoring of the voltage on the

_{DD(DCDC)(3V3)}pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal

V

to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt

Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor

the signal by reading a dedicated status register.

The second stage of low-voltage detection asserts Reset to inactivate the

LPC2364/65/66/67/68 when the voltage on the V_{DD(DCDC)(3V3)}pins falls below 2.65 V. This

Reset prevents alteration of the flash as operation of the various elements of the chip

would otherwise become unreliable due to low voltage. The BOD circuit maintains this

reset down below 1 V, at which point the power-on reset circuitry maintains the overall

Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

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7.25.3 Code security (Code Read Protection - CRP)

This feature of the LPC2364/65/66/67/68 allows user to enable different levels of security

in the system so that access to the on-chip flash and use of the JTAG and ISP can be

restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

7.25.4 AHB

The LPC2364/65/66/67/68 implement two AHBs in order to allow the Ethernet block to

operate without interference caused by other system activity. The primary AHB, referred

to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface,

and 8 kB SRAM primarily intended for use by the USB. The USB interface is available on

LPC2364/66/68 only.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the

GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters

with access to AHB2 are the ARM7 and the Ethernet block.

7.25.5 External interrupt inputs

The LPC2364/65/66/67/68 include up to 46 edge sensitive interrupt inputs combined with

up to four level sensitive external interrupt inputs as selectable pin functions. The external

interrupt inputs can optionally be used to wake up the processor from Power-down mode.

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7.25.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear at the

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot

ROM or the SRAM. This allows code running in different memory spaces to have control

of the interrupts.

7.26 Emulation and debugging

The LPC2364/65/66/67/68 support emulation and debugging via a JTAG serial port. A

trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer,

and interface peripherals residing on other pins are available during the development and

debugging phase as they are when the application is run in the embedded system itself.

7.26.1 EmbeddedICE

The EmbeddedICE logic provides on-chip debug support. The debugging of the target

system requires a host computer running the debugger software and an EmbeddedICE

protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug

Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present

on the target system.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC

allows a program running on the target to communicate with the host debugger or another

separate host without stopping the program flow or even entering the debug state. The

DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core.

The DCC allows the JTAG port to be used for sending and receiving data without affecting

the normal program flow. The DCC data and control registers are mapped in to addresses

in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than ¹⁄₆of the CPU clock (CCLK) for the JTAG

interface to operate.

7.26.2 Embedded trace

Since the LPC2364/65/66/67/68 have significant amounts of on-chip memories, it is not

possible to determine how the processor core is operating simply by observing the

external pins. The ETM provides real-time trace capability for deeply embedded

processor cores. It outputs information about processor execution to a trace port. A

software debugger allows configuration of the ETM using a JTAG interface and displays

the trace information that has been captured.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

Trace Port Analyzer captures the trace information under software debugger control. The

trace port can broadcast the Instruction trace information. Instruction trace (or PC trace)

shows the flow of execution of the processor and provides a list of all the instructions that

were executed. Instruction trace is significantly compressed by only broadcasting branch

addresses as well as a set of status signals that indicate the pipeline status on a cycle by

cycle basis. Trace information generation can be controlled by selecting the trigger

resource. Trigger resources include address comparators, counters and sequencers.

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Since trace information is compressed the software debugger requires a static image of

the code being executed. Self-modifying code can not be traced because of this

restriction.

7.26.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2364/65/66/67/68 contain a specific

configuration of RealMonitor software programmed into the on-chip ROM memory.

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8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

Parameter

Conditions

Min

Max

Unit

V_DD(3V3)

supply voltage (3.3 V)

core and external

rail

3.0

3.6

V

V_{DD(DCDC)(3V3)}DC-to-DC converter supply voltage

(3.3 V)

3.0

3.6

V

V_DDA

analog 3.3 V pad supply voltage

input voltage on pin VBAT

input voltage on pin VREF

analog input voltage

0.5

+4.6

+5.1

V

V_i(VBAT)

V_i(VREF)

V_IA

for the RTC

on ADC related

pins

[2]

V_I

input voltage

5 V tolerant I/O

pins; only valid

when the V_DD(3V3)

supply voltage is

present

0.5

+6.0

V

[2][3]

other I/O pins

0.5

V_DD(3V3)

0.5

+

V

[4]

[5]

I_DD

supply current

per supply pin

per ground pin

non-operating

-

100

+150

1.5

mA

C

I_SS

ground current

-

T_stg

storage temperature

total power dissipation (per package)

65

P_tot(pack)

based on package

heat transfer, not

device power

-

W

consumption

[6]

V_ESD

electrostatic discharge voltage

human body

2500

+2500

V

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

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9. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T_j= T_amb+ P_D R_{thj – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 6.

Thermal characteristics

V_DD= 3.0 V to 3.6 V; T_amb= 40 C to +85 C unless otherwise specified;

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_j(max)

maximum junction

temperature

-

125

C

Table 7.

Thermal resistance value (C/W): ±15 %

V_DD= 3.0 V to 3.6 V; T_amb= 40 C to +85 C unless otherwise specified;

LQFP100

TFBGA100

ja

JEDEC (4.5 in  4 in)

0 m/s

37.3

32.2

29.5

0 m/s

53.9

45.5

39.5

1 m/s

2.5 m/s

Single-layer (4.5 in  3 in)

8-layer (4.5 in  3 in)

0 m/s

1 m/s

2.5 m/s

jc

54.4

42.9

38.8

6.7

0 m/s

1 m/s

2.5 m/s

jc

44.3

39.2

34.2

9.4

jb

12

jb

10.8

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10. Static characteristics

Table 8.

Static characteristics

T_amb= 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified.

Symbol

Parameter

Conditions

Min

3.0

Typ^[1]

3.3

Max

3.6

Unit

V

V_DD(3V3)

supply voltage (3.3 V)

core and external rail

V_{DD(DCDC)(3V3)}

DC-to-DC converter

supply voltage (3.3 V)

3.3

3.6

V

V_DDA

analog 3.3 V pad supply

voltage

3.0

2.0

2.5

3.3

3.6

V

[2]

V_i(VBAT)

V_i(VREF)

input voltage on pin

VBAT

3.6

input voltage on pin

VREF

V_DDA

I_{DD(DCDC)act(3V3)}active mode DC-to-DC V_{DD(DCDC)(3V3)}= 3.3 V;

converter supply

current (3.3 V)

T_amb= 25 C; code

while(1){}

executed from flash; no

peripherals enabled;

PCLK = CCLK

CCLK = 10 MHz

CCLK = 72 MHz

-

15

63

-

mA

all peripherals enabled;

PCLK = CCLK / 8

CCLK = 10 MHz

CCLK = 72 MHz

-

21

92

-

mA

all peripherals enabled;

PCLK = CCLK

CCLK = 10 MHz

CCLK = 72 MHz

-

27

-

mA

A

125

113

[3]

I_{DD(DCDC)pd(3V3)}Power-down mode

DC-to-DC converter

V_{DD(DCDC)(3V3)}= 3.3 V;

T_amb= 25 C

supply current (3.3 V)

I_{DD(DCDC)dpd(3V3)}Deep power-down

mode DC-to-DC

converter supply

current (3.3 V)

-

20

-

A

[4]

[3]

I_BATact

I_BAT

active mode battery

supply current

-

20

-

A

battery supply current

Deep power-down mode

Standard port pins, RESET, RTCK

I_IL

LOW-level input current V_I= 0 V; no pull-up

-

3

A

I_IH

HIGH-level input

current

V_I= V_DD(3V3); no

pull-down

I_OZ

OFF-state output

current

V_O= 0 V; V_O= V_DD(3V3)

no pull-up/down

;

-

3

A

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Single-chip 16-bit/32-bit microcontrollers

Table 8.

Static characteristics …continued

T_amb= 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_latch

I/O latch-up current

(0.5V_DD(3V3)) < V_I<

-

100

mA

(1.5V_DD(3V3));

T_j< 125 C

[5][6]

[7][8]

V_I

input voltage

pin configured to provide

a digital function

0

-

5.5

V

V_O

output voltage

output active

0

-

V_DD(3V3)

-

V

V_IH

HIGH-level input

voltage

2.0

V_IL

LOW-level input voltage

hysteresis voltage

-

0.8

V

V_hys

V_OH

0.4

-

[9]

HIGH-level output

voltage

I_OH= 4 mA

V_DD(3V3)

0.4



V_OL

I_OH

LOW-level output

voltage

I_OL= 4 mA

-

0.4

-

V

[9]

HIGH-level output

current

V_OH= V_DD(3V3) 0.4 V

V_OL= 0.4 V

4

4

-

mA

[9]

I_OL

LOW-level output

current

-

[10]

[11]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

45

50

LOW-level short-circuit V_OL= V_DDA

output current

-

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

50

150

85

100

0

A

V_I= 0 V; 40 C to +85 C

V_I= 0 V; > 85 C

V_DD(3V3)< V_I< 5 V

15

0

50

0

[12]

[11]

I²C-bus pins (P0[27] and P0[28])

V_IH

HIGH-level input

voltage

0.7V_DD(3V3)

-

V

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD(3V3)

V

V_hys

V_OL

0.05V_DD(3V3)

-

[9]

LOW-level output

voltage

I_OLS= 3 mA

0.4

[13]

I_LI

input leakage current

V_I= V_DD(3V3)

V_I= 5 V

-

2

4

A

10

22

Oscillator pins

V_i(XTAL1)

input voltage on pin

XTAL1

0.5

1.8

1.95

V

V_o(XTAL2)

V_i(RTCX1)

V_o(RTCX2)

output voltage on pin

XTAL2

input voltage on pin

RTCX1

output voltage on pin

RTCX2

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Single-chip 16-bit/32-bit microcontrollers

Table 8.

Static characteristics …continued

T_amb= 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

USB pins (LPC2364/66/68 only)

I_OZ

OFF-state output

current

0 V < V_I< 3.3 V

-

10

A

V_BUS

V_DI

bus supply voltage

-

5.25

-

V

differential input

(D+)  (D)

0.2

sensitivity voltage

V_CM

differential common

mode voltage range

includes V_DIrange

0.8

-

2.5

2.0

V

V_th(rs)se

single-ended receiver

switching threshold

voltage

V_OL

LOW-level output

voltage for

low-/full-speed

R_Lof 1.5 k to 3.6 V

R_Lof 15 k to GND

-

0.18

3.5

V

V_OH

HIGH-level output

voltage (driven) for

low-/full-speed

2.8

C_trans

Z_DRV

transceiver capacitance pin to GND

-

20

pF

[14]

driver output

with 33  series resistor;

steady state drive

36

44.1



impedance for driver

which is not high-speed

capable

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] The RTC typically fails when V_i(VBAT)drops below 1.6 V.

[3] V_{DD(DCDC)(3V3)}= 3.3 V; V_DD(3V3)= 3.3 V; V_i(VBAT)= 3.3 V; T_amb= 25 C.

[4] On pin VBAT.

[5] Including voltage on outputs in 3-state mode.

[6]

V_DD(3V3)supply voltages must be present.

[7] 3-state outputs go into 3-state mode when V_DD(3V3)is grounded.

[8] Please also see the errata note in errata sheet.

[9] Accounts for 100 mV voltage drop in all supply lines.

[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[11] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[12] LPC2364HBD only.

[13] To V_SS

.

[14] Includes external resistors of 33   1 % on D+ and D.

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Single-chip 16-bit/32-bit microcontrollers

10.1 Power-down mode

002aae049

4

I

DD(IO)

(μA)

2

0

V

= 3.3 V

= 3.0 V

DD(3V3)

V

DD(3V3)

−2

−4

−40

−15

10

35

60

85

temperature (°C)

V_i(VBAT)= V_{DD(DCDC)(3V3)}= 3.3 V; T_amb= 25 C.

Fig 5. I/O maximum supply current I_DD(IO)versus temperature in Power-down mode

002aae050

40

I

BAT

(μA)

30

V

= 3.3 V

= 3.0 V

i(VBAT)

V

i(VBAT)

20

10

0

−40

−15

10

35

60

85

temperature (°C)

V_DD(3V3)= V_{DD(DCDC)(3V3)}= 3.3 V; T_amb= 25 C.

Fig 6. RTC battery maximum supply current I_BATversus temperature in Power-down

mode

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Single-chip 16-bit/32-bit microcontrollers

002aae051

800

I

DD(DCDC)pd(3v3)

(μA)

600

400

200

V

= 3.3 V

= 3.0 V

DD(DCDC)(3V3)

V

DD(DCDC)(3V3)

0

−40

−15

10

35

60

85

temperature (°C)

V_DD(3V3)= V_i(VBAT)= 3.3 V; T_amb= 25 C.

Fig 7. Total DC-to-DC converter supply current I_{DD(DCDC)pd(3V3)}at different temperatures

in Power-down mode

10.2 Deep power-down mode

002aae046

300

I

DD(IO)

(μA)

200

100

0

V

= 3.3 V

= 3.0 V

DD(3V3)

−40

−15

10

35

60

85

temperature (°C)

V_DD(3V3)= V_{DD(DCDC)(3V3)}= 3.3 V; T_amb= 25 C.

Fig 8. I/O maximum supply current I_DD(IO)versus temperature in Deep power-down

mode

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Single-chip 16-bit/32-bit microcontrollers

002aae047

40

I

BAT

(μA)

30

V

= 3.3 V

= 3.0 V

i(VBAT)

20

10

0

−40

−15

10

35

60

85

temperature (°C)

V_DD(3V3)= V_{DD(DCDC)(3V3)}= 3.3 V; T_amb= 25 C

Fig 9. RTC battery maximum supply current I_BATversus temperature in Deep

power-down mode

002aae048

100

I

DD(DCDC)dpd(3v3)

(μA)

80

60

V

= 3.3 V

= 3.0 V

DD(DCDC)(3V3)

40

20

0

V

DD(DCDC)(3V3)

−40

−15

10

35

60

85

temperature (°C)

V_DD(3V3)= V_i(VBAT)= 3.3 V; T_amb= 25 C.

Fig 10. Total DC-to-DC converter maximum supply current I_{DD(DCDC)dpd(3V3)}versus

temperature in Deep power-down mode

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Single-chip 16-bit/32-bit microcontrollers

10.3 Electrical pin characteristics

002aaf112

3.6

V

OH

(V)

T = 85 °C

25 °C

−40 °C

3.2

2.8

2.4

2.0

0

8

16

24

I

(mA)

OH

Conditions: V_DD(3V3)= 3.3 V; standard port pins.

Fig 11. Typical HIGH-level output voltage V_OHversus HIGH-level output source current

I_OH

002aaf111

15

I

OL

T = 85 °C

25 °C

−40 °C

(mA)

10

5

0

0.2

0.4

0.6

V

(V)

OL

Conditions: V_DD(3V3)= 3.3 V; standard port pins.

Fig 12. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

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Single-chip 16-bit/32-bit microcontrollers

11. Dynamic characteristics

Table 9.

_amb= 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified; V_DD(3V3)

over specified ranges.^[1]

Dynamic characteristics

T

Symbol

Parameter

Conditions

Min

Typ^[2]

Max

Unit

ARM processor clock frequency

f_oper

operating frequency

CCLK; 40 C to +85 C

CCLK; > 85 C

1

-

72

MHz

[3]

1

-

60

IRC; 40 C to +85 C

IRC; > 85 C

3.96

3.98

4

4.04

4.06

4.02

External clock

f_osc

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

1

-

25

MHz

ns

T_cy(clk)

t_CHCX

40

1000

T_cy(clk) 0.4

-

ns

t_CLCX

T_cy(clk) 0.4

-

ns

t_CLCH

-

5

ns

t_CHCL

clock fall time

ns

I²C-bus pins (P0[27] and P0[28])

[4]

t_f(o)

output fall time

V_IHto V_IL

20 + 0.1  C_b

-

ns

SSP interface

t_{su(SPI_MISO)}

SPI_MISO set-up time

T_amb= 25 C; measured

in SPI Master mode; see

Figure 15

-

11

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[3] LPC2364HBD only.

[4] Bus capacitance C_bin pF, from 10 pF to 400 pF.

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 13. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

11.1 Internal oscillators

Table 10. Dynamic characteristic: internal oscillators

T_amb= 40 C to +85 C; 3.0 V  V_DD(3V3) 3.6 V.^[1]

Symbol

f_osc(RC)

f_i(RTC)

Parameter

Conditions

Min

3.96

-

Typ^[2]

4.02

Max

4.04

-

Unit

MHz

kHz

internal RC oscillator frequency

RTC input frequency

-

32.768

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

11.2 I/O pins

Table 11. Dynamic characteristic: I/O pins^[1]

T_amb= 40 C to +85 C; V_DD(3V3)over specified ranges.

Symbol

Parameter

rise time

fall time

Conditions

Min

3.0

2.5

Typ

Max

Unit

ns

t_r

t_f

pin configured as output

-

5.0

ns

[1] Applies to standard I/O pins and RESET pin.

11.3 USB interface

Table 12. Dynamic characteristics of USB pins (full-speed) (LPC2364/66/68 only)

C_L= 50 pF; R_pu= 1.5 k on D+ to V_DD(3V3), unless otherwise specified.

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

t_r/ t_f

Min

8.5

7.7

-

Typ

Max

Unit

ns

t_r

-

13.8

13.7

109

t_f

ns

t_FRFM

differential rise and fall time

matching

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

1.3

160

2

-

2.0

175

+5

V

t_FEOPT

t_FDEOP

see Figure 14

ns

source jitter for differential transition see Figure 14

to SE0 transition

t_JR1

receiver jitter to next transition

18.5

9

-

+18.5

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

+9

-

[1]

t_EOPR1

must reject as

EOP; see

Figure 14

40

t_EOPR2

EOP width at receiver

must accept as

EOP; see

82

-

ns

Figure 14

[1] Characterized but not implemented as production test. Guaranteed by design.

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Single-chip 16-bit/32-bit microcontrollers

11.4 Flash memory

Table 13. Dynamic characteristics of flash

T_amb= 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified;

_DD(3V3)= 3.0 V to 3.6 V; all voltages are measured with respect to ground.

V

Symbol

N_endu

t_ret

Parameter

endurance

Conditions

Min

10000

10

Typ

Max

Unit

[1]

100000

-

cycles

years

ms

retention time

powered; 100 cycles

-

unpowered;  100 cycles

20

-

t_er

erase time

sector or multiple

95

100

105

consecutive sectors

[2]

t_prog

programming time

0.95

1

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

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11.5 Timing

Single-chip 16-bit/32-bit microcontrollers

T

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × T

+ t

PERIOD

FDEOP

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 14. Differential data-to-EOP transition skew and EOP width

shifting edges

SCK

sampling edges

MOSI

MISO

t

su(SPI_MISO)

002aad326

Fig 15. MISO line set-up time in SSP Master mode

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12. ADC electrical characteristics

Table 14. ADC characteristics

V_DDA= 2.5 V to 3.6 V; T_amb= 40 C to +85 C, unless otherwise specified; ADC frequency 4.5 MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

V_IA

C_ia

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

pF

[1][2][3]

[1][4]

[1][5]

[1][6]

[1][7]

[8]

E_D

1

LSB

%

E_L(adj)

E_O

2

3

E_G

gain error

0.5

4

E_T

absolute error

LSB

k

R_vsi

voltage source interface

resistance

40

[1] Conditions: V_SSA= 0 V, V_DDA= 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 16.

[4] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 16.

[5] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 16.

[6] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 16.

[7] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 16.

[8] See Figure 17.

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

offset

error

gain

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

offset error

E

O

V

− V

SSA

i(VREF)

1 LSB =

1024

002aae604

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 16. ADC characteristics

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Single-chip 16-bit/32-bit microcontrollers

LPC23XX

R

vsi

20 kΩ

AD0[y]

SAMPLE

3 pF

5 pF

V

EXT

V

SS

002aac610

Fig 17. Suggested ADC interface - LPC2364/65/66/67/68 AD0[y] pin

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13. DAC electrical characteristics

Table 15. DAC electrical characteristics

V_DDA= 3.0 V to 3.6 V; T_amb= 40 C to +85 C unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

1

Max

Unit

LSB

%

E_D

differential linearity error

integral non-linearity

offset error

-

E_L(adj)

E_O

1.5

0.6

200

-

E_G

gain error

-

%

C_L

load capacitance

load resistance

-

pF

R_L

1

k

14. Application information

14.1 Suggested USB interface solutions (LPC2364/66/68 only)

V

DD(3V3)

USB_UP_LED

USB_CONNECT

LPC23XX

SoftConnect switch

R1

1.5 kΩ

V

BUS

R

= 33 Ω

S

USB-B

connector

USB_D+

S

USB_D−

V

SS

002aac578

Fig 18. LPC2364/66/68 USB interface on a self-powered device

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Single-chip 16-bit/32-bit microcontrollers

V

DD(3V3)

R2

LPC23XX

R1

1.5 kΩ

USB_UP_LED

V

BUS

USB-B

connector

R

= 33 Ω

S

USB_D+

S

USB_D−

V

SS

002aac579

Fig 19. LPC2364/66/68 USB interface on a bus-powered device

14.2 Crystal oscillator XTAL input and component selection

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/ (C_i+ C_g). In

slave mode, a minimum of 200 mV (RMS) is needed.

LPC2xxx

XTAL1

C

i

C

g

100 pF

002aae718

Fig 20. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(Figure 20), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTAL2 pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 21 and in

Table 16 and Table 17. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C_X1and C_X2need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, C_Land

R_S). Capacitance C_Pin Figure 21 represents the parallel package capacitance and should

not be larger than 7 pF. Parameters F_OSC, C_L, R_Sand C_Pare supplied by the crystal

manufacturer.

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Single-chip 16-bit/32-bit microcontrollers

LPC2xxx

L

XTAL1

XTAL2

C

L

C

P

=

XTAL

R

S

C

X2

C

X1

002aag469

Fig 21. Oscillator modes and models: oscillation mode of operation and external crystal

model used for C_X1/C_X2evaluation

Table 16. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters): low frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1/C_X2

1 MHz to 5 MHz

10 pF

< 300 

< 200 

< 100 

< 160 

< 60 

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

20 pF

30 pF

5 MHz to 10 MHz

10 pF

20 pF

30 pF

10 MHz to 15 MHz

15 MHz to 20 MHz

10 pF

20 pF

10 pF

< 80 

Table 17. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters): high frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

15 MHz to 20 MHz

10 pF

< 180 

< 100 

< 160 

< 80 

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

20 pF

20 MHz to 25 MHz

10 pF

20 pF

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14.3 RTC 32 kHz oscillator component selection

LPC2xxx

L

RTCX1

RTCX2

C

L

C

P

=

32 kHz XTAL

R

S

C

X2

C

X1

002aaf495

Fig 22. RTC oscillator modes and models: oscillation mode of operation and external

crystal model used for C_X1/C_X2evaluation

The RTC external oscillator circuit is shown in Figure 22. Since the feedback resistance is

integrated on chip, only a crystal, the capacitances C_X1and C_X2need to be connected

externally to the microcontroller.

Table 18 gives the crystal parameters that should be used. C_Lis the typical load

capacitance of the crystal and is usually specified by the crystal manufacturer. The actual

C_Linfluences oscillation frequency. When using a crystal that is manufactured for a

different load capacitance, the circuit will oscillate at a slightly different frequency

(depending on the quality of the crystal) compared to the specified one. Therefore for an

accurate time reference it is advised to use the load capacitors as specified in Table 18

that belong to a specific C_L. The value of external capacitances C_X1and C_X2specified in

this table are calculated from the internal parasitic capacitances and the C_L. Parasitics

from PCB and package are not taken into account.

Table 18. Recommended values for the RTC external 32 kHz oscillator C_X1/C_X2components

Crystal load capacitance Maximum crystal series

External load capacitors C_X1/C_X2

C_L

resistance R_S

11 pF

13 pF

15 pF

< 100 k

18 pF, 18 pF

22 pF, 22 pF

27 pF, 27 pF

< 100 k

14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1, C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_x1and C_x2should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

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14.5 Standard I/O pin configuration

Figure 23 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Analog input (for ADC input channels)

The default configuration for standard I/O pins is input with pull-up enabled. The weak

MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.

V

DD

output enable

ESD

pin configured

as digital output

driver

output

ESD

V

DD

SS

weak

pull-up

pull-up enable

weak

pull-down

pin configured

as digital input

pull-down enable

data input

select analog input

pin configured

as analog input

analog input

002aaf496

Fig 23. Standard I/O pin configuration with analog input

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14.6 Reset pin configuration

V

DD

V

DD

V

DD

R

pu

ESD

20 ns RC

GLITCH FILTER

reset

ESD

V

SS

002aaf274

Fig 24. Reset pin configuration

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15. Package outline

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

y

X

A

51

75

50

26

(1)

76

Z

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

detail X

100

1

25

Z

D

v

M

A

B

e

w M

b

p

D

B

H

v

M

5

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

p

v

w

y

Z

θ

1

2

3

p

E

D

E

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 14.1 14.1

0.17 0.09 13.9 13.9

16.25 16.25

15.75 15.75

0.75

0.45

1.15 1.15

0.85 0.85

mm

1.6

0.25

0.5

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-02-01

03-02-20

SOT407-1

136E20

MS-026

Fig 25. Package outline SOT407-1 (LQFP100)

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Single-chip 16-bit/32-bit microcontrollers

TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm

SOT926-1

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

C

M

∅ v

∅ w

C

A

B

b

e

1/2 e

y

1

y

M

C

K

J

H

G

F

e

2

E

D

C

B

A

1/2 e

ball A1

index area

1

2

3

4

5

6

7

8

9

10

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.4

0.3

0.8

0.65

0.5

0.4

9.1

8.9

9.1

8.9

mm

1.2

0.8

7.2

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

05-12-09

05-12-22

SOT926-1

- - -

Fig 26. Package outline SOT926-1 (TFBGA100)

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Single-chip 16-bit/32-bit microcontrollers

16. Abbreviations

Table 19. Abbreviations

Acronym

ADC

AHB

AMBA

APB

BOD

CAN

DAC

DCC

DMA

DSP

EOP

ETM

GPIO

IrDA

JTAG

MII

Description

Analog-to-Digital Converter

Advanced High-performance Bus

Advanced Microcontroller Bus Architecture

Advanced Peripheral Bus

BrownOut Detection

Controller Area Network

Digital-to-Analog Converter

Debug Communication Channel

Direct Memory Access

Digital Signal Processing

End Of Packet

Embedded Trace Macrocell

General Purpose Input/Output

Infrared Data Association

Joint Test Action Group

Media Independent Interface

Media Independent Interface Management

Physical Layer

MIIM

PHY

PLL

Phase-Locked Loop

PWM

RMII

SE0

Pulse Width Modulator

Reduced Media Independent Interface

Single Ended Zero

SPI

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

SSI

SSP

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus

UART

USB

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17. Revision history

Table 20. Revision history

Document ID

Release date

Data sheet status

Change

notice

Supersedes

LPC2364_65_66_67_68 v.7.1

Modifications:

20131016

Product data sheet

-

LPC2364_65_66_67_68 v.7

• Table 4 “Pin description”, Table note 6: Changed glitch filter spec from 5 ns to 10 ns.

• Table 9 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40.

LPC2364_65_66_67_68 v.7

Modifications:

20111020

Product data sheet

-

LPC2364_65_66_67_68 v.6

• Table 13 “Dynamic characteristics of flash”: Added characteristics for t_erand t_prog

• Table 4 “Pin description”: Updated description for USB_UP_LED.

.

• Table 4 “Pin description”: Added Table note 12 “If the RTC is not used, these pins can

be left floating.” for RTCX1 and RTCX2 pins.

• Table 4 “Pin description”: Added Table note 8 “This pin has a built-in pull-up resistor.”

for DBGEN, TMS, TDI, TRST, and RTCK pins.

• Table 4 “Pin description”: Added Table note 7 “This pin has no built-in pull-up and no

built-in pull-down resistor.” for TCK and TDO pins.

• Table 5 “Limiting values”: Added “non-operating” to conditions column of T_stg

.

• Table 5 “Limiting values”: Updated Table note 5 “The maximum non-operating

storage temperature is different than the temperature for required shelf life which

should be determined based on required shelf lifetime. Please refer to the JEDEC

spec (J-STD-033B.1) for further details.”.

• Table 5 “Limiting values”: Updated storage temperature min/max to 65/+150.

• Added Table 7 “Thermal resistance value (C/W): ±15 %”.

• Added Table 10 “Dynamic characteristic: internal oscillators”.

• Added Table 11 “Dynamic characteristic: I/O pins[1]”.

• Table 8 “Static characteristics”: Changed V_hystyp value from 0.5V_DD(3V3)to

0.05V_DD(3V3)

.

• Table 13 “Dynamic characteristics of flash”: Updated table.

• Added Section 9 “Thermal characteristics”.

• Added Section 10.3 “Electrical pin characteristics”.

• Added Section 14.2 “Crystal oscillator XTAL input and component selection”.

• Added Section 14.3 “RTC 32 kHz oscillator component selection”.

• Added Section 14.4 “XTAL and RTCX Printed Circuit Board (PCB) layout guidelines”.

• Added Section 14.5 “Standard I/O pin configuration”.

• Added Section 14.6 “Reset pin configuration”.

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Table 20. Revision history …continued

Document ID

Release date

Data sheet status

Change

notice

Supersedes

LPC2364_65_66_67_68 v.6

Modifications:

20100201

Product data sheet

-

LPC2364_65_66_67_68 v.5

• Table 5 “Limiting values”: Changed V_ESDmin/max to 2500/+2500.

• Table 6: Updated min, typical and max values for oscillator pins.

• Table 6: Updated conditions and typical values for I_{DD(DCDC)pd(3V3)}, I_BATact

;

I_{DD(DCDC)dpd(3V3)}and I_BATadded.

• Table 9 “Dynamic characteristics of flash”: Changed flash endurance spec from

100000 to 10000 minimum cycles.

• Added Table 11 “DAC electrical characteristics”.

• Section 7.2 “On-chip flash programming memory”: Removed text regarding flash

endurance minimum specs.

• Added Section 7.24.4.4 “Deep power-down mode”.

• Section 7.25.2 “Brownout detection”: Changed V_DD(3V3)to V_{DD(DCDC)(3V3)}

• Added Section 9.2 “Deep power-down mode”.

.

• Added Section 13.2 “XTAL1 input”.

• Added Section 13.3 “XTAL and RTC Printed-Circuit Board (PCB) layout guidelines”.

• Added table note for XTAL1 and XTAL2 pins in Table 3.

LPC2364_65_66_67_68 v.5

Modifications:

20090409

Product data sheet

-

LPC2364_65_66_67_68 v.4

• Added part LPC2364HBD100.

• Section 7.2: Added sentence clarifying SRAM speeds for LPC2364HBD.

• Table 5: Updated V_esdmin/max.

• Table 6: Updated Z_DRVTable note [14].

• Table 6: V_hys, moved 0.4 from typ to min column.

• Table 6: I_pu, added specs for >85 C.

• Table 6: Removed R_pu.

• Table 7: CCLK and IRC, added specs for >85 C.

• Added Table 9.

• Updated Figure 14.

• Updated Figure 11.

LPC2364_65_66_67_68 v.4

LPC2364_66_68 v.3

LPC2364_66_68 v.2

LPC2364_66_68 v.1

20080417

20071220

20071001

20070103

Product data sheet

Preliminary data sheet

-

LPC2364_66_68 v.3

LPC2364_66_68 v.2

LPC2364_66_68 v.1

-

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18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

18.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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NXP Semiconductors

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

18.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

20. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.20.1

7.21

7.21.1

7.22

7.22.1

7.23

7.23.1

7.24

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Pulse width modulator . . . . . . . . . . . . . . . . . . 29

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 30

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

RTC and battery RAM . . . . . . . . . . . . . . . . . . 31

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Clocking and power control . . . . . . . . . . . . . . 31

Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 31

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10

7.24.1

7.24.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 32

7.24.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 32

7.24.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 32

7.24.2

7.24.3

7.24.4

7.24.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.24.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.24.4.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 34

7.24.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 34

7.24.4.5 Power domains . . . . . . . . . . . . . . . . . . . . . . . 34

7

7.1

7.2

7.3

7.4

7.5

7.5.1

7.6

7.7

7.7.1

7.8

7.8.1

7.9

7.9.1

7.10

7.10.1

7.10.2

7.11

Functional description . . . . . . . . . . . . . . . . . . 18

Architectural overview . . . . . . . . . . . . . . . . . . 18

On-chip flash programming memory . . . . . . . 19

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 19

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 21

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 21

General purpose DMA controller . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Fast general purpose parallel I/O . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

USB interface (LPC2364/66/68 only) . . . . . . . 24

USB device controller . . . . . . . . . . . . . . . . . . . 24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

CAN controller and acceptance filters

(LPC2364/66/68 only). . . . . . . . . . . . . . . . . . . 25

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 26

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SSP serial I/O controller . . . . . . . . . . . . . . . . . 27

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SD/MMC card interface (LPC2367/68 only) . . 27

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

I²C-bus serial I/O controllers. . . . . . . . . . . . . . 27

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I²S-bus serial I/O controllers. . . . . . . . . . . . . . 28

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

General purpose 32-bit timers/external

PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 32

Power control. . . . . . . . . . . . . . . . . . . . . . . . . 33

7.25

System control . . . . . . . . . . . . . . . . . . . . . . . . 35

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Brownout detection . . . . . . . . . . . . . . . . . . . . 35

Code security

(Code Read Protection - CRP) . . . . . . . . . . . 36

AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

External interrupt inputs. . . . . . . . . . . . . . . . . 36

Memory mapping control . . . . . . . . . . . . . . . . 37

Emulation and debugging . . . . . . . . . . . . . . . 37

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 37

Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 37

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.25.1

7.25.2

7.25.3

7.25.4

7.25.5

7.25.6

7.26

7.26.1

7.26.2

7.26.3

7.11.1

7.12

7.12.1

7.13

7.13.1

7.14

7.14.1

7.15

7.15.1

7.16

7.16.1

7.17

7.17.1

7.18

7.18.1

7.19

8

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 39

Thermal characteristics . . . . . . . . . . . . . . . . . 40

10

Static characteristics . . . . . . . . . . . . . . . . . . . 41

Power-down mode. . . . . . . . . . . . . . . . . . . . . 44

Deep power-down mode . . . . . . . . . . . . . . . . 45

Electrical pin characteristics. . . . . . . . . . . . . . 47

10.1

10.2

10.3

11

Dynamic characteristics. . . . . . . . . . . . . . . . . 48

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 49

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 49

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 50

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.1

11.2

11.3

11.4

11.5

12

13

14

ADC electrical characteristics . . . . . . . . . . . . 52

DAC electrical characteristics . . . . . . . . . . . . 55

Application information . . . . . . . . . . . . . . . . . 55

7.19.1

7.20

event counters . . . . . . . . . . . . . . . . . . . . . . . . 29

continued >>

LPC2364_65_66_67_68

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.1 — 16 October 2013

68 of 69

LPC2364/65/66/67/68

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

14.1

14.2


型号：	935285102000
厂家：	NXP
描述：	32-BIT, FLASH, 72MHz, RISC MICROCONTROLLER, PBGA100, 9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100 时钟外围集成电路
文件：	总69页 (文件大小：399K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935285102000 [NXP]

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