935299509118 [NXP]

DATACOM, INTERFACE CIRCUIT, PDSO8;
935299509118
型号: 935299509118
厂家: NXP    NXP
描述:

DATACOM, INTERFACE CIRCUIT, PDSO8

电信 光电二极管 电信集成电路
文件: 总21页 (文件大小:419K)
中文:  中文翻译
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TJA1049  
High-speed CAN transceiver with Standby mode  
Rev. 3 — 16 September 2013  
Product data sheet  
1. General description  
The TJA1049 high-speed CAN transceiver provides an interface between a Controller  
Area Network (CAN) protocol controller and the physical two-wire CAN bus. The  
transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the automotive  
industry, supplying the differential transmit and receive capability to (a microcontroller  
with) a CAN protocol controller.  
The TJA1049 belongs to the third generation of high-speed CAN transceivers from NXP  
Semiconductors, offering significant improvements over first- and second-generation  
devices such as the TJA1040. It offers improved ElectroMagnetic Compatibility (EMC)  
and ElectroStatic Discharge (ESD) performance, and also features:  
Ideal passive behavior to the CAN bus when the supply voltage is off  
A very low-current Standby mode with bus wake-up capability  
TJA1049T/3 and TJA1049TK/3 can be interfaced directly to microcontrollers with  
supply voltages from 3 V to 5 V  
These features make the TJA1049 an excellent choice for all types of HS-CAN networks,  
in nodes that require a low-power mode with wake-up capability via the CAN bus.  
2. Features and benefits  
2.1 General  
Fully ISO 11898-2 and ISO 11898-5 compliant  
Suitable for 12 V and 24 V systems  
Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)  
VIO input on TJA1049T/3 and TJA1049TK/3 allows for direct interfacing with 3 V to 5 V  
microcontrollers  
SPLIT voltage output on TJA1049T and TJA1049TK for stabilizing recessive bus level  
Both variants available in SO8 and HVSON8 packages  
Leadless HVSON8 package (3.0 mm 3.0 mm) with improved Automated Optical  
Inspection (AOI) capability  
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)  
compliant)  
2.2 Low-power management  
Very low-current Standby mode with host and bus wake-up capability  
Functional behavior predictable under all supply conditions  
Transceiver disengages from the bus when not powered up (zero load)  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
2.3 Protection  
High ESD handling capability on the bus pins  
Bus pins protected against transients in automotive environments  
Transmit Data (TXD) dominant time-out function  
Bus-dominant time-out function in Standby mode  
Undervoltage detection on pins VCC and VIO  
Thermally protected  
3. Quick reference data  
Table 1.  
Symbol  
VCC  
Quick reference data  
Parameter  
Conditions  
Min  
4.75  
-
Typ Max Unit  
supply voltage  
supply current  
-
5.25  
15  
V
ICC  
Standby mode: TJA1049T, TJA1049TK  
Standby mode: TJA1049T/3, TJA1049TK/3  
Normal mode; bus recessive  
10  
-
A  
A  
mA  
mA  
V
-
5
2.5  
20  
3.5  
5
7.5  
65  
Normal mode; bus dominant  
45  
-
Vuvd(VCC)  
undervoltage detection voltage  
on pin VCC  
4.75  
VIO  
IIO  
supply voltage on pin VIO  
supply current on pin VIO  
2.8  
5
-
5.5  
14  
V
Standby mode  
-
A  
A  
Normal mode; bus recessive  
Normal mode; bus dominant  
15  
-
80  
200  
350 1000 A  
Vuvd(VIO)  
undervoltage detection voltage  
on pin VIO  
1.3  
2.0 2.7  
V
VESD  
VCANH  
VCANL  
VSPLIT  
Tvj  
electrostatic discharge voltage  
voltage on pin CANH  
IEC 61000-4-2 at pins CANH and CANL  
no time limit; DC limiting value  
no time limit; DC limiting value  
no time limit; DC limiting value  
8  
-
-
-
-
-
+8  
kV  
V
58  
58  
58  
40  
+58  
+58  
+58  
voltage on pin CANL  
V
voltage on pin SPLIT  
V
virtual junction temperature  
+150 C  
4. Ordering information  
Table 2.  
Ordering information  
Type number[1]  
Package  
Name  
Description  
plastic small outline package; 8 leads; body width 3.9 mm  
Version  
TJA1049T  
SO8  
SOT96-1  
SOT782-1  
TJA1049TK  
HVSON8  
plastic thermal enhanced very thin small outline package; no leads;  
8 terminals; body 3 3 0.85 mm  
TJA1049T/3  
SO8  
plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
TJA1049TK/3  
HVSON8  
plastic thermal enhanced very thin small outline package; no leads;  
SOT782-1  
8 terminals; body 3 3 0.85 mm  
[1] TJA1049T and TJA1049TK with SPLIT pin; TJA1049T/3 and TJA1049TK/3 with VIO pin.  
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
2 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
5. Block diagram  
V
V
IO  
5
CC  
3
V
CC  
TJA1049  
TEMPERATURE  
PROTECTION  
(1)  
V
IO  
7
6
CANH  
CANL  
SLOPE  
CONTROL  
AND  
1
TXD  
TIME-OUT  
DRIVER  
(1)  
V
IO  
8
MODE  
CONTROL  
5
STB  
SPLIT  
SPLIT  
MUX  
AND  
DRIVER  
4
RXD  
WAKE-UP  
FILTER  
2
015aaa164  
GND  
(1) In a transceiver with a SPLIT pin, the VIO input is internally connected to VCC  
.
Fig 1. Block diagram  
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
3 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
6. Pinning information  
6.1 Pinning  
TJA1049  
terminal 1  
index area  
TJA1049TK  
1
2
3
4
8
7
6
5
TXD  
STB  
STB  
TXD  
1
2
3
4
8
7
6
5
CANH  
GND  
GND  
CANH  
CANL  
SPLIT  
V
CANL  
SPLIT  
CC  
V
CC  
RXD  
RXD  
015aaa420  
Transparent top view  
015aaa166  
a. TJA1049T: SO8 package  
b. TJA1049TK: HVSON8 package  
TJA1049T/3  
terminal 1  
index area  
TJA1049TK/3  
1
2
3
4
8
7
6
5
TXD  
STB  
STB  
TXD  
1
8
7
6
5
CANH  
GND  
2
3
4
GND  
CANH  
CANL  
V
CC  
CANL  
V
CC  
RXD  
V
IO  
RXD  
V
IO  
015aaa436  
Transparent top view  
015aaa435  
c. TJA1049T/3: SO8 package  
d. TJA1049TK/3: HVSON8 package  
Fig 2. Pin configuration diagrams  
6.2 Pin description  
Table 3.  
Pin description  
Pin Description  
Symbol  
TXD  
1
transmit data input  
GND  
VCC  
2[1] ground supply  
3
4
5
5
6
7
8
supply voltage  
RXD  
receive data output; reads out data from the bus lines  
common-mode stabilization output; TJA1049T and TJA1049TK only  
supply voltage for I/O level adapter; TJA1049T/3 and TJA1049TK/3 only  
LOW-level CAN bus line  
SPLIT  
VIO  
CANL  
CANH  
STB  
HIGH-level CAN bus line  
Standby mode control input  
[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON8 package should  
be soldered to board ground (and not to any other voltage level).  
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
4 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
7. Functional description  
The TJA1049 is a HS-CAN stand-alone transceiver with Standby mode. It combines the  
functionality of the PCA82C250, PCA82C251 and TJA1040 transceivers with improved  
EMC and ESD handling capability and quiescent current performance. Improved slope  
control and high DC handling capability on the bus pins provide additional application  
flexibility.  
The TJA1049 is available in two versions, distinguished only by the function of pin 5:  
The TJA1049T and TJA1049TK are 100 % backwards compatible with the TJA1040  
when operating with a 5 V microcontroller, and also cover existing PCA82C250 and  
PCA82C251 applications  
The TJA1049T/3 and TJA1049TK/3 allow for direct interfacing to microcontrollers with  
supply voltages down to 3 V  
7.1 Operating modes  
The TJA1049 supports two operating modes, Normal and Standby, which are selectable  
via pin STB. See Table 4 for a description of the operating modes under normal supply  
conditions.  
Table 4.  
Mode  
Operating modes  
Pin STB  
Pin RXD  
LOW  
HIGH  
Normal  
LOW  
HIGH  
bus dominant  
bus recessive  
Standby  
wake-up request  
detected  
no wake-up request  
detected  
7.1.1 Normal mode  
A LOW level on pin STB selects Normal mode. In this mode, the transceiver can transmit  
and receive data via the bus lines CANH and CANL (see Figure 1 for the block diagram).  
The differential receiver converts the analog data on the bus lines into digital data which is  
output on pin RXD. The slope of the output signals on the bus lines is controlled and  
optimized in a way that guarantees the lowest possible EME.  
7.1.2 Standby mode  
A HIGH level on pin STB selects Standby mode. In Standby mode, the transceiver is not  
able to transmit or correctly receive data via the bus lines. The transmitter and  
Normal-mode receiver blocks are switched off to reduce supply current, and only a  
low-power differential receiver monitors the bus lines for activity. The wake-up filter on the  
output of the low-power receiver does not latch bus dominant states, but ensures that only  
bus dominant and bus recessive states that persist longer than tfltr(wake)bus are reflected on  
pin RXD.  
In Standby mode, the bus lines are biased to ground to minimize the system supply  
current. The low-power receiver is supplied by VIO, and is capable of detecting CAN bus  
activity even if VIO is the only supply voltage available. When pin RXD goes LOW to signal  
a wake-up request, a transition to Normal mode will not be triggered until STB is forced  
LOW.  
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
5 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
7.2 Fail-safe features  
7.2.1 TXD dominant time-out function  
A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on  
pin TXD persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus  
lines to recessive state. This function prevents a hardware and/or software application  
failure from driving the bus lines to a permanent dominant state (blocking all network  
communications). The TXD dominant time-out timer is reset when pin TXD is set HIGH.  
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.  
7.2.2 Bus dominant time-out function  
In Standby mode, a 'bus dominant time-out' timer is started when the CAN bus changes  
from recessive to dominant state. If the dominant state on the bus persists for longer than  
tto(dom)bus, the RXD pin is forced HIGH. This prevents a clamped dominant bus (due to a  
bus short-circuit or a failure in one of the other nodes on the network) generating a  
permanent wake-up request. The bus dominant time-out timer is reset when the CAN bus  
changes from dominant to recessive state.  
7.2.3 Internal biasing of TXD and STB input pins  
Pins TXD and STB have internal pull-ups to VIO to ensure a safe, defined state in case  
one (or both) of these pins is left floating. Pull-up currents flow in these pins in all states;  
both pins should be held HIGH in Standby mode to minimize standby current.  
7.2.4 Undervoltage detection on pins VCC and VIO  
Should VCC drop below the VCC undervoltage detection level, Vuvd(VCC), the transceiver  
will switch to Standby mode. The logic state of pin STB will be ignored until VCC has  
recovered.  
Should VIO drop below the VIO undervoltage detection level, Vuvd(VIO), the transceiver will  
switch off and disengage from the bus (zero load) until VIO has recovered.  
7.2.5 Overtemperature protection  
The output drivers are protected against overtemperature conditions. If the virtual junction  
temperature exceeds the shutdown junction temperature, Tj(sd), the output drivers will be  
disabled until the virtual junction temperature falls below Tj(sd) and TXD becomes  
recessive again. Including the TXD condition ensures that output driver oscillation due to  
temperature drift is avoided.  
7.3 SPLIT output pin and VIO supply pin  
Two versions of the TJA1049 are available, only differing in the function of a single pin.  
Pin 5 is either a SPLIT output pin or a VIO supply pin.  
7.3.1 SPLIT pin  
Using the SPLIT pin on the TJA1049T or TJA1049TK in conjunction with a split  
termination network (see Figure 3 and Figure 6) can help to stabilize the recessive voltage  
level on the bus. This will reduce EME in networks with DC leakage to ground (e.g. from  
deactivated nodes with poor bus leakage performance). In Normal mode, pin SPLIT  
delivers a DC output voltage of 0.5VCC. In Standby mode or when VCC is off, pin SPLIT is  
floating.  
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
6 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
V
CC  
TJA1049  
CANH  
SPLIT  
CANL  
R
60 Ω  
60 Ω  
V
= 0.5 V  
CC  
SPLIT  
in normal mode;  
otherwise floating  
R
015aaa167  
GND  
Fig 3. Stabilization circuitry and application for version with SPLIT pin  
7.3.2 VIO supply pin  
Pin VIO on the TJA1049T/3 and TJA1049TK/3 should be connected to the microcontroller  
supply voltage (see Figure 7). This will adjust the signal levels of pins TXD, RXD and STB  
to the I/O levels of the microcontroller. Pin VIO also provides the internal supply voltage for  
the low-power differential receiver of the transceiver. For applications running in  
low-power mode, this allows the bus lines to be monitored for activity even if there is no  
supply voltage on pin VCC  
.
For versions of the TJA1049 without a VIO pin, the VIO input is internally connected to VCC  
This sets the signal levels of pins TXD, RXD and STB to levels compatible with 5 V  
microcontrollers.  
.
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
7 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
8. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.  
Symbol Parameter  
Conditions  
Min  
Max  
Unit  
Vx  
voltage on pin x  
no time limit; DC value  
on pins CANH, CANL and SPLIT  
on any other pin  
on pins CANH and CANL  
IEC 61000-4-2  
at pins CANH and CANL  
HBM  
58  
+58  
+7  
V
V
V
0.3  
[1]  
[2]  
[3]  
[4]  
Vtrt  
transient voltage  
150 +100  
VESD  
electrostatic discharge voltage  
8  
+8  
kV  
at pins CANH and CANL  
at any other pin  
MM  
8  
4  
+8  
+4  
kV  
kV  
[5]  
[6]  
at any pin  
300 +300  
V
CDM  
at corner pins  
750 +750  
500 +500  
V
at any pin  
V
[7]  
Tvj  
virtual junction temperature  
storage temperature  
40  
55  
+150  
+150  
C  
C  
Tstg  
[1] Verified by an external test house to ensure pins CANH and CANL can withstand ISO 7637 part 3 automotive transient test pulses 1, 2a,  
3a and 3b.  
[2] IEC 61000-4-2 (150 pF, 330 ); direct coupling.  
[3] ESD performance of pins CANH and CANL according to IEC 61000-4-2 (150 pF, 330 ) has been be verified by an external test house.  
The result is equal to or better than 8 kV (unaided).  
[4] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).  
[5] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).  
[6] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF); grade C3B.  
[7] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(vj-a), where Rth(vj-a) is a  
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient  
temperature (Tamb).  
9. Thermal characteristics  
Table 6.  
Thermal characteristics  
According to IEC 60747-1.  
Symbol  
Parameter  
Conditions  
Typ  
145  
50  
Unit  
K/W  
K/W  
Rth(j-a)  
thermal resistance from junction to ambient  
SO8 package; in free air  
HVSON8 package; in free air  
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
8 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
10. Static characteristics  
Table 7.  
Static characteristics  
Tvj = 40 C to +150 C; VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.5 V[1]; RL = 60 unless specified otherwise; All voltages are  
defined with respect to ground. Positive currents flow into the IC.[2]  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Supply; pin VCC  
VCC  
ICC  
supply voltage  
4.75  
-
5.25  
V
supply current  
Standby mode  
TJA1049T or TJA1049TK;  
includes IIO; VTXD = VIO  
-
-
10  
-
15  
5
A  
A  
TJA1049T/3 or TJA1049TK/3  
Normal mode  
recessive; VTXD = VIO  
dominant; VTXD = 0 V  
2.5  
20  
5
7.5  
65  
mA  
mA  
V
45  
-
Vuvd(VCC)  
undervoltage detection  
voltage on pin VCC  
[1]  
3.5  
4.75  
I/O level adapter supply; pin VIO  
VIO  
IIO  
supply voltage on pin VIO  
2.8  
5
-
-
5.5  
14  
V
supply current on pin VIO  
Standby mode; VTXD = VIO  
Normal mode  
A  
recessive; VTXD = VIO  
dominant; VTXD = 0 V  
15  
-
80  
200  
1000  
2.7  
A  
A  
V
350  
2.0  
Vuvd(VIO)  
undervoltage detection  
voltage on pin VIO  
1.3  
Standby mode control input; pin STB  
[3]  
VIH  
HIGH-level input voltage  
0.7VIO  
-
VIO  
0.3  
+
V
VIL  
IIH  
IIL  
LOW-level input voltage  
HIGH-level input current  
LOW-level input current  
0.3  
1  
-
-
-
0.3VIO  
+1  
V
VSTB = VIO  
VSTB = 0 V  
A  
A  
15  
1  
CAN transmit data input; pin TXD  
[3]  
VIH  
HIGH-level input voltage  
0.7VIO  
-
VIO  
0.3  
+
V
VIL  
IIH  
IIL  
LOW-level input voltage  
HIGH-level input current  
LOW-level input current  
input capacitance  
0.3  
5  
-
0.3VIO  
+5  
V
VTXD = VIO  
VTXD = 0 V  
-
A  
A  
pF  
260  
-
150  
30  
10  
[4]  
Ci  
5
CAN receive data output; pin RXD  
IOH  
HIGH-level output current  
TJA1049T or TJA1049TK;  
VRXD = VCC 0.4 V  
8  
9  
1
3  
3  
-
1  
1  
12  
mA  
mA  
mA  
TJA1049T/3 or TJA1049TK/3;  
VRXD = VIO 0.4 V  
IOL  
LOW-level output current  
VRXD = 0.4 V; bus dominant  
TJA1049  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 16 September 2013  
9 of 21  
TJA1049  
NXP Semiconductors  
High-speed CAN transceiver with Standby mode  
Table 7.  
Static characteristics …continued  
Tvj = 40 C to +150 C; VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.5 V[1]; RL = 60 unless specified otherwise; All voltages are  
defined with respect to ground. Positive currents flow into the IC.[2]  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Bus lines; pins CANH and CANL  
VO(dom)  
dominant output voltage  
VTXD = 0 V; t < tto(dom)TXD  
pin CANH  
2.75  
0.5  
3.5  
1.5  
-
4.5  
V
pin CANL  
2.25  
+400  
V
Vdom(TX)sym  
VO(dif)bus  
transmitter dominant voltage Vdom(TX)sym = VCC VCANH VCANL  
400  
mV  
symmetry  
bus differential output  
voltage  
VTXD = 0 V; t < tto(dom)TXD  
VCC = 4.75 V to 5.25 V  
RL = 45 to 65   
1.5  
-
3
V
V
TXD = VIO recessive; no load  
50  
2
-
+50  
3
mV  
V
VO(rec)  
recessive output voltage  
Normal mode; VTXD = VIO; no load  
Standby mode; no load  
Vcm(CAN) = 12 V to +12 V  
Normal mode  
0.5VCC  
-
0.1  
+0.1  
V
[5]  
[6]  
Vth(RX)dif  
differential receiver  
threshold voltage  
0.5  
0.4  
100  
-
-
-
0.9  
V
Standby mode  
1.15  
300  
V
Vhys(RX)dif  
IO(sc)dom  
differential receiver  
hysteresis voltage  
Vcm(CAN) = 12 V to +12 V  
mV  
Normal mode  
dominant short-circuit output VTXD = 0 V; t < tto(dom)TXD; VCC = 5 V  
current  
pin CANH; VCANH = 0 V  
100  
40  
70  
70  
-
40  
100  
+5  
mA  
mA  
mA  
pin CANL; VCANL = 5 V / 40 V  
IO(sc)rec  
IL  
recessive short-circuit  
output current  
Normal mode; VTXD = VIO  
VCANH = VCANL = 27 V to +32 V  
5  
leakage current  
VCC = VIO = 0 V;  
3  
-
+3  
A  
VCANH = VCANL = 5 V  
Ri  
input resistance  
9
15  
-
28  
+3  
52  
20  
k  
%
Ri  
input resistance deviation  
differential input resistance  
between VCANH and VCANL  
3  
19  
-
Ri(dif)  
Ci(cm)  
30  
-
k  
pF  
[4]  
[4]  
common-mode input  
capacitance  
Ci(dif)  
differential input capacitance  
-
-
10  
pF  
V
Common mode stabilization output, pin SPLIT; only relevant for TJA1049T and TJA1049TK  
VO  
output voltage  
Normal mode  
0.3VCC 0.5VCC 0.7VCC  
ISPLIT = 500 A to +500 A  
Normal mode; RL = 1 M  
0.45VCC 0.5VCC 0.55VCC  
V
IL  
leakage current  
Standby mode  
5  
-
+5  
-
A  
VSPLIT = 58 V to +58 V  
Temperature detection  
Tj(sd) shutdown junction  
temperature  
[4]  
-
190  
C  
[1] Only TJA1049T/3 and TJA1049TK/3 have a VIO pin; in TJA1049T and TJA1049TK, the VIO input is internally connected to VCC  
.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to  
cover the specified temperature and power supply voltage range.  
TJA1049  
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Product data sheet  
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High-speed CAN transceiver with Standby mode  
[3] Maximum value assumes VCC < VIO; if VCC > VIO, the maximum value will be VCC + 0.3 V.  
[4] Not tested in production; guaranteed by design.  
[5]  
Vcm(CAN) is the common mode voltage of CANH and CANL.  
[6] For TJA1049T/3 and TJA1049TK/3: values valid when VIO = 4.5 V to 5.5 V; when VIO = 2.8 V to 4.5 V, values valid when  
Vcm(CAN) = 12 V to +12 V.  
11. Dynamic characteristics  
Table 8.  
Dynamic characteristics  
Tvj = 40 C to +150 C; VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.5 V[1]; RL = 60 unless specified otherwise. All voltages are  
defined with respect to ground. Positive currents flow into the IC.[2]  
Symbol  
Parameter  
Conditions  
Min Typ  
Max  
Unit  
Transceiver timing; pins CANH, CANL, TXD and RXD; see Figure 4 and Figure 5  
td(TXD-busdom) delay time from TXD to bus dominant  
td(TXD-busrec) delay time from TXD to bus recessive  
td(busdom-RXD) delay time from bus dominant to RXD  
td(busrec-RXD) delay time from bus recessive to RXD  
Normal mode  
Normal mode  
Normal mode  
Normal mode  
-
65  
90  
60  
65  
-
-
ns  
ns  
ns  
ns  
ns  
-
-
-
-
-
-
tPD(TXD-RXD)  
propagation delay from TXD to RXD  
versions with SPLIT pin  
Normal mode  
60  
220  
versions with VIO pin  
Normal mode  
60  
-
250  
ns  
tto(dom)TXD  
tto(dom)bus  
tfltr(wake)bus  
TXD dominant time-out time  
bus dominant time-out time  
bus wake-up filter time  
VTXD = 0 V; Normal mode  
Standby mode  
0.3  
0.3  
0.5  
2
2
1
5
5
3
ms  
ms  
s  
version with SPLIT pin  
Standby mode  
versions with VIO pin  
Standby mode  
0.5  
7
1.5  
25  
5
s  
s  
td(stb-norm)  
standby to normal mode delay time  
47  
[1] Only TJA1049T/3 and TJA1049TK/3 have a VIO pin; in the TJA1049T and TJA1049TK, the VIO input is internally connected to VCC  
.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to  
cover the specified temperature and power supply voltage range.  
TJA1049  
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Product data sheet  
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High-speed CAN transceiver with Standby mode  
+5 V  
47 μF  
100 nF  
V
CC  
TXD  
CANH  
TJA1049  
R
L
100 pF  
SPLIT  
CANL  
RXD  
GND  
STB  
15 pF  
015aaa165  
(1) For versions with a VIO pin (TJA1049T/3 and TJA1049TK/3), the VIO pin is connected to pin VCC  
.
Fig 4. Timing test circuit for CAN transceiver  
HIGH  
LOW  
TXD  
CANH  
CANL  
dominant  
0.9 V  
0.5 V  
V
O(dif)(bus)  
recessive  
HIGH  
0.7V  
IO  
RXD  
0.3V  
IO  
LOW  
t
t
d(TXD-busrec)  
d(TXD-busdom)  
t
t
d(busrec-RXD)  
d(busdom-RXD)  
t
t
PD(TXD-RXD)  
PD(TXD-RXD)  
015aaa025  
Fig 5. CAN transceiver timing diagram  
TJA1049  
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Product data sheet  
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High-speed CAN transceiver with Standby mode  
12. Application information  
5 V  
BAT  
V
CC  
V
DD  
CANH  
STB  
Pxx  
Pyy  
CANH  
MICRO-  
CONTROLLER  
SPLIT  
CANL  
TJA1049  
TXD  
RXD  
TX0  
RX0  
CANL  
GND  
GND  
015aaa168  
Fig 6. Typical application with TJA1049T or TJA1049TK and a 5 V microcontroller.  
BAT  
3 V  
INH  
5 V  
V
V
IO  
CC  
V
STB  
CANH  
CANL  
DD  
Pxx  
CANH  
CANL  
TJA1049T/3  
MICRO-  
CONTROLLER  
TXD  
RXD  
TJA1049TK/3  
TX0  
RX0  
GND  
GND  
015aaa437  
Switching off the 5 V supply in Standby mode (dotted line) is optional.  
Fig 7. Typical application with TJA1049T/3 or TJA1049TK/3 and a 3 V microcontroller.  
13. Test information  
13.1 Quality information  
This product has been qualified in accordance with the Automotive Electronics Council  
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for  
integrated circuits, and is suitable for use in automotive applications.  
TJA1049  
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Product data sheet  
Rev. 3 — 16 September 2013  
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High-speed CAN transceiver with Standby mode  
14. Package outline  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT96-1  
076E03  
MS-012  
Fig 8. Package outline SOT96-1 (SO8)  
TJA1049  
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Product data sheet  
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High-speed CAN transceiver with Standby mode  
HVSON8: plastic thermal enhanced very thin small outline package; no leads;  
8 terminals; body 3 x 3 x 0.85 mm  
SOT782-1  
X
D
B
A
E
A
A
1
c
detail X  
terminal 1  
index area  
e
1
C
terminal 1  
index area  
v
C A  
C
B
e
b
y
1
y
w
C
1
4
L
K
E
h
8
5
D
h
0
1
2 mm  
L
scale  
Dimensions  
(1)  
Unit  
A
A
b
c
D
D
h
E
E
e
e
1
K
v
w
y
y
1
1
h
max 1.00 0.05 0.35  
mm nom 0.85 0.03 0.30 0.2 3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40 0.1 0.05 0.05 0.1  
min 0.80 0.00 0.25 2.90 2.35 2.90 1.55 0.25 0.35  
3.10 2.45 3.10 1.65  
0.35 0.45  
Note  
1. Plastic or metal protrusions of 0.075 maximum per side are not included.  
sot782-1_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
- - -  
JEDEC  
JEITA  
- - -  
09-08-25  
09-08-28  
SOT782-1  
MO-229  
Fig 9. Package outline SOT782-1 (HVSON8)  
TJA1049  
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Product data sheet  
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15. Handling information  
All input and output pins are protected against ElectroStatic Discharge (ESD) under  
normal handling. When handling ensure that the appropriate precautions are taken as  
described in JESD625-A or equivalent standards.  
16. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
16.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
16.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
Through-hole components  
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
Board specifications, including the board finish, solder masks and vias  
Package footprints, including solder thieves and orientation  
The moisture sensitivity level of the packages  
Package placement  
Inspection and repair  
Lead-free soldering versus SnPb soldering  
16.3 Wave soldering  
Key characteristics in wave soldering are:  
TJA1049  
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Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
Solder bath specifications, including temperature and impurities  
16.4 Reflow soldering  
Key characteristics in reflow soldering are:  
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus  
reducing the process window  
Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 9 and 10  
Table 9.  
SnPb eutectic process (from J-STD-020D)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
350  
220  
< 2.5  
235  
220  
2.5  
220  
Table 10. Lead-free process (from J-STD-020D)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 10.  
TJA1049  
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High-speed CAN transceiver with Standby mode  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 10. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
17. Soldering of HVSON packages  
Section 16 contains a brief introduction to the techniques most commonly used to solder  
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON  
leadless package ICs can found in the following application notes:  
AN10365 “Surface mount reflow soldering description”  
AN10366 “HVQFN application information”  
18. Revision history  
Table 11. Revision history  
Document ID  
TJA1049 v3  
Release date  
20130916  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
TJA1049 v.2  
Modifications:  
added HVSON8 package  
added TJA1049T/3 and TJA1049TK/3 (with VIO pin)  
revised text, drawings and characteristics tables throughout to accommodate above changes  
TJA1049 v.2  
TJA1049 v.1  
20110323  
Product data sheet  
-
TJA1049 v.1  
20100924  
Product data sheet  
-
-
TJA1049  
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19. Legal information  
19.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use in automotive applications — This NXP  
19.2 Definitions  
Semiconductors product has been qualified for use in automotive  
applications. Unless otherwise agreed in writing, the product is not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer's own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
19.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
TJA1049  
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Product data sheet  
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No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
19.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
20. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
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21. Contents  
1
General description. . . . . . . . . . . . . . . . . . . . . . 1  
19.4  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Contact information . . . . . . . . . . . . . . . . . . . . 20  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Low-power management . . . . . . . . . . . . . . . . . 1  
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
20  
21  
2.1  
2.2  
2.3  
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
7
7.1  
Functional description . . . . . . . . . . . . . . . . . . . 5  
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5  
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 6  
TXD dominant time-out function. . . . . . . . . . . . 6  
Bus dominant time-out function . . . . . . . . . . . . 6  
Internal biasing of TXD and STB input pins . . . 6  
Undervoltage detection on pins VCC and VIO . . 6  
Overtemperature protection . . . . . . . . . . . . . . . 6  
SPLIT output pin and VIO supply pin . . . . . . . . 6  
SPLIT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
7.1.1  
7.1.2  
7.2  
7.2.1  
7.2.2  
7.2.3  
7.2.4  
7.2.5  
7.3  
7.3.1  
7.3.2  
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Thermal characteristics . . . . . . . . . . . . . . . . . . 8  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9  
Dynamic characteristics . . . . . . . . . . . . . . . . . 11  
Application information. . . . . . . . . . . . . . . . . . 13  
Test information. . . . . . . . . . . . . . . . . . . . . . . . 13  
Quality information . . . . . . . . . . . . . . . . . . . . . 13  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14  
Handling information. . . . . . . . . . . . . . . . . . . . 16  
9
10  
11  
12  
13  
13.1  
14  
15  
16  
Soldering of SMD packages . . . . . . . . . . . . . . 16  
Introduction to soldering . . . . . . . . . . . . . . . . . 16  
Wave and reflow soldering . . . . . . . . . . . . . . . 16  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 16  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 17  
16.1  
16.2  
16.3  
16.4  
17  
18  
Soldering of HVSON packages. . . . . . . . . . . . 18  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18  
19  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
19.1  
19.2  
19.3  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2013.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 16 September 2013  
Document identifier: TJA1049  

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