935299954147 [NXP]
Interface Circuit;
| 型号： | 935299954147 |
| 厂家： | 
NXP |
| 描述： | Interface Circuit 接口集成电路 |
| 文件： | 总23页 (文件大小：1088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9617A
Level translating Fm+ I2C-bus repeater
Rev. 1 — 20 March 2013
Product data sheet
1. General description
The PCA9617A is a CMOS integrated circuit that provides level shifting between low
voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I2C-bus
or SMBus applications. While retaining all the operating modes and features of the
I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two
buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617A
enables the system designer to isolate two halves of a bus for both voltage and
capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance
when the PCA9617A is unpowered.
The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjustable
voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the
port B translating into a nearly 0 V LOW on the port A which accommodates the smaller
voltage swings of lower voltage logic.
The static offset design of the port B PCA9617A I/O drivers prevents them from being
connected to the static or incremented offset of other bus buffers. Port A of two or more
PCA9617As can be connected together, however, to allow a star topography with port A
on the common bus, and port A can be connected directly to any other buffer with static or
incremented offset outputs. Multiple PCA9617As can be connected in series, port A to
port B, with no build-up in offset voltage with only time of flight delays to consider.
The PCA9617A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and
off under system control. Caution should be observed to only change the state of the
enable pin when the bus is idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V,
while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a latching condition from occurring. The output pull-down on port A drives a
hard LOW and the input level is set at 0.35VCC(A) to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.8 V.
2. Features and benefits
2 channel, bidirectional buffer isolates capacitance and allows 540 pF on either side of
the device at 1 MHz and up to 4000 pF at lower speeds
Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V
Footprint and functional replacement for PCA9517A at Fast-mode speeds
Port A operating supply voltage range of 0.8 V to 5.5 V with normal levels
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
Port B operating supply voltage range of 2.2 V to 5.5 V with static offset level
5 V tolerant I2C-bus and enable pins
0 Hz to 1000 kHz clock frequency (the maximum system operating frequency may be
less than 1000 kHz because of the delays added by the repeater)
Active HIGH repeater enable input referenced to VCC(B)
Open-drain input/outputs
Latching free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices,
SMBus (standard and high power mode), PMBus and multiple masters
Powered-off high-impedance I2C-bus pins
ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: TSSOP8 and HWSON8
3. Ordering information
Table 1.
Ordering information
Tamb = 40 C to +85 C.
Type number Topside
mark
PCA9617ADP P617A
Package
Name
Description
Version
TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
PCA9617ATP
P7A
HWSON8
plastic thermal enhanced very very thin small outline package;
SOT1069-2
no leads; 8 terminals; body 2 3 0.8 mm
[1] Also known as MSOP8.
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
Package
Packing method
Minimum Temperature range
part number
order
quantity
PCA9617ADP
PCA9617ATP
PCA9617ADPJ
PCA9617ATPZ
TSSOP8
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
HWSON8
Reel 7” Q2/T3 *standard mark
4000
Tamb = 40 C to +85 C
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
2 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
4. Functional diagram
V
V
CC(A)
CC(B)
PCA9617A
SDAA
SDAB
SCLB
SCLA
EN
V
CC(B)
pull-up
resistor
002aag641
GND
Fig 1. Functional diagram of PCA9617A
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
3 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
5. Pinning information
5.1 Pinning
terminal 1
index area
PCA9617ATP
SDAA
GND
EN
1
2
3
4
8
7
6
5
SCLA
V
CC(A)
V
CC(B)
1
2
3
4
8
7
6
5
V
V
CC(B)
CC(A)
SCLA
SDAA
GND
SCLB
SDAB
EN
PCA9617ADP
SDAB
SCLB
002aag644
Transparent top view
002aag643
Fig 2. Pin configuration for TSSOP8
(MSOP8)
Fig 3. Pin configuration for HWSON8
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP8
HWSON8
VCC(A)
SCLA
SDAA
GND
1
2
3
4
5
6
7
8
7
port A supply voltage (0.8 V to 5.5 V)
serial clock port A bus
8
1
2[1]
serial data port A bus
supply ground (0 V)
EN
3
active HIGH repeater enable input
serial data port B bus
SDAB
SCLB
VCC(B)
4
5
serial clock port B bus
6
port B supply voltage (2.2 V to 5.5 V)
[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper head conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
4 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9617A”.
The PCA9617A enables I2C-bus or SMBus translation down to VCC(A) as low as 0.8 V
without degradation of system performance. The PCA9617A contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.8 V) and a 2.5 V, 3.3 V or 5 V I2C-bus or SMBus. All
inputs and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered
(VCC(B) and/or VCC(A) = 0 V). The PCA9617A includes a power-up circuit that keeps the
output drivers turned off until VCC(B) is above 2.2 V and until after the internal reference
circuits have settled ~400 s, and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be
applied in any sequence at power-up. After power-up and with the enable (EN) HIGH, a
LOW level on port A (below 0.3VCC(A)) turns the corresponding port B driver (either SDA
or SCL) on and drives port B down to about 0.55 V. When port A rises above 0.3VCC(A)
the port B pull-down driver is turned off and the external pull-up resistor pulls the pin
HIGH. When port B falls first and goes below 0.4 V, the port A driver is turned on and
,
port A pulls down to ~0 V. The port A pull-down is not enabled unless the port B voltage
goes below 0.4 V. If the port B low voltage goes below 0.4 V, the port B pull-down driver is
enabled and port B will only be able to rise to 0.55 V until port A rises above 0.3VCC(A)
,
then port B will continue to rise being pulled up by the external pull-up resistor. The VCC(A)
is only used to provide the 0.35VCC(A) reference to the port A input comparators and for
the power good detect circuit. The PCA9617A includes a VCC(A) overvoltage disable that
turns the channel off if 0.4VCC(A) + 0.8 V > VCC(B). The PCA9617A logic and all I/Os are
powered by the VCC(B) pin.
6.1 Enable
The EN pin is active HIGH with thresholds referenced to VCC(B) and an internal pull-up to
CC(B) that maintains the device active unless the user selects to disable the repeater to
V
isolate a badly behaved slave on power-up until after the system power-up reset. It should
never change state during an I2C-bus operation because disabling during a bus operation
will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus
parts being enabled. The enable does not switch the internal reference circuits so the
~400 s delay is only seen when VCC(B) comes up.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode, Fast-mode
and Fast-mode Plus I2C-bus devices in addition to SMBus devices. Standard mode and
Fast-mode I2C-bus devices only specify 3 mA output drive; this limits the termination
current to 3 mA in a generic I2C-bus system where Standard-mode devices, Fast-mode
devices and multiple masters are possible. When only Fast-mode Plus devices are used
with 30 mA at 5 V drive strength, then lower value pull-up resistors can be used. The
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
5 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
B-side RC should not be less than 67.5 ns because shorter RCs increase the turnaround
bounce when the B-side transitions from being externally driven to pulled down by its
offset buffer.
Please see Application Note AN255, “I2C/SMBus Repeaters, Hubs and Expanders” for
additional information on sizing resistors and precautions when using more than one
PCA9617A in a system or using the PCA9617A in conjunction with other bus buffers.
7. Application design-in information
A typical application is shown in Figure 4. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at
1000 kHz. Master devices can be placed on either bus.
3.3 V
1.2 V
1.4 kΩ
1.4 kΩ
1.4 kΩ
1.4 kΩ
V
V
CC(A)
CC(B)
SDAB
SCLB
SDAA
SCLA
SDA
SCL
BUS
MASTER
1000 kHz
SDA
SCL
PCA9617A
SLAVE
1000 kHz
EN
bus B
bus A
002aag653
Fig 4. Typical application
The PCA9617A is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.8 V to 5.5 V bus voltages and 2.2 V to 5.5 V bus voltages.
When port A of the PCA9617A is pulled LOW by a driver on the I2C-bus, a comparator
detects the falling edge when it goes below 0.3VCC(A) and causes the internal driver on
port B to turn on, causing port B to pull down to about 0.5 V. When port B of the
PCA9617A falls, first a CMOS hysteresis type input detects the falling edge and causes
the internal driver on port A to turn on and pull the port A pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the
bus master in Figure 4 were to write to the slave through the PCA9617A, waveforms
shown in Figure 8 would be observed on the A bus. This looks like a normal I2C-bus
transmission except that the HIGH level may be as low as 0.8 V, and the turn on and turn
off of the acknowledge signals are slightly delayed.
The internal comparator requires that 0.4 VCC(A) be less than or equal to VCC(B) 0.8 V
for the device to operate. Since A port is 5 V tolerant, the VCC(A) can be lowered to support
device spectrum while still supporting 5 V signals on the A port.
On the B bus side of the PCA9617A, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9617A. After the eighth clock pulse, the data line
will be pulled to the VOL of the slave device which is very close to ground in this example.
At the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9617A for a short delay while the A bus side rises above 0.3VCC(A) then it continues
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
6 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9617A (VIL) be at or below 0.4 V to be
recognized by the PCA9617A and then transmitted to the A bus side.
Multiple PCA9617A port A sides can be connected in a star configuration (Figure 5),
allowing all nodes to communicate with each other.
Multiple PCA9617As can be connected in series (Figure 6) as long as port A is connected
to port B. I2C-bus slave devices can be connected to any of the bus segments. The
number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
V
V
CC(B)
CC(A)
1.4 kΩ
1.4 kΩ
1.4 kΩ
1.4 kΩ
V
V
CC(B)
CC(A)
SDAA
SCLA
SDAB
SCLB
SDA
SCL
SDA
SCL
BUS
MASTER
PCA9617A
SLAVE
1000 kHz
EN
1.4 kΩ
1.4 kΩ
V
V
CC(B)
CC(A)
SDAA
SCLA
SDAB
SCLB
SDA
SCL
PCA9617A
SLAVE
1000 kHz
EN
1.4 kΩ
1.4 kΩ
V
V
CC(B)
CC(A)
SDAA
SCLA
SDAB
SCLB
SDA
SCL
PCA9617A
SLAVE
1000 kHz
EN
002aag645
Fig 5. Typical star application
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
7 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
V
CC
1.4 kΩ
1.4 kΩ
1.4 kΩ
1.4 kΩ
1.4 kΩ
1.4 kΩ
1.4 kΩ
1.4 kΩ
SDAA
SCLA
SDAB
SCLB
SDAA
SCLA
SDAB
SCLB
SDAA
SCLA
SDAB
SCLB
SDA
SCL
BUS
MASTER
SDA
SCL
PCA9617A
PCA9617A
PCA9617A
SLAVE
1000 kHz
EN
EN
EN
002aag646
Decoupling capacitors not shown for simplicity, but they are required. It is especially important that the decoupling for the
PCA9617A VCC(B) be close to the VCC(B) pin.
Fig 6. Typical series application
CARD 1
V
CC(A)
V
CC(B)
CARD 2
R
R
10 kΩ
10 kΩ
10 kΩ
(optional)
PU
PU
V
CC(A)
V
CC(B)
75 Ω
SDAA
SCLA
SDAB
SCLB
EN
MASTER
OR
75 Ω
SLAVE
GND
002aag647
Decoupling capacitors not shown for simplicity, but they are required. It is especially important that
the decoupling for the PCA9617A VCC(B) be close to the VCC(B) pin.
Fig 7. Typical application of PCA9617A driving a short cable
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
8 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
9th clock pulse
acknowledge
SCL
SDA
002aac775
Fig 8. Bus A (0.8 V to 5.5 V bus) waveform
9th clock pulse
acknowledge
SCL
SDA
V
of PCA9617A
OL
002aag648
V
of slave
OL
Fig 9. Bus B (2.2 V to 5.5 V) waveform
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC(B)
VCC(A)
VI/O
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage port B
supply voltage port A
voltage on an input/output pin
input/output current
input current
0.5
0.5
0.5
-
adjustable
+7
V
port A and port B; enable pin (EN)
port A; port B
+7
V
II/O
50
mA
mA
mW
C
C
C
II
EN, VCC(A), VCC(B), GND
-
50
Ptot
total power dissipation
storage temperature
ambient temperature
junction temperature
-
100
+125
+85
+125
Tstg
55
40
-
Tamb
Tj
operating in free air
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
9 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
9. Static characteristics
Table 5.
CC(A) = 0.8 V to 5.5 V[1]; VCC(B) = 2.2 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Typical values measured with VCC(A) = 0.95 V and VCC(B) = 2.5 V at 25 C, unless otherwise noted.
Static characteristics
V
Symbol
Supplies
VCC(B)
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage port B
supply voltage port A
supply current port A
2.2
-
5.5
5.5
8
V
[2]
VCC(A)
0.8
-
V
ICC(A)
VCC(A) = 0.95 V
VCC(A) = 5.5 V
-
-
-
-
A
A
mA
-
50
2.5
ICCH(B)
ICCL(B)
port B HIGH-level
supply current
VCC(B) = 5.5 V;
SDAn = SCLn = VCC(n)
1.5
port B LOW-level
supply current
VCC(B) = 5.5 V; one SDA and
one SCL = GND; other SDA and
SCL open (with pull-up resistors)
-
1.7
2.9
mA
Input and output SDAB and SCLB
VIH
VIL
VIK
ILI
HIGH-level input voltage
LOW-level input voltage
input clamping voltage
input leakage current
0.7VCC(B)
-
-
-
-
-
-
5.5
+0.4
0.3
1
V
0.5
V
II = 18 mA
1.2
V
VI = 5.5 V
-
A
A
V
IIL
LOW-level input current
LOW-level output voltage
SDA, SCL; VI = 0.2 V
IOL = 150 A at VCC(B) = 2.2 V
IOL = 13 mA at VCC(B) = 2.2 V
-
10
[3]
[4]
VOL
0.47
-
-
0.54 0.60
V
VOLVIL
difference between
LOW-level output and
LOW-level input voltage
VOL at IOL = 1 mA;
guaranteed by design
60
90
160
mV
Cio
input/output capacitance
VI = 3 V or 0 V; VCC(B) = 3.3 V;
EN = LOW
-
-
7
7
10
10
pF
pF
VI = 3 V or 0 V; VCC = 0 V
Input and output SDAA and SCLA
VIH
VIL
VIK
ILI
HIGH-level input voltage
LOW-level input voltage
input clamping voltage
input leakage current
0.7VCC(A)
-
5.5
V
[5]
[6]
0.5
-
+0.25VCC(A)
V
II = 18 mA
1.2
-
0.3
1
V
VI = 5.5 V
-
-
-
-
-
A
A
V
IIL
LOW-level input current
LOW-level output voltage
input/output capacitance
SDA, SCL; VI = 0.2 V
IOL = 13 mA; VCC(B) = 2.2 V
-
10
VOL
Cio
0.1
7
0.2
10
VI = 3 V or 0 V; VCC = 3.3 V;
EN = LOW
pF
VI = 3 V or 0 V; VCC = 0 V
-
7
10
pF
Enable
VIL
LOW-level input voltage
HIGH-level input voltage
0.5
-
+0.3VCC(B)
V
VIH
0.7VCC(B)
18
-
5.5
V
IIL(EN)
LOW-level input current on
pin EN
VI = 0.2 V, EN; VCC(B) = 2.2 V
7
4
A
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
10 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
Table 5.
Static characteristics …continued
VCC(A) = 0.8 V to 5.5 V[1]; VCC(B) = 2.2 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Typical values measured with VCC(A) = 0.95 V and VCC(B) = 2.5 V at 25 C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
1
-
Typ
Max
+1
7
Unit
A
ILI
Ci
input leakage current
input capacitance
-
VI = VCC(B)
6
pF
[1] VCC(A) may be as high as 5.5 V for overvoltage tolerance but 0.4VCC(A) + 0.8 V VCC(B) for the channels to be enabled and functional
normally.
[2] For part to function, 0.4 VCC(A) must be equal or less than VCC(B) 0.8 V. The voltage on the A port can still be up to 5.5 V without
damage to the pins.
[3] Pull-up should result in IOL 150 A.
[4] Guaranteed by design and characterization.
[5]
VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.
[6] When VCC(A) is less than 1 V, care is required to make certain that the system ground offset and noise are minimized such that there is
reasonable difference between the VIL present at the PCA9617A A-side input and the 0.25VCC(A) input threshold.
[7] Power supply decoupling capacitors need to be present for both VCC(A) and VCC(B) and the 0.1 F decoupling for VCC(B) needs to be
located near the VCC(B) pin.
002aah461
002aag896
0.70
port B V
0.4
Port A V
OL
OL
(V)
(V)
V
= 2.2 V (Nom = 25 °C)
2.2 V (Hot = 85 °C)
CC(B)
0.65
0.60
0.55
0.50
0.3
V
= 2.2 V (Nom = 25 °C)
2.2 V (Hot = 85 °C)
3.0 V (Hot = 85 °C)
CC(B)
0.2
0.1
0
0
10
20
30
0
10
20
30
port B I (mA)
OL
Port A I (mA)
OL
Fig 10. Port B VOL versus IOL
Fig 11. Port A VOL versus IOL
002aag897
110
Port B
t
(ns)
100
PHL
maximum
typical
90
80
70
minimum
50
100
150
200
C
at constant RC (pF)
L
RC = 67.5 ns, VCC(A) = 0.95 V, VCC(B) = 2.5 V, and Tamb = 25 C.
Fig 12. Nominal port B tPHL with load capacitance at constant RC
PCA9617A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
11 of 23
PCA9617A
NXP Semiconductors
Level translating Fm+ I2C-bus repeater
10. Dynamic characteristics
Table 6.
Dynamic characteristics
V
CC(A) = 0.8 V to 5.5 V[1]; VCC(B) = 2.2 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.[2][3]
Symbol Parameter
Conditions
Min
-42
67
Typ[4]
65
94
Max
103
130
152
-
Unit
ns
tPLH
tPLH2
tPHL
tTLH
SRf
tPLH
tPHL
tTLH
SRf
ten
LOW to HIGH propagation delay
LOW to HIGH propagation delay 2
HIGH to LOW propagation delay
LOW to HIGH output transition time
falling slew rate
port B to port A; Figure 15
port B to port A; Figure 15
port B to port A; Figure 13
port A; Figure 13
[5]
[6]
ns
46
76
ns
-
60
ns
port A; 0.7VCC(A) to 0.3VCC(A)
port A to port B; Figure 14
port A to port B; Figure 14
port B; Figure 14
0.022
40
0.037
60
0.11
102
173
-
V/ns
ns
[7]
[7]
[6]
LOW to HIGH propagation delay
HIGH to LOW propagation delay
LOW to HIGH output transition time
falling slew rate
63
80
ns
-
60
ns
port B; 0.7VCC(B) to 0.3 VCC(B)
0.029
-
0.056
-
0.09
100
V/ns
ns
[8]
[8]
enable time
quiescent 0.3 V;
EN HIGH to enable; Figure 16
tdis
disable time
quiescent + 0.3 V;
-
-
100
ns
EN LOW to disable; Figure 16
[1] 0.4VCC(A) + 0.8 V VCC(B) for the channels to be enabled and function normally.
[2] Times are specified with loads of 1.35 k pull-up resistance and 50 pF load capacitance on port A and port B, and a falling edge slew
rate of 0.05 V/ns input signals.
[3] Pull-up voltages are VCC(A) on port A and VCC(B) on port B.
[4] Typical values were measured with VCC(A) = 0.95 V, VCC(B) = 2.5 V at Tamb = 25 C, unless otherwise noted.
[5] The tPLH2 delay data from port B to port A is measured at 0.45 V on port B to 0.5VCC(A) on port A.
[6] The tTLH of the bus is determined by the pull-up resistance (1.35 k) and the total capacitance (50 pF).
[7] The proportional delay data from port A to port B is measured at 0.5VCC(A) on port A to 0.5VCC(B) on port B.
[8] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
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10.1 AC waveforms
V
V
V
CC(A)
CC(B)
OL
input
0.5V
0.5V
input
0.5V
PHL
0.5V
CC(A)
CC(B)
CC(B)
CC(A)
0.5V
t
t
t
t
PLH
PHL
PLH
V
V
V
CC(B)
CC(A)
OL
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
0.5V
0.5V
CC(B)
0.5V
output
CC(A)
output
CC(A)
CC(B)
t
t
t
t
TLH
THL
TLH
THL
002aag649
002aag650
Fig 13. Propagation delay and transition times;
port B to port A
Fig 14. Propagation delay and transition times;
port A to port B
50 % of V
CC(B)
V
V
CC(B)
OL
input
SDAB, SCLB
input
0.5V
dis
0.5V
CC(B)
CC(B)
0.45 V
PLH2
t
PLH
t
t
en
output
SCLA, SDAA
50 % of V
CC(A)
−0.3 V
EN to output
+0.3 V
output
t
V
OL
002aag651
002aag894
Fig 15. Propagation delay
Fig 16. Enable and disable times
11. Test information
V
CC(B)
V
CC(A)
CC(B)
V
R
L
V
V
O
I
PULSE
GENERATOR
DUT
C
L
R
T
002aab649
RL = load resistor; 1.35 k on port A and port B.
CL = load capacitance includes jig and probe capacitance; 50 pF
RT = termination resistance should be equal to Zo of pulse generators
Fig 17. Test circuit for open-drain outputs
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12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
4
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.05
0.95
0.80
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
5.1
4.7
0.7
0.4
0.70
0.35
6°
0°
mm
1.1
0.65
0.25
0.94
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-04-09
03-02-18
SOT505-1
Fig 18. Package outline SOT505-1 (TSSOP8)
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HWSON8: plastic thermal enhanced very very thin small outline package; no leads;
8 terminals; body 2 x 3 x 0.75 mm
SOT1069-2
X
D
B
A
E
A
2
A
A
1
A
3
terminal 1
index area
detail X
e
1
C
terminal 1
index area
v
w
C
C
A
B
e
b
y
y
C
1
1
4
L
K
E
2
8
5
D
2
0
1
2 mm
K
scale
Dimensions
Unit
(1)
(1)
(1)
A
A
1
A
A
b
D
D
E
E
e
e
L
v
w
y
y
1
2
3
2
2
1
max 0.80 0.05 0.65
mm nom 0.75 0.02 0.55 0.2 0.25 2.0 1.5 3.0 1.5 0.5 1.5 0.35 0.40 0.1 0.05 0.05 0.05
min 0.70 0.00 0.45 0.18 1.9 1.4 2.9 1.4 0.30 0.35
0.30 2.1 1.6 3.1 1.6
0.40 0.45
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1069-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
09-11-18
12-04-18
SOT1069-2
MO-229
Fig 19. Package outline SOT1069-2 (HWSON8)
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 20) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
350
220
< 2.5
235
220
2.5
220
Table 8.
Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Soldering: PCB footprints
3.600
2.950
0.725
0.125
0.125
5.750 3.600
3.200 5.500
1.150
0.600
0.450
0.650
sot505-1_fr
solder lands
occupied area
Dimensions in mm
Fig 21. PCB footprint for SOT505-1 (TSSOP8); reflow soldering
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Footprint information for reflow soldering of HWSON8 package
SOT1069-2
Gx
D
P
C
nSPx
SPx
Hy
Gy
SPy
SLy By
Ay
nSPy
SLx
solder land
solder paste deposit
solder land plus solder paste
occupied area
DIMENSIONS in mm
P
Ay
By
C
D
SLx
1.6
SLy
1.6
SPx
0.6
SPy
0.6
Gx
2.25
Gy
Hy
nSPx nSPy
0.5
3.45
2.2
0.625
0.25
3.25
3.7
1
1
12-02-09
12-02-22
Issue date
sot1069-2_fr
Fig 22. PCB footprint for SOT1069-2 (HWSON8); reflow soldering
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15. Abbreviations
Table 9.
Abbreviations
Description
Charged-Device Model
Acronym
CDM
CMOS
ESD
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
I2C-bus
Inter-Integrated Circuit bus
Input/Output
I/O
PMBus
RC
Power Management Bus
Resistor-Capacitor network
System Management Bus
SMBus
16. Revision history
Table 10. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9617A v.1
20130320
Product data sheet
-
-
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
17.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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19. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
6.1
6.2
Functional description . . . . . . . . . . . . . . . . . . . 5
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Application design-in information . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 13
Test information. . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
10.1
11
12
13
Soldering of SMD packages . . . . . . . . . . . . . . 16
Introduction to soldering . . . . . . . . . . . . . . . . . 16
Wave and reflow soldering . . . . . . . . . . . . . . . 16
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 16
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 17
13.1
13.2
13.3
13.4
14
15
16
Soldering: PCB footprints. . . . . . . . . . . . . . . . 18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 March 2013
Document identifier: PCA9617A
相关型号：
935299998125
HCT SERIES, 1-INPUT INVERT GATE, PDSO5, 1.25 MM, PLASTIC, MO-203, SC-88A, SOT353-1, TSSOP-5
NXP
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