935300331118 [NXP]
HCT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14;
| 型号： | 935300331118 |
| 厂家： | 
NXP |
| 描述： | HCT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC125-Q100; 74HCT125-Q100
Quad buffer/line driver; 3-state
Rev. 2 — 19 January 2015
Product data sheet
1. General description
The 74HC125-Q100; 74HCT125-Q100 is a quad buffer/line driver with 3-state outputs
controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to
assume a high impedance OFF-state. Inputs include clamp diodes which enable the use
of current limiting resistors to interface inputs to voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard no. 7A
Input levels:
The 74HC125-Q100: CMOS levels
The 74HCT125-Q100: TTL levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC125D-Q100
74HCT125D-Q100
74HC125PW-Q100
74HCT125PW-Q100
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width SOT108-1
3.9 mm
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
4. Functional diagram
ꢀ$
ꢀ<
ꢁ<
ꢂ<
ꢄ<
ꢂ
ꢅ
ꢁ
ꢁ
ꢀ
ꢀ2(
ꢁ$
ꢀ
ꢃ
ꢂ
ꢀ
(1ꢀ
ꢃ
ꢅ
ꢄ
ꢁ2(
ꢂ$
ꢄ
ꢆ
ꢈ
ꢆ
ꢈ
ꢂ2(
ꢄ$
ꢀꢇ
ꢀꢁ
ꢀꢇ
Q<
Q$
ꢀꢀ
ꢀꢁ
ꢀꢂ
ꢀꢀ
ꢄ2(
ꢀꢂ
Q2(
PQDꢀꢀꢁ
PQDꢀꢀꢂ
PQDꢀꢀꢃ
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one buffer)
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢂꢃꢄꢅ4ꢂꢆꢆ
ꢀꢁ+&7ꢂꢃꢄꢅ4ꢂꢆꢆ
ꢀ
ꢁ
ꢂ
ꢄ
ꢃ
ꢅ
ꢉ
ꢀꢄ
ꢀꢂ
ꢀꢁ
ꢀꢀ
ꢀꢇ
ꢆ
9
&&
ꢀ2(
ꢀ$
ꢄ2(
ꢄ$
ꢀ<
ꢁ2(
ꢁ$
ꢄ<
ꢂ2(
ꢂ$
ꢁ<
*1'
ꢈ
ꢂ<
DDDꢄꢅꢅꢆꢇꢀꢇ
Fig 4. Pin configuration SO14 and TSSOP14
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
2 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE, 2OE, 3OE, 4OE
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
output enable input (active LOW)
data input
data output
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Control
nOE
Function table[1]
Input
nA
L
Output
nY
L
L
H
H
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
35
+70
70
+150
500
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
65
[1]
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
3 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC125-Q100
74HCT125-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
VI
supply voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
4.5
5.0
5.5
VCC
VCC
V
V
V
input voltage
0
-
0
-
VO
output voltage
0
-
+25
-
0
-
+25
-
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
40
+125 C
-
-
-
-
-
-
-
ns/V
1.67
-
1.67
-
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC125-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 6.0 mA; VCC = 4.5 V 3.98 4.32
IO = 7.8 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.5
-
5.0
-
10.0 A
output current VO = VCC or GND;
VCC = 6.0 V
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
4 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
input
-
3.5
-
pF
capacitance
74HCT125-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 6 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 6.0 mA
0.16 0.26
0.33
1.0
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
0.5
8.0
1.0
A
IOZ
ICC
ICC
OFF-state
VI = VIH or VIL; VCC = 5.5 V;
output current VO = VCC or GND
-
-
-
-
-
-
-
-
5.0
80
-
-
-
10
160
490
A
A
A
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
per input pin;
100
360
450
supply current VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
-
3.5
-
pF
capacitance
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
5 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 7.
Symbol Parameter Conditions
74HC125-Q100
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
[1]
tpd
propagation nA to nY; see Figure 5
delay
VCC = 2.0 V
-
-
-
-
30
11
9
100
20
-
-
-
-
-
125
25
-
-
-
-
-
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
9
17
21
26
[2]
[3]
[4]
[5]
ten
tdis
tt
enable time nOE to nY; see Figure 6
VCC = 2.0 V
-
-
-
41
15
12
125
25
-
-
-
155
31
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
21
26
32
disable time nOE to nY; see Figure 6
VCC = 2.0 V
-
-
-
41
15
12
125
25
-
-
-
155
31
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
21
26
32
transition
time
nY; see Figure 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
14
5
60
12
10
-
-
-
-
-
75
15
13
-
-
-
-
-
90
18
15
-
ns
ns
ns
pF
4
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
22
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
6 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 7.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
74HCT125-Q100
[1]
tpd
propagation nA to nY; see Figure 5
delay
VCC = 4.5 V
-
-
15
12
25
-
-
-
31
-
-
-
38
-
ns
ns
VCC = 5 V; CL = 15 pF
[2]
[3]
ten
enable time nOE to nY; see Figure 6
VCC = 4.5 V
-
15
28
-
35
-
42
ns
tdis
disable time nOE to nY; see Figure 6
VCC = 4.5 V
-
-
15
5
25
12
-
-
31
15
-
-
38
18
ns
ns
[4]
[5]
tt
transition
time
nY; see Figure 5
CPD
power
CL = 50 pF; f = 1 MHz;
-
24
-
-
-
-
-
pF
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] dis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
t
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9
,
9
9
0
0
Q$ꢊLQSXW
*1'
W
W
3/+
3+/
9
2+
ꢆꢇꢊꢋꢊ
9
9
0
0
Q<ꢊRXWSXW
ꢀꢇꢊꢋꢊ
9
2/
W
W
7/+
7+/
DDDꢄꢅꢅꢇꢈꢇꢅ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay input (nA) to output (nY)
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
7 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
9
,
Q2(ꢊLQSXW
RXWSXW
9
0
*1'
W
W
3/=
3=/
9
&&
9
/2:ꢌWRꢌ2))
2))ꢌWRꢌ/2:
0
ꢀꢇꢊꢋ
9
2/
W
W
3+=
3=+
9
2+
ꢆꢇꢊꢋꢊ
RXWSXW
+,*+ꢌWRꢌ2))
9
0
2))ꢌWRꢌ+,*+
*1'
RXWSXWV
HQDEOHG
RXWSXWV
GLVDEOHG
RXWSXWV
HQDEOHG
DDDꢄꢅꢅꢇꢈꢇꢈ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Enable and disable times
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC125-Q100
74HCT125-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
8 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
W
:
9
,
ꢆꢇꢊꢋ
QHJDWLYHꢊ
SXOVH
9
9
9
0
0
0
ꢀꢇꢊꢋ
ꢇꢊ9
W
W
U
I
W
W
U
I
9
,
ꢆꢇꢊꢋ
SRVLWLYHꢊ
SXOVH
9
0
ꢀꢇꢊꢋ
ꢇꢊ9
W
:
9
9
&&
&&
9
,
9
2
ꢊ
5
/
6ꢀ
*
RSHQ
'87
5
7
&
/
ꢅꢅꢈDDGꢂꢁꢇ
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC125-Q100
VCC
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT125-Q100 3 V
open
GND
VCC
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
9 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
12. Package outline
62ꢂꢁꢌꢇSODVWLFꢇVPDOOꢇRXWOLQHꢇSDFNDJHꢍꢇꢂꢁꢇOHDGVꢍꢇERG\ꢇZLGWKꢇꢉꢈꢎꢇPPꢇ
627ꢂꢆꢏꢅꢂꢇ
'ꢊ
(ꢊ
$ꢊ
;ꢊ
Fꢊ
\ꢊ
+ꢊ
(ꢊ
Yꢊ 0ꢊ
$ꢊ
=ꢊ
ꢈꢊ
ꢀꢄꢊ
4ꢊ
$ꢊ
ꢁꢊ
$ꢊ
ꢎ$ꢊꢊꢏꢊ
ꢂꢊ
$ꢊ
ꢀꢊ
SLQꢊꢀꢊLQGH[ꢊ
șꢊ
/ꢊ
Sꢊ
/ꢊ
ꢀꢊ
ꢉꢊ
Hꢊ
GHWDLOꢊ;ꢊ
Zꢊ 0ꢊ
Eꢊ
Sꢊ
ꢇꢊ
ꢁꢍꢃꢊ
VFDOHꢊ
ꢃꢊPPꢊ
',0(16,216ꢇꢊLQFKꢇGLPHQVLRQVꢇDUHꢇGHULYHGꢇIURPꢇWKHꢇRULJLQDOꢇPPꢇGLPHQVLRQVꢋꢇ
$ꢇ
ꢊꢂꢋꢇ
ꢊꢂꢋꢇ
ꢊꢂꢋꢇ
81,7ꢇ
$ꢇ
ꢂꢇ
$ꢇ
ꢃꢇ
$ꢇ
ꢉꢇ
Eꢇ
Sꢇ
Fꢇ
'ꢇ
(ꢇ
Hꢇ
+ꢇ
(ꢇ
/ꢇ
/ꢇ
Sꢇ
4ꢇ
Yꢇ
Zꢇ
\ꢇ
=ꢇ
șꢊ
PD[ꢈꢇ
ꢇꢍꢁꢃꢊ ꢀꢍꢄꢃꢊ
ꢇꢍꢀꢇꢊ ꢀꢍꢁꢃꢊ
ꢇꢍꢄꢆꢊ ꢇꢍꢁꢃꢊ ꢈꢍꢉꢃꢊ
ꢇꢍꢂꢅꢊ ꢇꢍꢀꢆꢊ ꢈꢍꢃꢃꢊ
ꢄꢍꢇꢊ
ꢂꢍꢈꢊ
ꢅꢍꢁꢊ
ꢃꢍꢈꢊ
ꢊ
ꢀꢍꢇꢊ
ꢇꢍꢄꢊ
ꢇꢍꢉꢊ
ꢇꢍꢅꢊ
ꢇꢍꢉꢊ
ꢇꢍꢂꢊ
PPꢊ
ꢀꢍꢉꢃꢊ
ꢀꢍꢁꢉꢊ
ꢇꢍꢇꢃꢊ
ꢀꢍꢇꢃꢊ
ꢇꢍꢁꢃꢊ ꢇꢍꢁꢃꢊ
ꢇꢍꢀꢊ
ꢇꢍꢁꢃꢊ
ꢇꢍꢇꢀꢊ
Rꢊ
ꢈꢊ
Rꢊ
ꢇꢊ
ꢇꢍꢇꢀꢇꢊ ꢇꢍꢇꢃꢉꢊ
ꢇꢍꢇꢇꢄꢊ ꢇꢍꢇꢄꢆꢊ
ꢇꢍꢇꢀꢆꢊ ꢇꢍꢇꢀꢇꢇꢊ ꢇꢍꢂꢃꢊ ꢇꢍꢀꢅꢊ
ꢇꢍꢇꢀꢄꢊ ꢇꢍꢇꢇꢉꢃꢊ ꢇꢍꢂꢄꢊ ꢇꢍꢀꢃꢊ
ꢇꢍꢁꢄꢄꢊ
ꢇꢍꢁꢁꢈꢊ
ꢇꢍꢇꢂꢆꢊ ꢇꢍꢇꢁꢈꢊ
ꢇꢍꢇꢀꢅꢊ ꢇꢍꢇꢁꢄꢊ
ꢇꢍꢇꢁꢈꢊ
ꢇꢍꢇꢀꢁꢊ
LQFKHVꢊ
ꢇꢍꢇꢄꢀꢊ
ꢇꢍꢇꢀꢊ ꢇꢍꢇꢀꢊ ꢇꢍꢇꢇꢄꢊ
ꢇꢍꢇꢅꢆꢊ
1RWHꢇ
ꢀꢍꢊ3ODVWLFꢊRUꢊPHWDOꢊSURWUXVLRQVꢊRIꢊꢇꢍꢀꢃꢊPPꢊꢎꢇꢍꢇꢇꢅꢊLQFKꢏꢊPD[LPXPꢊSHUꢊVLGHꢊDUHꢊQRWꢊLQFOXGHGꢍꢊꢊ
ꢇ5()(5(1&(6ꢇ
ꢇ-('(&ꢇ ꢇ-(,7$ꢇ
ꢊ06ꢌꢇꢀꢁꢊ
287/,1(ꢇ
9(56,21ꢇ
(8523($1ꢇ
352-(&7,21ꢇ
,668(ꢇ'$7(ꢇ
ꢇ,(&ꢇ
ꢆꢆꢌꢀꢁꢌꢁꢉꢊ
ꢇꢂꢌꢇꢁꢌꢀꢆꢊ
ꢊ627ꢀꢇꢈꢌꢀꢊ
ꢊꢇꢉꢅ(ꢇꢅꢊ
Fig 8. Package outline SOT108-1 (SO14)
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
10 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
76623ꢂꢁꢌꢇSODVWLFꢇWKLQꢇVKULQNꢇVPDOOꢇRXWOLQHꢇSDFNDJHꢍꢇꢂꢁꢇOHDGVꢍꢇERG\ꢇZLGWKꢇꢁꢈꢁꢇPPꢇ
627ꢁꢆꢃꢅꢂꢇ
'ꢊ
(ꢊ
$ꢊ
;ꢊ
Fꢊ
\ꢊ
+ꢊ
(ꢊ
Yꢊ 0ꢊ
$ꢊ
=ꢊ
ꢈꢊ
ꢀꢄꢊ
4ꢊ
ꢎ$ꢊꢊꢏꢊ
ꢂꢊ
$ꢊ
ꢁꢊ
$ꢊ
$ꢊ
ꢀꢊ
SLQꢊꢀꢊLQGH[ꢊ
șꢊ
/ꢊ
Sꢊ
/ꢊ
ꢀꢊ
ꢉꢊ
GHWDLOꢊ;ꢊ
Zꢊ 0ꢊ
Eꢊ
Sꢊ
Hꢊ
ꢇꢊ
ꢁꢍꢃꢊ
ꢃꢊPPꢊ
VFDOHꢊ
',0(16,216ꢇꢊPPꢇDUHꢇWKHꢇRULJLQDOꢇGLPHQVLRQVꢋꢇ
$ꢇ
ꢊꢂꢋꢇ
ꢊꢃꢋꢇ
ꢊꢂꢋꢇ
81,7ꢇ
PPꢊ
$ꢇ
ꢂꢇ
$ꢇ
ꢃꢇ
$ꢇ
ꢉꢇ
Eꢇ
Sꢇ
Fꢇ
'ꢇ
(ꢇ
Hꢇ
+ꢇ
/ꢇ
/ꢇ
Sꢇ
4ꢇ
Yꢇ
Zꢇ
\ꢇ
ꢇꢍꢀꢊ
=ꢇ
șꢊ
(ꢇ
PD[ꢈꢇ
Rꢊ
ꢇꢍꢀꢃꢊ ꢇꢍꢆꢃꢊ
ꢇꢍꢇꢃꢊ ꢇꢍꢈꢇꢊ
ꢇꢍꢂꢇꢊ
ꢇꢍꢀꢆꢊ
ꢇꢍꢁꢊ
ꢇꢍꢀꢊ
ꢃꢍꢀꢊ
ꢄꢍꢆꢊ
ꢄꢍꢃꢊ
ꢄꢍꢂꢊ
ꢅꢍꢅꢊ
ꢅꢍꢁꢊ
ꢇꢍꢉꢃꢊ
ꢇꢍꢃꢇꢊ
ꢇꢍꢄꢊ
ꢇꢍꢂꢊ
ꢇꢍꢉꢁꢊ
ꢇꢍꢂꢈꢊ
ꢈꢊ
ꢀꢍꢀꢊ
ꢇꢍꢅꢃꢊ
ꢀꢊ
ꢇꢍꢁꢊ ꢇꢍꢀꢂꢊ
ꢇꢍꢁꢃꢊ
Rꢊ
ꢇꢊ
1RWHVꢇ
ꢀꢍꢊ3ODVWLFꢊRUꢊPHWDOꢊSURWUXVLRQVꢊRIꢊꢇꢍꢀꢃꢊPPꢊPD[LPXPꢊSHUꢊVLGHꢊDUHꢊQRWꢊLQFOXGHGꢍꢊ
ꢁꢍꢊ3ODVWLFꢊLQWHUOHDGꢊSURWUXVLRQVꢊRIꢊꢇꢍꢁꢃꢊPPꢊPD[LPXPꢊSHUꢊVLGHꢊDUHꢊQRWꢊLQFOXGHGꢍꢊ
ꢇ5()(5(1&(6ꢇ
ꢇ-('(&ꢇ ꢇ-(,7$ꢇ
ꢊ02ꢌꢀꢃꢂꢊ
287/,1(ꢇ
9(56,21ꢇ
(8523($1ꢇ
352-(&7,21ꢇ
,668(ꢇ'$7(ꢇ
ꢇ,(&ꢇ
ꢆꢆꢌꢀꢁꢌꢁꢉꢊ
ꢇꢂꢌꢇꢁꢌꢀꢈꢊ
ꢊ627ꢄꢇꢁꢌꢀꢊ
Fig 9. Package outline SOT402-1 (TSSOP14)
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
11 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
LSTTL
ESD
Description
Complementary Metal Oxide Semiconductor
Low-power Schottky Transistor-Transistor Logic
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
MIL
Military
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT125_Q100 v.2 20150119
Product data sheet
-
74HC_HCT125_Q100 v.1
Modifications:
• Table 7: Power dissipation capacitance condition for 74HCT125-Q100 is corrected.
74HC_HCT125_Q100 v.1 20130226
Product data sheet
-
-
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
12 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
13 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2015
14 of 15
74HC125-Q100; 74HCT125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 January 2015
Document identifier: 74HC_HCT125_Q100
相关型号：
935300337118
HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16
NXP
935300346118
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 5.30 MM, PLASTIC, MO-150, SOT338-1, SSOP-16
NXP
935300347118
HCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 5.30 MM, PLASTIC, MO-150, SOT338-1, SSOP-16
NXP
935300349118
HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16
NXP
935300396118
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16
NXP
935300692125
AHC/VHC/H/U/V SERIES, 2-INPUT NAND GATE, PDSO5, 1.25 MM, PLASTIC, MO-203, SC-88A, SOT353-1, TSSOP-5
NXP
©2020 ICPDF网 联系我们和版权申明