935301419118 [NXP]
IC MUX 6CH DISPLAY PORT 50TFBGA;
| 型号： | 935301419118 |
| 厂家： | 
NXP |
| 描述： | IC MUX 6CH DISPLAY PORT 50TFBGA |
| 文件： | 总19页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBTL06GP213
Second-generation high performance general purpose switch
Rev. 3.1 — 13 December 2016
Product data sheet
1. General description
The CBTL06GP213 is a six-channel (‘hex’) multiplexer for DisplayPort, HDMI and
PCI Express applications at Generation 2 (‘Gen2’) speeds. It provides four differential
channels capable of 1 : 2 switching or 2 : 1 multiplexing bidirectional, AC-coupled
PCI Express, DisplayPort signals, USB3 SuperSpeed or DC coupled TMDS signals, using
high-bandwidth pass-gate technology. It provides support for high common-mode/bias
voltage on the high-speed differential channels. Additionally, it provides for
switching/multiplexing of the Hot Plug Detect signal as well as the AUX or DDC (Display
Data Channel) signals, for a total of six channels on the display side. The AUX and DDC
channels provide a four-position multiplexer such that an additional level of multiplexing
can be accomplished when AUX and DDC I/Os are on separate pins of the display source
device.
The CBTL06GP213 is designed for Gen2 speeds, supporting 5.0 Gbit/s for PCI Express,
5.4 Gbit/s for DisplayPort or 6 Gbit/s for HDMI 2.0. It consumes 490 A current (typical) in
operational mode and provides a shutdown function to support battery-powered
applications.
A typical application of CBTL06GP213 is on applications where one of two GPU display
sources must be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth pass gate
technology), the CBTL06GP213 can also be used in the reverse topology, for example, to
connect one display source device to one of two display sink devices or connectors.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) PCI Express
(v2.0 - 5.0 Gbit/s) signals, USB3 SuperSpeed or HDMI 2.0 (6 Gbit/s) TMDS signals
4 high-speed differential channels with 2 : 1 muxing/switching for DisplayPort or
PCI Express or HDMI signals
1 channel with 4 : 1 or 4 : 2 muxing/switching for AUX at 1 Mbit/s or DDC signals,
USB2 signals
1 channel with 2 : 1 muxing/switching for single-ended HPD signal
High-bandwidth analog pass-gate technology
Supports high-speed signal switching over a wide common-mode range and
differential swing
RON on DP high-speed channels: 7
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
Low insertion loss:
0.9 dB at 100 MHz
1.1 dB at 1.35 GHz
1.3 dB at 2.7 GHz
3 dB bandwidth at 9.5 GHz
Low crosstalk: 32 dB at 2.7 GHz
Low off-state isolation: 23 dB at 2.7 GHz
Low return loss: 19 dB at 2.7 GHz
Very low intra-pair skew (5 ps typical)
Very low inter-pair skew (< 80 ps)
Switch/multiplexer position select CMOS input
Shutdown mode CMOS input
Supports backdrive protection
Single 3.3 V power supply
Operation current of 490 A typical, shut-down current 10 A maximum
ESD 2 kV HBM, 500 V CDM
Available in 5 mm 5 mm, 0.5 mm ball pitch TFBGA50 package
3. Applications
Motherboard applications requiring DisplayPort, HDMI, PCI Express, and USB
switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Type number
Topside Solder process
marking
Package
Name
Description
Version
CBTL06GP213EE[1] GP213
Pb-free (SnAgCu TFBGA50 plastic thin fine-pitch ball grid array package; SOT1345-1
solder compound)
50 balls; body 5 5 0.8 mm[2]
[1] Industrial temperature range.
[2] Total height including solder balls after printed circuit board mounting = 1.15 mm.
For more information on product marking, refer to
www.nxp.com/products/related/package-markings.html.
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
2 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
Package Packing method
Minimum
Temperature
part number
order quantity
CBTL06GP213EE CBTL06GP213EEJ TFBGA50 Reel 13” Q1/T1
*standard mark SMD
3000
Tamb = 40 C to +105 C
5. Functional diagram
VDD
4
4
DIN1_n+
DIN1_n−
4
DOUT_n+
DOUT_n−
DP
MUX
DIN2_n+
DIN2_n−
DAUX1+
DAUX1−
AUX+ or SCL
AUX− or SDA
AUX+
AUX−
DAUX2+
DAUX2−
AUX/
DDC
MUX
DDC_CLK1
DDC_DAT1
DDC_CLK
DDC_DAT
DDC_CLK2
DDC_DAT2
HPD_1
HPD_2
HPD
MUX
HPDIN
GPU_SEL
DDC_AUX_SEL
XSD
GND
002aah658
Fig 1. Functional diagram
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
3 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL06GP213EE
1
2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aah659
Transparent top view
Fig 2. Pin configuration for TFBGA50
1
2
3
4
5
6
7
8
9
GPU_SEL
A
B
C
D
E
F
VDD
DIN1_0−
DIN1_1−
DIN1_2−
DIN1_3+
DIN1_3−
DOUT_0−
DOUT_0+
GND
DIN1_0+
DIN1_1+
DIN1_2+
XSD
DIN2_0+
GND
DIN2_0−
DDC_AUX
_SEL
DOUT_1−
DOUT_2−
DOUT_3−
DOUT_1+
DOUT_2+
DOUT_3+
GND
DIN2_1+
DIN2_2+
DIN2_3+
GND
DIN2_1−
DIN2_2−
DIN2_3−
G
H
J
AUX−
AUX+
HPD_2
GND
VDD
DDC_CLK2 DAUX2+
GND
DDC_CLK1 DAUX1+
HPDIN
HPD_1
DDC_CLK
DDC_DAT2 DAUX2− DDC_DAT DDC_DAT1 DAUX1−
002aah660
Transparent top view
Fig 3. Ball mapping
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
4 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
6.2 Pin description
Table 3.
Symbol
GPU_SEL
Pin description
Ball
A1
Type
Description
3.3 V CMOS
single-ended input
Selects between two multiplexer/switch paths. When HIGH,
path 2 left-side is connected to its corresponding right-side I/O.
When LOW, path 1 left-side is connected to its corresponding
right-side I/O. Refer to Table 6 for switch connection details.
DDC_AUX_SEL C2
3.3 V CMOS
single-ended input
Tri-level select pin. Selects between DDC and AUX paths.
When HIGH, the AUX+ and AUX I/Os are connected to
appropriate DDC terminals. When LOW, the AUX+ and AUX
I/Os are connected to their appropriate AUX terminals. When
MID, AUX and DDC terminals are connected to the AUX+/
and DDC_CLK/DAT I/Os respectively. Refer to Table 6 for
switch connection details.
XSD
B7
3.3 V CMOS
single-ended input
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting high-impedance state) and supply current
consumption is minimized.
DIN1_0+
DIN1_0
DIN1_1+
DIN1_1
DIN1_2+
DIN1_2
DIN1_3+
DIN1_3
DIN2_0+
DIN2_0
DIN2_1+
DIN2_1
DIN2_2+
DIN2_2
DIN2_3+
DIN2_3
DOUT_0+
DOUT_0
DOUT_1+
DOUT_1
DOUT_2+
DOUT_2
DOUT_3+
DOUT_3
DAUX1+
DAUX1
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
F9
B2
B1
D2
D1
E2
E1
F2
F1
H9
J9
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
Four high-speed differential pairs for DisplayPort, PCI Express
or HDMI, USB3 signals, path 1, left-side.
Four high-speed differential pairs for DisplayPort, PCI Express
or HDMI, USB3 signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort, PCI Express
or HDMI, USB3 signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
5 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
Table 3.
Symbol
DAUX2+
DAUX2
DDC_CLK
DDC_DAT
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
AUX+
Pin description …continued
Ball
H6
J6
Type
Description
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
single-ended I/O
single-ended I/O
power supply
High-speed differential pair for AUX signals, path 2, left-side.
J3
Pair of single-ended terminals for DDC clock and data signals,
right-side.
J7
H8
J8
Pair of single-ended terminals for DDC clock and data signals,
path 1, left-side.
H5
J5
Pair of single-ended terminals for DDC clock and data signals,
path 2, left-side.
H2
H1
J2
High-speed differential pair for AUX or single-ended DDC
signals, right-side.
AUX
HPD_1
Single ended channel for the HPD signal, path 1, left-side.
Single ended channel for the HPD signal, path 2, left-side.
Single ended channel for the HPD signal, right-side.
3.3 V power supply.
HPD_2
H3
J1
HPDIN
VDD
A2, J4
GND
B3, C8, G2, ground
G8, H4, H7
Ground.
7. Functional description
Refer to Figure 1 “Functional diagram”.
The CBTL06GP213 uses a 3.3 V power supply. All main signal paths are implemented
using high-bandwidth pass-gate technology and are non-directional. No clock or reset
signal is needed for the multiplexer to function.
The switch position for the main channels is selected using the select signal GPU_SEL.
Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the
DDC / AUX channel. The detailed operation is described in Section 7.1.
7.1 Multiplexer/switch select functions
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and
DDC_AUX_SEL as described below.
Table 4.
Multiplexer/switch select control for DIN and DOUT channels
GPU_SEL
DIN1_n
DIN2_n
0
1
active; connected to DOUT_n
high-impedance
high-impedance
active; connected to DOUT_n
Table 5.
Multiplexer/switch select control for HPD channel
GPU_SEL
HPD1
HPD2
0
1
active; connected to HPDIN
high-impedance
high-impedance
active; connected to HPDIN
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
6 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
Table 6.
Multiplexer/switch select control for DDC and AUX channels
DDC_AUX_SEL GPU_SEL
DAUX1
DAUX2
DDC1
DDC2
LOW
LOW
HIGH
HIGH
MID
LOW
HIGH
LOW
HIGH
LOW
HIGH
active;
connected to AUX
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
active;
connected to AUX
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
active;
connected to AUX
high-Z
active;
connected to AUX
active;
connected to AUX
active;
connected to DDC
high-Z
MID
high-Z
active;
high-Z
active;
connected to AUX
connected to DDC
The voltage thresholds for the different pin settings — LOW, MID and HIGH — are given
in Table 14.
7.2 Shutdown function
The CBTL06GP213 provides a shutdown function to minimize power consumption when
the application is not active but CBTL06GP213 can remain powered. Pin XSD (active
LOW) puts all channels in off mode (non-conducting high-impedance state) while reducing
current consumption to near-zero.
Table 7.
Shutdown function
State
XSD
0
1
shutdown
active
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
7 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
8. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
0.3
0.3
Max
+4.6
+4.0
Unit
V
VDD
VI
supply voltage
input voltage
DDC_AUX_SEL, GPU_SEL,
XSD, DINx_n, DOUT_n
V
AUX1, AUX2, AUX, DDC1,
DDC2, DDC, HPD
0.3
+6.0
V
Tstg
storage temperature
65
+150
2000
500
C
V
[1]
[2]
VESD
electrostatic discharge HBM
voltage
-
-
CDM
V
[1] Human Body Model: ANSI/ESDAJEDEC JDS-001-2012 (Revision of ANSI/ESDA/JECEC JS-001-2011),
ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model - Component level;
Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association,
Arlington, VA, USA.
[2] Charged Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008),
standard for ESD sensitivity testing, Charged Device Model - Component level; JEDEC Solid State
Technology Association, Arlington, VA, USA.
9. Recommended operating conditions
Table 9.
Recommended operating conditions
Symbol Parameter
Conditions
Min
3.0
Typ
3.3
-
Max
Unit
V
VDD
VI
supply voltage
input voltage
3.6
DDC_AUX_SEL,
GPU_SEL, XSD
0.3
VDD + 0.3
V
DINx_n, DOUT_n
0.3
0.3
-
-
+4.0
+5.5
V
V
AUX1, AUX2, AUX,
DDC1, DDC2, DDC,
HPD
Tamb
ambient temperature operating in free air
40
-
+105
C
10. Characteristics
10.1 General characteristics
Table 10. General characteristics
Symbol Parameter
Conditions
Min
Typ
490
-
Max
Unit
A
IDD
supply current
operating mode (XSD = HIGH)
shutdown mode (XSD = LOW)
operating mode (XSD = HIGH)
-
-
-
-
-
15
-
A
Pcons
power consumption
start-up time
1.6
-
mW
ms
tstartup
supply voltage valid or XSD going HIGH to
channel specified operating characteristics
5
trcfg
reconfiguration time
GPU_SEL or DDC_AUX_SEL state change
to channel specified operating characteristics
-
-
10
s
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
8 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
10.2 DisplayPort channel characteristics
Table 11. DisplayPort channel characteristics
Symbol Parameter Conditions
Min
0.3
0
Typ
Max
+4.0
3.6
Unit
V
VI
input voltage
-
-
-
VIC
VID
RON
common-mode input voltage
differential input voltage
ON resistance
V
peak-to-peak
-
+1.4
V
VDD = 3.3 V; II = 20 mA
VIC = 0 V to 2 V
-
-
-
-
-
-
-
-
-
7
10
10
-
VIC = 2 V to 3.6 V
channel is ON; f 100 MHz
channel is ON; f = 1.35 GHz
channel is ON; f = 2.7 GHz
channel is OFF; f = 2.7 GHz
f = 100 MHz
8
DDIL
differential insertion loss
differential return loss
0.9
1.1
1.3
23
22
21
19
dB
dB
dB
dB
dB
dB
dB
-
-
-
DDRL
-
f = 1.35 GHz
-
f = 2.7 GHz
-
DDNEXT differential near-end crosstalk
adjacent channels are ON
f = 100 MHz
-
-
-
-
50
32
9.5
80
-
-
-
-
dB
f = 2.7 GHz
dB
B
bandwidth
3.0 dB intercept
GHz
ps
tPD
propagation delay
from left-side port to right-side port
or vice versa
tsk(dif)
tsk
differential skew time
skew time
intra-pair
inter-pair
-
-
-
-
-
5
-
8
ps
80
10
10
10
ps
ILIH
HIGH-level input leakage current VDD = 3.3 V; VI = 4.0 V
VDD = 0 V; VI = 4.0 V
-
A
A
A
-
ILIL
LOW-level input leakage current VDD = 3.3 V; VI = GND
-
All S-parameter measurements are with respect to 100 differential impedance
reference, 50 single-ended impedance reference. DDIL and DDRL measurements are
with Common-mode voltage of 3 V.
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
9 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
10.3 AUX and DDC ports
Table 12. AUX and DDC port characteristics
Symbol Parameter Conditions
VI input voltage
Vbias(DC) bias voltage (DC)
Min
0.3
0
Typ
Max
+5.5
3.3
Unit
V
-
-
-
AUX
V
Vi(dif)
RON
differential input voltage
AUX; single-ended swing
AUX path; VDD = 3.3 V; II = 20 mA
VIC = 0 V to 3.3 V
-
0.7
V
ON resistance
-
-
4.7
6.5
-
-
VIC = 3.3 V to 5.25 V
DDC path; VDD = 3.3 V; II = 20 mA
VIC = 0 V to 3.3 V
-
-
6.5
8.5
-
-
VIC = 3.3 V to 5.25 V
on AUX/DDC ports
DDIL
differential insertion loss
differential return loss
channel is ON; f 100 MHz
channel is ON; f = 240 MHz
channel is ON; f = 720 MHz
channel is OFF; f = 240 MHz
on AUX/DDC ports
-
-
-
-
0.7
1.0
1.2
38
-
-
-
-
dB
dB
dB
dB
DDRL
f = 100 MHz
-
-
-
-
21
16
12
80
-
-
-
-
dB
dB
dB
ps
f = 240 MHz
f = 720 MHz
[1]
tPD
propagation delay
from left-side port to right-side port
or vice versa
tsk(dif)
ILIH
differential skew time
intra-pair skew on AUX
-
-
-
10
-
-
ps
HIGH-level input leakage current VDD = 3.3 V; VI = 4.0 V
LOW-level input leakage current VDD = 3.3 V; VI = GND
10
+10
A
A
ILIL
-
[1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
V
i(dif)
DAUX1, DAUX2, AUX
GND (0 V)
V
bias(DC)
002aag605
Fig 4. DAUX1, DAUX2 and AUX input voltage waveform
All S-parameter measurements are with respect to 100 differential impedance reference
and 50 single-ended impedance reference.
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
10 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
10.4 HPDIN input, HPD_x outputs
Table 13. HPD input and output characteristics
Symbol Parameter Conditions
Min
Typ
Max
Unit
VI
input voltage
0.3
-
+5.5
V
RON
ON resistance
VDD = 3.3 V; II = 20 mA
VIC = 0 V to 3.3 V
-
-
-
-
-
5
-
VIC = 3.3 V to 5.5 V
VDD = 3.3 V; VI = 4.0 V
VDD = 3.3 V; VI = GND
6.5
-
ILIH
ILIL
tPD
HIGH-level input leakage current
LOW-level input leakage current
propagation delay
-
10
+10
-
A
A
ps
-
[1]
from HPDIN to HPD_x or
vice versa
100
[1] Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time.
10.5 GPU_SEL, DDC_AUX_SEL, XSD inputs
Table 14. GPU_SEL, DDC_AUX_SEL, XSD input characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
HIGH-level;
GPU_SEL, DDC_AUX_SEL, XSD
0.7 VDD
-
-
-
-
-
-
-
V
MID-level;
DDC_AUX_SEL
0.45 VDD
0.55 VDD
0.2 VDD
10
V
LOW-level;
GPU_SEL, DDC_AUX_SEL, XSD
-
-
-
-
V
ILI
input leakage current
HIGH-level;
VDD = 3.3 V; HIGH-level VI = 3.6 V
A
A
A
MID-level;
10
V
DD = 3.3 V; MID-level VI = 0.55 VDD
LOW-level;
+10
VDD = 3.3 V; LOW-level VI = GND
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
11 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
11. Package outline
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Fig 5. Package outline TFBGA50 (SOT1345-1)
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
12 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
13 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 6) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 15 and 16
Table 15. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 16. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 6.
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
14 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 6. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13. Abbreviations
Table 17. Abbreviations
Acronym
AUX
Description
Auxiliary channel (in DisplayPort definition)
Display Data Channel
DDC
DVI
Digital Video Interface
GPU
HDMI
HPD
Graphics Processor Unit
High-Definition Multimedia Interface
Hot Plug Detect
PCB
Printed-Circuit Board
PCIe
PCI Express
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
15 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
14. Revision history
Table 18. Revision history
Document ID
Release date
20161213
Data sheet status
Change notice
Supersedes
CBTL06GP213 v.3.1
Modifications:
Product data sheet
-
CBTL06GP213 v.3
• Section 1 and Section 2: Updated HDMI spec from 1.4b to 2.0
CBTL06GP213 v.3
CBTL06GP213 v.2
CBTL06GP213 v.1
20140627
20140217
20130830
Product data sheet
Product data sheet
Product data sheet
-
-
-
CBTL06GP213 v.2
CBTL06GP213 v.1
-
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
16 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
17 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
15.4 Licenses
Purchase of NXP ICs with HDMI technology
non-automotive qualified products in automotive equipment or applications.
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
admin@hdmi.org.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTL06GP213
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
18 of 19
CBTL06GP213
NXP Semiconductors
Second-generation high performance general purpose switch
17. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
7.2
Functional description . . . . . . . . . . . . . . . . . . . 6
Multiplexer/switch select functions . . . . . . . . . . 6
Shutdown function . . . . . . . . . . . . . . . . . . . . . . 7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
10
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
General characteristics. . . . . . . . . . . . . . . . . . . 8
DisplayPort channel characteristics . . . . . . . . . 9
AUX and DDC ports . . . . . . . . . . . . . . . . . . . . 10
HPDIN input, HPD_x outputs . . . . . . . . . . . . . 11
GPU_SEL, DDC_AUX_SEL, XSD inputs . . . . 11
10.1
10.2
10.3
10.4
10.5
11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
12
Soldering of SMD packages . . . . . . . . . . . . . . 13
Introduction to soldering . . . . . . . . . . . . . . . . . 13
Wave and reflow soldering . . . . . . . . . . . . . . . 13
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 13
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 14
12.1
12.2
12.3
12.4
13
14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.1
15.2
15.3
15.4
15.5
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 December 2016
Document identifier: CBTL06GP213
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